From patchwork Thu Aug 19 10:56:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 12446839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA0B8C4338F for ; Thu, 19 Aug 2021 10:58:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FA8560F4C for ; Thu, 19 Aug 2021 10:58:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8FA8560F4C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=CxgmtQkSOgzKdXuG4Jcg3+kHg5CsLWfHGJ5s6G1jpTg=; b=JpmS5TuqrIUUET Dwm5Lh9lPns05oXI7l7Ns1Be2XMadf5wCuQJRNaccRR3BeGVlDqdH7HomFlp1OLHax/l6p3Chyh/+ kG2C7lOkvxvG1G2Ztz5mlN+4ZgHq/6t24ibfoWckPg9o6KRXVLz2+u//Kn/J6cFNNIS4TGJFkXbvO X8XNBQ9T3P2DVNqYxCNcqYR8Bld3rV7wJyV59WTX9rIdMFSLPf5t1df4tJzt8IPEY1LdhTuj37rIk Jmq/BqRLtdVFOL1Gw/cTeriqZJbS+KOOVjtUxWhoyqrkxdk47dw9PkYo1m+tekYzFBJMi1hFnvN3B i9yfU3xjcp9IbYUD4Dqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGfj9-0082aO-9c; Thu, 19 Aug 2021 10:56:51 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGfiv-0082Y3-1F for linux-arm-kernel@lists.infradead.org; Thu, 19 Aug 2021 10:56:38 +0000 Received: from unknown (HELO iyokan2-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 19 Aug 2021 19:56:34 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan2-ex.css.socionext.com (Postfix) with ESMTP id 3B8852083C46; Thu, 19 Aug 2021 19:56:34 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 19 Aug 2021 19:56:34 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 0560CB631E; Thu, 19 Aug 2021 19:56:34 +0900 (JST) From: Kunihiko Hayashi To: =?unknown-8bit?q?Lorenzo_Pieralisi_=3Clorenzo=2Epieralisi=40arm=2Ecom=3E?= =?unknown-8bit?q?=2C_Rob_Herring_=3Crobh=40kernel=2Eorg=3E=2C_Krzysztof_Wil?= =?unknown-8bit?q?czy=8F=AB=CDski__=3Ckw=40linux=2Ecom=3E=2C_Bjorn_Helgaas_?= =?unknown-8bit?q?=3Cbhelgaas=40google=2Ecom=3E?= Cc: =?unknown-8bit?q?Pali_Roh=8F=AB=A1r__=3Cpali=40kernel=2Eorg=3E=2C_Masami?= =?unknown-8bit?q?_Hiramatsu_=3Cmhiramat=40kernel=2Eorg=3E=2C_linux-pci=40vg?= =?unknown-8bit?q?er=2Ekernel=2Eorg=2C_linux-arm-kernel=40lists=2Einfradead?= =?unknown-8bit?q?=2Eorg=2C_linux-kernel=40vger=2Ekernel=2Eorg=2C_Kunihiko_H?= =?unknown-8bit?q?ayashi_=3Chayashi=2Ekunihiko=40socionext=2Ecom=3E?= Subject: [PATCH] PCI: uniphier: Take lock in INTX irq_{mask, unmask, ack} callbacks Date: Thu, 19 Aug 2021 19:56:06 +0900 Message-Id: <1629370566-29984-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210819_035637_277982_F2FD2992 X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The same condition register PCI_RCV_INTX is used in irq_mask(), irq_unmask() and irq_ack() callbacks. Accesses to register can occur at the same time without lock. This introduces a lock into the callbacks to prevent the issue. Fixes: 7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support") Suggested-by: Pali Rohár Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index ebe43e9..5075714 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -186,12 +186,17 @@ static void uniphier_pcie_irq_ack(struct irq_data *d) struct pcie_port *pp = irq_data_get_irq_chip_data(d); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + unsigned long flags; u32 val; + raw_spin_lock_irqsave(&pp->lock, flags); + val = readl(priv->base + PCL_RCV_INTX); val &= ~PCL_RCV_INTX_ALL_STATUS; val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT); writel(val, priv->base + PCL_RCV_INTX); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } static void uniphier_pcie_irq_mask(struct irq_data *d) @@ -199,12 +204,17 @@ static void uniphier_pcie_irq_mask(struct irq_data *d) struct pcie_port *pp = irq_data_get_irq_chip_data(d); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + unsigned long flags; u32 val; + raw_spin_lock_irqsave(&pp->lock, flags); + val = readl(priv->base + PCL_RCV_INTX); val &= ~PCL_RCV_INTX_ALL_MASK; val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); writel(val, priv->base + PCL_RCV_INTX); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } static void uniphier_pcie_irq_unmask(struct irq_data *d) @@ -212,12 +222,17 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d) struct pcie_port *pp = irq_data_get_irq_chip_data(d); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + unsigned long flags; u32 val; + raw_spin_lock_irqsave(&pp->lock, flags); + val = readl(priv->base + PCL_RCV_INTX); val &= ~PCL_RCV_INTX_ALL_MASK; val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); writel(val, priv->base + PCL_RCV_INTX); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } static struct irq_chip uniphier_pcie_irq_chip = {