From patchwork Thu Aug 19 12:59:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 12447169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EE36C4338F for ; Thu, 19 Aug 2021 13:00:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06E3261152 for ; Thu, 19 Aug 2021 13:00:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 06E3261152 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=L8bT6SaZflmD5AO/WnPqL1n9FRllLsST60An2mCXy2g=; b=jkaudYuxd2l139 kYv+3lys9oKHdfn1v/eCpAPnQAp8K/mp8BDbqnSgWGQdLl5nNbjaeTgNvYThT/jz/8YoDpG16m2OS n8A2m9d6QLOmIl3RExQT7l4gpFoQz4vO7uH2WMSSrSg+oNUDQyPS9pc5VvIv5eHcR+Sz7rTyRDttJ OJGAFUXKldONzujQPQXqFFt9OBE2myql6qxOrd8DmEkbyhWZMjeLsSu/SUOf5lXxZi6nKKQBeknXW PycgMXMZJ4RKEYihMwPiD34QE6iiwUUtxc+bEcRfBUU+qjePUK88G7j6UPYI3R2WqTnqhjJf4wTv1 LSQMHF5CulpkeUuOG+5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGheH-008P2V-Rh; Thu, 19 Aug 2021 12:59:57 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGheD-008P0b-0R; Thu, 19 Aug 2021 12:59:56 +0000 X-UUID: f2286f7e61be46bf98f9bff5df148226-20210819 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=65Qg+yTQ6Hh/FJ4xd+jM/c5MgTUeXVzdFkImksb4vw4=; b=ZwajC2bOjbf7HOhtX1gqqUw6uEhkQFmmCVPYylzJNSoHwTumGVFe+BZzzw4v4VIXD9PUbsAPgIblTwfGeNaZYHIClIR9PAKfin0cBJhv9B0dhxzbZ2SJmiRQ9fa9qV/SlWUC2fbr4/spDTrn3EDII/HLh/yYSdyxbZrBpVxd/Tw=; X-UUID: f2286f7e61be46bf98f9bff5df148226-20210819 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 674967990; Thu, 19 Aug 2021 05:59:48 -0700 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Aug 2021 05:59:46 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Aug 2021 20:59:45 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 Aug 2021 20:59:44 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , Rob Herring , Krzysztof Wilczyski , Bjorn Helgaas , Ryder Lee , Matthias Brugger CC: , , , , Jianjun Wang , , Subject: [PATCH] PCI: mediatek-gen3: Disable DVFSRC voltage request Date: Thu, 19 Aug 2021 20:59:39 +0800 Message-ID: <20210819125939.21253-1-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210819_055953_097322_0D5FA5F3 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org When the DVFSRC feature is not implemented, the MAC layer will assert a voltage request signal when exit from the L1ss state, but cannot receive the voltage ready signal, which will cause the link to fail to exit the L1ss state correctly. Disable DVFSRC voltage request by default, we need to find a common way to enable it in the future. Signed-off-by: Jianjun Wang Reviewed-by: Tzung-Bi Shih --- drivers/pci/controller/pcie-mediatek-gen3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index f3aeb8d4eaca..79fb12fca6a9 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -79,6 +79,9 @@ #define PCIE_ICMD_PM_REG 0x198 #define PCIE_TURN_OFF_LINK BIT(4) +#define PCIE_MISC_CTRL_REG 0x348 +#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) + #define PCIE_TRANS_TABLE_BASE_REG 0x800 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 @@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) val &= ~PCIE_INTX_ENABLE; writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); + /* Disable DVFSRC voltage request */ + val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG); + val |= PCIE_DISABLE_DVFSRC_VLT_REQ; + writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG); + /* Assert all reset signals */ val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;