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Fri, 20 Aug 2021 14:03:55 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 20 Aug 2021 14:03:55 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 20 Aug 2021 14:03:55 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 17KJ3lwX018479; Fri, 20 Aug 2021 14:03:52 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Chunfeng Yun , Kishon Vijay Abraham I , Peter Chen , , Subject: [PATCH v4 1/6] phy: cdns-dphy: Prepare for Rx support Date: Sat, 21 Aug 2021 00:33:41 +0530 Message-ID: <20210820190346.18550-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120400_979273_E78BC32A X-CRM114-Status: GOOD ( 22.20 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Rx programming sequence differs from the Tx programming sequence. Currently only Tx mode is supported. For example, the power on and off, validation, and configuration procedures are all different between Rx and Tx DPHYs. Currently they are only written from a Tx point of view and they won't work with an Rx DPHY. Move them to cdns_dphy_ops so they can be defined by the implementation, accommodating both Rx and Tx mode DPHYs. The clocks "psm" and "pll_ref" are not used by the Rx path so make them optional in the probe and then check if they exist in the Tx power_on() hook. Signed-off-by: Pratyush Yadav --- Changes in v4: - Instead of having both Rx and Tx modes in the same driver data, keep them separate since the op selection is based on compatible now. For that reason, the cdns_dphy_driver_data struct is no longer needed. - Rename ref_dphy_ops to tx_ref_dphy_ops to clarify their purpose. - Drop submode checks in validate() hook. drivers/phy/cadence/cdns-dphy.c | 123 ++++++++++++++++++++++---------- 1 file changed, 87 insertions(+), 36 deletions(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index ba042e39cfaf..0a169d649216 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -75,6 +75,11 @@ struct cdns_dphy; struct cdns_dphy_ops { int (*probe)(struct cdns_dphy *dphy); void (*remove)(struct cdns_dphy *dphy); + int (*power_on)(struct cdns_dphy *dphy); + int (*power_off)(struct cdns_dphy *dphy); + int (*validate)(struct cdns_dphy *dphy, enum phy_mode mode, int submode, + union phy_configure_opts *opts); + int (*configure)(struct cdns_dphy *dphy, union phy_configure_opts *opts); void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, enum cdns_dphy_clk_lane_cfg cfg); @@ -86,6 +91,7 @@ struct cdns_dphy_ops { struct cdns_dphy { struct cdns_dphy_cfg cfg; void __iomem *regs; + struct device *dev; struct clk *psm_clk; struct clk *pll_ref_clk; const struct cdns_dphy_ops *ops; @@ -199,20 +205,9 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) dphy->regs + DPHY_PSM_CFG); } -/* - * This is the reference implementation of DPHY hooks. Specific integration of - * this IP may have to re-implement some of them depending on how they decided - * to wire things in the SoC. - */ -static const struct cdns_dphy_ops ref_dphy_ops = { - .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, - .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, - .set_psm_div = cdns_dphy_ref_set_psm_div, -}; - -static int cdns_dphy_config_from_opts(struct phy *phy, - struct phy_configure_opts_mipi_dphy *opts, - struct cdns_dphy_cfg *cfg) +static int cdns_dphy_tx_config_from_opts(struct phy *phy, + struct phy_configure_opts_mipi_dphy *opts, + struct cdns_dphy_cfg *cfg) { struct cdns_dphy *dphy = phy_get_drvdata(phy); unsigned int dsi_hfp_ext = 0; @@ -232,24 +227,13 @@ static int cdns_dphy_config_from_opts(struct phy *phy, return 0; } -static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, - union phy_configure_opts *opts) +static int cdns_dphy_tx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) { struct cdns_dphy_cfg cfg = { 0 }; - - if (mode != PHY_MODE_MIPI_DPHY) - return -EINVAL; - - return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); -} - -static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - struct cdns_dphy *dphy = phy_get_drvdata(phy); - struct cdns_dphy_cfg cfg = { 0 }; int ret; - ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); + ret = cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); if (ret) return ret; @@ -279,9 +263,18 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } -static int cdns_dphy_power_on(struct phy *phy) +static int cdns_dphy_tx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); + struct cdns_dphy_cfg cfg = { 0 }; + + return cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); +} + +static int cdns_dphy_tx_power_on(struct cdns_dphy *dphy) +{ + if (!dphy->psm_clk || !dphy->pll_ref_clk) + return -EINVAL; clk_prepare_enable(dphy->psm_clk); clk_prepare_enable(dphy->pll_ref_clk); @@ -293,16 +286,73 @@ static int cdns_dphy_power_on(struct phy *phy) return 0; } -static int cdns_dphy_power_off(struct phy *phy) +static int cdns_dphy_tx_power_off(struct cdns_dphy *dphy) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); - clk_disable_unprepare(dphy->pll_ref_clk); clk_disable_unprepare(dphy->psm_clk); return 0; } +/* + * This is the reference implementation of DPHY hooks. Specific integration of + * this IP may have to re-implement some of them depending on how they decided + * to wire things in the SoC. + */ +static const struct cdns_dphy_ops tx_ref_dphy_ops = { + .power_on = cdns_dphy_tx_power_on, + .power_off = cdns_dphy_tx_power_off, + .validate = cdns_dphy_tx_validate, + .configure = cdns_dphy_tx_configure, + .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, + .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, + .set_psm_div = cdns_dphy_ref_set_psm_div, +}; + +static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, + union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (dphy->ops->validate) + return dphy->ops->validate(dphy, mode, submode, opts); + + return 0; +} + +static int cdns_dphy_power_on(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_on) + return dphy->ops->power_on(dphy); + + return 0; +} + +static int cdns_dphy_power_off(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_off) + return dphy->ops->power_off(dphy); + + return 0; +} + +static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->configure) + return dphy->ops->configure(dphy, opts); + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, @@ -320,6 +370,7 @@ static int cdns_dphy_probe(struct platform_device *pdev) if (!dphy) return -ENOMEM; dev_set_drvdata(&pdev->dev, dphy); + dphy->dev = &pdev->dev; dphy->ops = of_device_get_match_data(&pdev->dev); if (!dphy->ops) @@ -329,11 +380,11 @@ static int cdns_dphy_probe(struct platform_device *pdev) if (IS_ERR(dphy->regs)) return PTR_ERR(dphy->regs); - dphy->psm_clk = devm_clk_get(&pdev->dev, "psm"); + dphy->psm_clk = devm_clk_get_optional(dphy->dev, "psm"); if (IS_ERR(dphy->psm_clk)) return PTR_ERR(dphy->psm_clk); - dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); + dphy->pll_ref_clk = devm_clk_get_optional(dphy->dev, "pll_ref"); if (IS_ERR(dphy->pll_ref_clk)) return PTR_ERR(dphy->pll_ref_clk); @@ -369,7 +420,7 @@ static int cdns_dphy_remove(struct platform_device *pdev) } static const struct of_device_id cdns_dphy_of_match[] = { - { .compatible = "cdns,dphy", .data = &ref_dphy_ops }, + { .compatible = "cdns,dphy", .data = &tx_ref_dphy_ops }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, cdns_dphy_of_match); From patchwork Fri Aug 20 19:03:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12450275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFE7BC4320E for ; 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Fri, 20 Aug 2021 14:03:55 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Chunfeng Yun , Kishon Vijay Abraham I , Peter Chen , , Subject: [PATCH v4 2/6] phy: cdns-dphy: Add Rx support Date: Sat, 21 Aug 2021 00:33:42 +0530 Message-ID: <20210820190346.18550-3-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120404_800082_1DF17995 X-CRM114-Status: GOOD ( 25.87 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Cadence DPHY can be used to receive image data over the CSI-2 protocol. Add support for Rx mode. The programming sequence differs from the Tx mode so it is added as a separate set of hooks to isolate the two paths. The mode in which the DPHY has to be used is selected based on the compatible. Signed-off-by: Pratyush Yadav --- Changes in v4: - Drop the submode parts. Use a different compatible for the Rx ops. - Make bands and num_bands static. Changes in v3: - Use a table to select the band. - Use a table to poll the data lane ready bits. - Multiply the DPHY HS clock rate by 2 to get the bit rate since the clock is DDR. drivers/phy/cadence/cdns-dphy.c | 171 ++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 0a169d649216..149fccdfad38 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright: 2017-2018 Cadence Design Systems, Inc. + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include +#include #include #include #include @@ -25,10 +28,14 @@ #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) #define DPHY_PCS(reg) (0xb00 + (reg)) +#define DPHY_ISO(reg) (0xc00 + (reg)) #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) +#define DPHY_CMN_RX_MODE_EN BIT(10) +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) #define DPHY_CMN_PWM_DIV(x) ((x) << 20) @@ -45,10 +52,27 @@ #define DPHY_CMN_OPDIV_FROM_REG BIT(6) #define DPHY_CMN_OPDIV(x) ((x) << 7) +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) + #define DPHY_PSM_CFG DPHY_PCS(0x4) #define DPHY_PSM_CFG_FROM_REG BIT(0) #define DPHY_PSM_CLK_DIV(x) ((x) << 1) +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa + +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) +#define DPHY_ISO_LANE_READY_BIT 0 +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL + #define DSI_HBP_FRAME_OVERHEAD 12 #define DSI_HSA_FRAME_OVERHEAD 14 #define DSI_HFP_FRAME_OVERHEAD 6 @@ -57,6 +81,9 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 +#define DPHY_LANES_MIN 1 +#define DPHY_LANES_MAX 4 + struct cdns_dphy_cfg { u8 pll_ipdiv; u8 pll_opdiv; @@ -98,6 +125,22 @@ struct cdns_dphy { struct phy *phy; }; +struct cdns_dphy_rx_band { + unsigned int min_rate; + unsigned int max_rate; +}; + +/* Order of bands is important since the index is the band number. */ +static struct cdns_dphy_rx_band bands[] = { + {80, 100}, {100, 120}, {120, 160}, {160, 200}, {200, 240}, + {240, 280}, {280, 320}, {320, 360}, {360, 400}, {400, 480}, + {480, 560}, {560, 640}, {640, 720}, {720, 800}, {800, 880}, + {880, 1040}, {1040, 1200}, {1200, 1350}, {1350, 1500}, {1500, 1750}, + {1750, 2000}, {2000, 2250}, {2250, 2500} +}; + +static int num_bands = ARRAY_SIZE(bands); + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -309,6 +352,132 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { .set_psm_div = cdns_dphy_ref_set_psm_div, }; +static int cdns_dphy_rx_power_on(struct cdns_dphy *dphy) +{ + /* Start RX state machine. */ + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, + DPHY_CMN_RX_BANDGAP_TIMER), + dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_power_off(struct cdns_dphy *dphy) +{ + writel(0, dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate; + int i; + + rate = hs_clk_rate / 1000000UL; + /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ + rate *= 2; + + if (rate < bands[0].min_rate || rate >= bands[num_bands - 1].max_rate) + return -EOPNOTSUPP; + + for (i = 0; i < num_bands; i++) { + if (rate >= bands[i].min_rate && rate < bands[i].max_rate) + return i; + } + + /* Unreachable. */ + WARN(1, "Reached unreachable code."); + return -EINVAL; +} + +static int cdns_dphy_rx_wait_for_bit(void __iomem *addr, unsigned int bit) +{ + u32 val; + + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); +} + +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy *dphy, int lanes) +{ + void __iomem *reg = dphy->regs; + u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, DPHY_ISO_DL_CTRL_L1, + DPHY_ISO_DL_CTRL_L2, DPHY_ISO_DL_CTRL_L3}; + int ret, i; + + /* Data lanes. Minimum one lane is mandatory. */ + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) + return -EINVAL; + + /* Clock lane */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + for (i = 0; i < lanes; i++) { + ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) +{ + unsigned int reg; + int band_ctrl, ret; + + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + + /* + * Set the required power island phase 2 time. This is mandated by DPHY + * specs. + */ + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); + + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); + if (ret) { + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + int ret; + + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (ret < 0) + return ret; + + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); +} + +static const struct cdns_dphy_ops rx_ref_dphy_ops = { + .power_on = cdns_dphy_rx_power_on, + .power_off = cdns_dphy_rx_power_off, + .configure = cdns_dphy_rx_configure, + .validate = cdns_dphy_rx_validate, +}; + static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, union phy_configure_opts *opts) { @@ -421,6 +590,7 @@ static int cdns_dphy_remove(struct platform_device *pdev) static const struct of_device_id cdns_dphy_of_match[] = { { .compatible = "cdns,dphy", .data = &tx_ref_dphy_ops }, + { .compatible = "cdns,dphy-rx", .data = &rx_ref_dphy_ops }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, cdns_dphy_of_match); @@ -436,5 +606,6 @@ static struct platform_driver cdns_dphy_platform_driver = { module_platform_driver(cdns_dphy_platform_driver); MODULE_AUTHOR("Maxime Ripard "); +MODULE_AUTHOR("Pratyush Yadav "); MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver"); MODULE_LICENSE("GPL"); From patchwork Fri Aug 20 19:03:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12450277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BB8FC4338F for ; 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Fri, 20 Aug 2021 14:03:59 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v4 3/6] phy: dt-bindings: Convert Cadence DPHY binding to YAML Date: Sat, 21 Aug 2021 00:33:43 +0530 Message-ID: <20210820190346.18550-4-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120407_486505_5033DEE3 X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Convert Cadence DPHY binding to YAML. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring --- (no changes since v3) Changes in v3: - Add Rob's R-by. Changes in v2: - Drop reg description. - Add a description for each DPHY clock. - Rename dphy@... to phy@... in example. - Add Laurent's R-by. - Re-order subject prefixes. .../devicetree/bindings/phy/cdns,dphy.txt | 20 -------- .../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted file mode 100644 index 1095bc4e72d9..000000000000 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt +++ /dev/null @@ -1,20 +0,0 @@ -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml new file mode 100644 index 000000000000..b90a58773bf2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Device Tree Bindings + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,dphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PMA state machine clock + - description: PLL reference clock + + clock-names: + items: + - const: psm + - const: pll_ref + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + dphy0: phy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0xfd0e0000 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; From patchwork Fri Aug 20 19:03:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12450279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24D35C4338F for ; Fri, 20 Aug 2021 19:04:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2F1161102 for ; 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Fri, 20 Aug 2021 14:04:06 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 20 Aug 2021 14:04:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 20 Aug 2021 14:04:06 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 17KJ3lwa018479; Fri, 20 Aug 2021 14:04:03 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v4 4/6] phy: dt-bindings: cdns,dphy: make clocks optional Date: Sat, 21 Aug 2021 00:33:44 +0530 Message-ID: <20210820190346.18550-5-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120411_641370_C9502A47 X-CRM114-Status: UNSURE ( 8.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The clocks are not used by the DPHY when used in Rx mode so make them optional. Signed-off-by: Pratyush Yadav Acked-by: Rob Herring --- (no changes since v3) Changes in v3: - Add Rob's Ack. Changes in v2: - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index b90a58773bf2..3bb5be05e825 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -33,8 +33,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - "#phy-cells" additionalProperties: false From patchwork Fri Aug 20 19:03:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12450281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41B2BC4338F for ; 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Fri, 20 Aug 2021 14:04:06 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v4 5/6] phy: dt-bindings: cdns, dphy: add power-domains property Date: Sat, 21 Aug 2021 00:33:45 +0530 Message-ID: <20210820190346.18550-6-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120416_000657_D3F11424 X-CRM114-Status: UNSURE ( 9.11 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Acked-by: Rob Herring --- (no changes since v3) Changes in v3: - Add Rob's Ack. Changes in v2: - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index 3bb5be05e825..d5a5e1f0b671 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -39,11 +42,13 @@ additionalProperties: false examples: - | + #include dphy0: phy@fd0e0000{ compatible = "cdns,dphy"; reg = <0xfd0e0000 0x1000>; clocks = <&psm_clk>, <&pll_ref_clk>; clock-names = "psm", "pll_ref"; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; #phy-cells = <0>; }; From patchwork Fri Aug 20 19:03:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12450283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED15C4338F for ; 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Fri, 20 Aug 2021 14:04:10 -0500 From: Pratyush Yadav To: Vinod Koul CC: Paul Kocialkowski , Tomi Valkeinen , Vignesh Raghavendra , Nikhil Devshatwar , Laurent Pinchart , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v4 6/6] phy: dt-bindings: cdns,dphy: add Rx DPHY compatible Date: Sat, 21 Aug 2021 00:33:46 +0530 Message-ID: <20210820190346.18550-7-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210820190346.18550-1-p.yadav@ti.com> References: <20210820190346.18550-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_120418_526073_B26CDB38 X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The DPHY is treated to be in Tx mode by default. Add a new compatible for Rx mode DPHYs. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- Changes in v4: - New in v4. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index d5a5e1f0b671..48b6a841152e 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -11,8 +11,9 @@ maintainers: properties: compatible: - items: + oneOf: - const: cdns,dphy + - const: cdns,dphy-rx reg: maxItems: 1