From patchwork Thu Aug 26 05:48:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 12459131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C22DC432BE for ; Thu, 26 Aug 2021 05:48:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 026BF61037 for ; Thu, 26 Aug 2021 05:48:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 026BF61037 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B18C6E506; Thu, 26 Aug 2021 05:48:04 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 831846E4F1 for ; Thu, 26 Aug 2021 05:47:58 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10087"; a="281387664" X-IronPort-AV: E=Sophos;i="5.84,352,1620716400"; d="scan'208";a="281387664" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2021 22:47:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,352,1620716400"; d="scan'208";a="474088766" Received: from unknown (HELO vandita-Z390-AORUS-ULTRA.iind.intel.com) ([10.190.238.8]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2021 22:47:56 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Vandita Kulkarni Date: Thu, 26 Aug 2021 11:18:10 +0530 Message-Id: <20210826054811.10572-2-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210826054811.10572-1-vandita.kulkarni@intel.com> References: <20210826054811.10572-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v2 1/2] drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband" field to account for the repeaters on the HS Request/Ready PPI signaling between the Display engine and the DPHY. v2: Fix build issue. v3: Align to new naming (Jani) Signed-off-by: Vandita Kulkarni Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 43ec7fcd3f5d..55645c456d9e 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1270,6 +1270,26 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, IGNORE_KVMR_PIPE_A, enable ? IGNORE_KVMR_PIPE_A : 0); } + +/* + * Wa_16012360555:adl-p + * SW will have to program the "LP to HS Wakeup Guardband" + * to account for the repeaters on the HS Request/Ready + * PPI signaling between the Display engine and the DPHY. + */ +static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + enum port port; + + if (DISPLAY_VER(i915) == 13) { + for_each_dsi_port(port, intel_dsi->ports) + intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), + TGL_DSI_CHKN_LSHS_GB, 0x4); + } +} + static void gen11_dsi_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1283,6 +1303,9 @@ static void gen11_dsi_enable(struct intel_atomic_state *state, /* Wa_1409054076:icl,jsl,ehl */ icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); + /* Wa_16012360555:adl-p */ + adlp_set_lp_hs_wakeup_gb(encoder); + /* step6d: enable dsi transcoder */ gen11_dsi_enable_transcoder(encoder); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d4cf1e203ab..815fc73bd2f7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11639,6 +11639,14 @@ enum skl_power_gate { _ICL_DSI_IO_MODECTL_1) #define COMBO_PHY_MODE_DSI (1 << 0) +/* TGL DSI Chicken register */ +#define _TGL_DSI_CHKN_REG_0 0x6B0C0 +#define _TGL_DSI_CHKN_REG_1 0x6B8C0 +#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \ + _TGL_DSI_CHKN_REG_0, \ + _TGL_DSI_CHKN_REG_1) +#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12) + /* Display Stream Splitter Control */ #define DSS_CTL1 _MMIO(0x67400) #define SPLITTER_ENABLE (1 << 31) From patchwork Thu Aug 26 05:48:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 12459129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA3AC4320A for ; Thu, 26 Aug 2021 05:48:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C505260F39 for ; Thu, 26 Aug 2021 05:48:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C505260F39 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F9B86E505; Thu, 26 Aug 2021 05:48:01 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08E436E505 for ; Thu, 26 Aug 2021 05:47:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10087"; a="281387666" X-IronPort-AV: E=Sophos;i="5.84,352,1620716400"; d="scan'208";a="281387666" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2021 22:47:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,352,1620716400"; d="scan'208";a="474088771" Received: from unknown (HELO vandita-Z390-AORUS-ULTRA.iind.intel.com) ([10.190.238.8]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2021 22:47:58 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Vandita Kulkarni Date: Thu, 26 Aug 2021 11:18:11 +0530 Message-Id: <20210826054811.10572-3-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210826054811.10572-1-vandita.kulkarni@intel.com> References: <20210826054811.10572-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v2 2/2] drm/i915/dsi/xelpd: Enable mipi dsi support. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable MIPI DSI support on ADL-P platform. The esc clock changes, WA changes are taken care in the previous patches. As per the Bspec the seq remains to be same as TGL. Signed-off-by: Vandita Kulkarni Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index fe5ad599c218..a7d002321bdc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11009,6 +11009,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_TC2); intel_ddi_init(dev_priv, PORT_TC3); intel_ddi_init(dev_priv, PORT_TC4); + icl_dsi_init(dev_priv); } else if (IS_ALDERLAKE_S(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_TC1);