From patchwork Thu Aug 26 12:38:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifeng Zhao X-Patchwork-Id: 12459693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5BADC432BE for ; Thu, 26 Aug 2021 12:43:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79506610A1 for ; Thu, 26 Aug 2021 12:43:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 79506610A1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y2ggLGByEUJTIvnyiM6REUwJEuXTbI0KKYIG8qEJ6e8=; b=vZRouXJGZtDDmF lh8tIIjBcSmi6TrX8NtB6LZARojLyrNia12ZirEVeVKJpAA4evwJmSLb9NwNEI199Aj8YPldZjbVA ugTMUfOHGEJaTuTdAW2PY/c0b9ri+jev6o9SyBUgJwx2FtER+QJjpWfZv/kng/gNEYXCQli6Gti3C +cBmIQdNd7dOL0CkeQoerb6vC66GakZiLa7UBrGj4lX1Z1RZWdDDtZDhtC4r+IPaFPzQSIlMtZtXA ZKizVGm5ssSJskXAYtxsQVML7hfdyQCOJq5kCWCLryde8l4LACfYauXQsdh9igBcqU8Cpod8ORiea DezMgtVctxXaNEIGgncQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mJEgQ-00A7Xj-8e; Thu, 26 Aug 2021 12:40:39 +0000 Received: from lucky1.263xmail.com ([211.157.147.135]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mJEeq-00A6zy-Nf; Thu, 26 Aug 2021 12:39:06 +0000 Received: from localhost (unknown [192.168.167.235]) by lucky1.263xmail.com (Postfix) with ESMTP id 06472B2CBA; Thu, 26 Aug 2021 20:38:51 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P32763T139761010153216S1629981525980003_; Thu, 26 Aug 2021 20:38:51 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <873f58238d50a8cc07e4d0550ef12971> X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 12 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, Yifeng Zhao Subject: [PATCH v1 1/3] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings Date: Thu, 26 Aug 2021 20:38:42 +0800 Message-Id: <20210826123844.8464-2-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> References: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210826_053901_320595_0B3615D0 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Signed-off-by: Yifeng Zhao --- .../phy/phy-rockchip-naneng-combphy.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml new file mode 100644 index 000000000000..69908614609c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC Naneng Combo Phy Device Tree Bindings + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3568-naneng-combphy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: reference clock + - description: apb clock + - description: pipe clock + + clock-names: + minItems: 1 + items: + - const: ref + - const: apb + - const: pipe + + '#phy-cells': + const: 1 + + resets: + minItems: 1 + items: + - description: exclusive apb reset line + - description: exclusive PHY reset line + + reset-names: + minItems: 1 + items: + - const: combphy-apb + - const: combphy + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional phy settings are access through GRF regs. + + rockchip,pipe-phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some additional pipe settings are access through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#phy-cells' + - resets + - reset-names + - rockchip,pipe-grf + - rockchip,pipe-phy-grf + +additionalProperties: false + +examples: + - | + + #include + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipegrf", "syscon"; + reg = <0xfdc50000 0x1000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0xfdc70000 0x1000>; + }; + + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0xfe820000 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + }; From patchwork Thu Aug 26 12:38:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifeng Zhao X-Patchwork-Id: 12459691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF91AC432BE for ; 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Thu, 26 Aug 2021 20:38:53 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <5edbae06160058b9826b59ee43e0d716> X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 12 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, Yifeng Zhao Subject: [PATCH v1 3/3] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Date: Thu, 26 Aug 2021 20:38:44 +0800 Message-Id: <20210826123844.8464-4-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> References: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210826_053901_087092_5B212A7D X-CRM114-Status: UNSURE ( 9.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index d89831bee1eb..b421e3d52412 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -214,11 +214,31 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipegrf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -862,6 +882,54 @@ status = "disabled"; }; + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + status = "disabled"; + }; + + combphy1_usq: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + status = "disabled"; + }; + + combphy2_psq: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>;