From patchwork Sun Aug 29 20:48:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12464339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 044BFC43214 for ; Sun, 29 Aug 2021 20:48:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA08860F51 for ; Sun, 29 Aug 2021 20:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233919AbhH2UtZ (ORCPT ); Sun, 29 Aug 2021 16:49:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235265AbhH2UtW (ORCPT ); Sun, 29 Aug 2021 16:49:22 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [IPv6:2001:4b7a:2000:18::162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CC8DC061760; Sun, 29 Aug 2021 13:48:27 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 2FBE11FAEC; Sun, 29 Aug 2021 22:48:25 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parents Date: Sun, 29 Aug 2021 22:48:19 +0200 Message-Id: <20210829204822.289829-2-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829204822.289829-1-marijn.suijten@somainline.org> References: <20210829204822.289829-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data instead of hardcoding a number that relies on an array defined hundreds of lines above. Signed-off-by: Marijn Suijten --- drivers/clk/qcom/gcc-sdm660.c | 80 +++++++++++++++++------------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 4d36f96e9ae2..9b97425008ce 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -309,7 +309,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -323,7 +323,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -337,7 +337,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -379,7 +379,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -393,7 +393,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -454,7 +454,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -482,7 +482,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -496,7 +496,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -510,7 +510,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -524,7 +524,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -538,7 +538,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -552,7 +552,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -566,7 +566,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -580,7 +580,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -601,7 +601,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -615,7 +615,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -629,7 +629,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -649,7 +649,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -670,7 +670,7 @@ static struct clk_rcg2 hmss_gpll4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll4_clk_src", .parent_data = gcc_parent_data_xo_gpll4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4), .ops = &clk_rcg2_ops, }, }; @@ -689,7 +689,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", .parent_data = gcc_parent_data_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -708,7 +708,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div), .ops = &clk_rcg2_ops, }, }; @@ -756,7 +756,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -778,7 +778,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -804,7 +804,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -827,7 +827,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -848,7 +848,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -862,7 +862,7 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_phy_aux_clk_src", .parent_data = gcc_parent_data_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -883,7 +883,7 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_unipro_core_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -904,7 +904,7 @@ static struct clk_rcg2 usb20_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -924,7 +924,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -949,7 +949,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -970,7 +970,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_data = gcc_parent_data_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; From patchwork Sun Aug 29 20:48:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12464337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB652C00143 for ; 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Sun, 29 Aug 2021 22:48:25 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] clk: qcom: gpucc-sdm660: Use ARRAY_SIZE for num_parents Date: Sun, 29 Aug 2021 22:48:20 +0200 Message-Id: <20210829204822.289829-3-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829204822.289829-1-marijn.suijten@somainline.org> References: <20210829204822.289829-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Signed-off-by: Marijn Suijten --- drivers/clk/qcom/gpucc-sdm660.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 1ebcceb3a50d..bea73ae28b36 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -114,7 +114,7 @@ static struct clk_rcg2_gfx3d gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_data = gpucc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gpucc_parent_data_1), .ops = &clk_gfx3d_ops, .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, @@ -172,7 +172,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbbmtimer_clk_src", .parent_data = gpucc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gpucc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -192,7 +192,7 @@ static struct clk_rcg2 rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbcpr_clk_src", .parent_data = gpucc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gpucc_parent_data_0), .ops = &clk_rcg2_ops, }, }; From patchwork Sun Aug 29 20:48:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12464341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2420DC3F6A3 for ; Sun, 29 Aug 2021 20:48:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 042EE60F58 for ; Sun, 29 Aug 2021 20:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236029AbhH2Ut0 (ORCPT ); Sun, 29 Aug 2021 16:49:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234668AbhH2UtW (ORCPT ); Sun, 29 Aug 2021 16:49:22 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [IPv6:2001:4b7a:2000:18::162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 745AAC0617AE; Sun, 29 Aug 2021 13:48:28 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id AD72F1FA03; Sun, 29 Aug 2021 22:48:26 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: qcom: mmcc-sdm660: Use ARRAY_SIZE for num_parents Date: Sun, 29 Aug 2021 22:48:21 +0200 Message-Id: <20210829204822.289829-4-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829204822.289829-1-marijn.suijten@somainline.org> References: <20210829204822.289829-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Signed-off-by: Marijn Suijten --- drivers/clk/qcom/mmcc-sdm660.c | 72 +++++++++++++++++----------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 941993bc610d..9bfce9c31ca7 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -483,7 +483,7 @@ static struct clk_rcg2 ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ahb_clk_src", .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -496,7 +496,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_data = mmcc_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -510,7 +510,7 @@ static struct clk_rcg2 byte1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_data = mmcc_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -538,7 +538,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -552,7 +552,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -573,7 +573,7 @@ static struct clk_rcg2 cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -597,7 +597,7 @@ static struct clk_rcg2 cpp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6), .ops = &clk_rcg2_ops, }, }; @@ -620,7 +620,7 @@ static struct clk_rcg2 csi0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -641,7 +641,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 csi1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -669,7 +669,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -683,7 +683,7 @@ static struct clk_rcg2 csi2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -697,7 +697,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 csi3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -733,7 +733,7 @@ static struct clk_rcg2 csiphy_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -752,7 +752,7 @@ static struct clk_rcg2 dp_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "dp_aux_clk_src", .parent_data = mmcc_xo_gpll0_gpll0_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -773,7 +773,7 @@ static struct clk_rcg2 dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "dp_crypto_clk_src", .parent_data = mmcc_xo_dplink_dpvco, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), .ops = &clk_rcg2_ops, }, }; @@ -793,7 +793,7 @@ static struct clk_rcg2 dp_gtc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "dp_gtc_clk_src", .parent_data = mmcc_xo_gpll0_gpll0_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -814,7 +814,7 @@ static struct clk_rcg2 dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "dp_link_clk_src", .parent_data = mmcc_xo_dplink_dpvco, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), .ops = &clk_rcg2_ops, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, @@ -828,7 +828,7 @@ static struct clk_rcg2 dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "dp_pixel_clk_src", .parent_data = mmcc_xo_dplink_dpvco, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), .ops = &clk_dp_ops, .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, }, @@ -842,7 +842,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_data = mmcc_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), .ops = &clk_rcg2_ops, }, }; @@ -855,7 +855,7 @@ static struct clk_rcg2 esc1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", .parent_data = mmcc_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), .ops = &clk_rcg2_ops, }, }; @@ -878,7 +878,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -906,7 +906,7 @@ static struct clk_rcg2 mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -920,7 +920,7 @@ static struct clk_rcg2 mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -934,7 +934,7 @@ static struct clk_rcg2 mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -948,7 +948,7 @@ static struct clk_rcg2 mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -974,7 +974,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -987,7 +987,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_data = mmcc_xo_dsi0pll_dsi1pll, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -1001,7 +1001,7 @@ static struct clk_rcg2 pclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_data = mmcc_xo_dsi0pll_dsi1pll, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -1025,7 +1025,7 @@ static struct clk_rcg2 rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rot_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1051,7 +1051,7 @@ static struct clk_rcg2 vfe0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1065,7 +1065,7 @@ static struct clk_rcg2 vfe1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1089,7 +1089,7 @@ static struct clk_rcg2 video_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_core_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7), .ops = &clk_rcg2_ops, .flags = CLK_IS_CRITICAL, }, @@ -1104,7 +1104,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_data = mmcc_xo_gpll0_gpll0_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -2055,7 +2055,7 @@ static struct clk_rcg2 axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "axi_clk_src", .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; From patchwork Sun Aug 29 20:48:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12464343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B66D6C4320A for ; Sun, 29 Aug 2021 20:48:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9ACDE60041 for ; Sun, 29 Aug 2021 20:48:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235316AbhH2Ut2 (ORCPT ); Sun, 29 Aug 2021 16:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235475AbhH2UtW (ORCPT ); Sun, 29 Aug 2021 16:49:22 -0400 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [IPv6:2001:4b7a:2000:18::165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A85EC0617AF; Sun, 29 Aug 2021 13:48:29 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 698101FBA5; Sun, 29 Aug 2021 22:48:27 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clk: qcom: gpucc-sdm660: Remove fallback to global clock names Date: Sun, 29 Aug 2021 22:48:22 +0200 Message-Id: <20210829204822.289829-5-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829204822.289829-1-marijn.suijten@somainline.org> References: <20210829204822.289829-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The necessary clocks for this driver are already fully specified in sdm630 DT under the .fw_name, and do not need an implicit fallback to their global name. Signed-off-by: Marijn Suijten --- drivers/clk/qcom/gpucc-sdm660.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index bea73ae28b36..41bba96a08b3 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -44,8 +44,7 @@ static struct clk_branch gpucc_cxo_clk = { .hw.init = &(struct clk_init_data){ .name = "gpucc_cxo_clk", .parent_data = &(const struct clk_parent_data){ - .fw_name = "xo", - .name = "xo" + .fw_name = "xo" }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -101,7 +100,7 @@ static const struct clk_parent_data gpucc_parent_data_1[] = { { .hw = &gpucc_cxo_clk.clkr.hw }, { .hw = &gpu_pll0_pll_out_main.clkr.hw }, { .hw = &gpu_pll1_pll_out_main.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" }, + { .fw_name = "gcc_gpu_gpll0_clk" }, }; static struct clk_rcg2_gfx3d gfx3d_clk_src = { @@ -154,8 +153,8 @@ static const struct parent_map gpucc_parent_map_0[] = { static const struct clk_parent_data gpucc_parent_data_0[] = { { .hw = &gpucc_cxo_clk.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" }, - { .fw_name = "gcc_gpu_gpll0_div_clk", .name = "gcc_gpu_gpll0_div_clk" }, + { .fw_name = "gcc_gpu_gpll0_clk" }, + { .fw_name = "gcc_gpu_gpll0_div_clk" }, }; static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {