From patchwork Mon Aug 30 00:36:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 12464391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23A7AC432BE for ; Mon, 30 Aug 2021 00:38:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC92060F38 for ; Mon, 30 Aug 2021 00:38:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DC92060F38 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hTFy/5FPhfAOHJFYAGs9YD7hbjZ9u86G08F3ZKx1cmY=; b=RdShltb9mhAvNS YXlfLI4Z/Re+mgDGndGUjEsFs3lF/0VNa0aWrf3uikulqK6N/hK7KUhKAQMnMhOKKzPDhS8ZGD047 6qOC37IH6x7CzWJ9vX06f+paQcEKRefcBaTQVEwbmdJ18BNxu8ujon0/3tz1LE6a6rGNmf7XnYi6J YYBJb7wwQ3oqtT8mFT/05AgwnyOoNFBtQke4K/EEsT2pk2tyqJVIKKibkBjmZwwxgJzNAQIsIrHk8 KbSv9paYsgpgGANzbGBFVODspwG1CVYmK3TR6VqvHyNTGPTT3iKBF2Htaek+HACu4hfDuERzKC70D jq8iWXoP2hMj90X/nXYA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKVHx-00GBCW-CY; Mon, 30 Aug 2021 00:36:37 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKVHf-00GB7b-9P; Mon, 30 Aug 2021 00:36:23 +0000 X-UUID: 43bb3f8565204dcda1831fdf33d6d16d-20210829 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sEXOn0hSOqKjEvcuAaL3NiZpk3UqBSxj+/qUK97psJc=; b=q5snEYMA237dDQHKZ+KsxzGHdXq9B5PNiHP4a8Ng14H/21wl3QH9JFmg/rfClu0/tGhCudoqm28bl88AIZsKUBQfHxmNvRgZpjzJ+WS3mvsEhFkYsDY1pGbYN8ddjvg2A16Cei1khUsCCG/PQURQjAqsORfLF20CCA0S7WlU+Gc=; X-UUID: 43bb3f8565204dcda1831fdf33d6d16d-20210829 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1809736754; Sun, 29 Aug 2021 17:36:16 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 29 Aug 2021 17:36:15 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 Aug 2021 08:36:13 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 Aug 2021 08:36:06 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v11 1/4] dt-bindings: pinctrl: mt8195: add rsel define Date: Mon, 30 Aug 2021 08:36:00 +0800 Message-ID: <20210830003603.31864-2-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210830003603.31864-1-zhiyong.tao@mediatek.com> References: <20210830003603.31864-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_173619_372726_6C94A428 X-CRM114-Status: UNSURE ( 9.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds rsel define for mt8195. Signed-off-by: Zhiyong Tao Acked-by: Rob Herring --- include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h index 7e16e58fe1f7..f5934abcd1bd 100644 --- a/include/dt-bindings/pinctrl/mt65xx.h +++ b/include/dt-bindings/pinctrl/mt65xx.h @@ -16,6 +16,15 @@ #define MTK_PUPD_SET_R1R0_10 102 #define MTK_PUPD_SET_R1R0_11 103 +#define MTK_PULL_SET_RSEL_000 200 +#define MTK_PULL_SET_RSEL_001 201 +#define MTK_PULL_SET_RSEL_010 202 +#define MTK_PULL_SET_RSEL_011 203 +#define MTK_PULL_SET_RSEL_100 204 +#define MTK_PULL_SET_RSEL_101 205 +#define MTK_PULL_SET_RSEL_110 206 +#define MTK_PULL_SET_RSEL_111 207 + #define MTK_DRIVE_2mA 2 #define MTK_DRIVE_4mA 4 #define MTK_DRIVE_6mA 6 From patchwork Mon Aug 30 00:36:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 12464393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA546C4320A for ; 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Mon, 30 Aug 2021 08:36:14 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v11 2/4] dt-bindings: pinctrl: mt8195: change pull up/down description Date: Mon, 30 Aug 2021 08:36:01 +0800 Message-ID: <20210830003603.31864-3-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210830003603.31864-1-zhiyong.tao@mediatek.com> References: <20210830003603.31864-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_173619_735656_57047F81 X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Change pull up/down description Signed-off-by: Zhiyong Tao --- .../bindings/pinctrl/pinctrl-mt8195.yaml | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 2f12ec59eee5..a341ed9f0095 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -85,9 +85,35 @@ patternProperties: 2/4/6/8/10/12/14/16mA in mt8195. enum: [0, 1, 2, 3, 4, 5, 6, 7] - bias-pull-down: true - - bias-pull-up: true + bias-pull-down: + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8195. + For pull down type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance. It can support "MTK_PULL_SET_RSEL_000" & + "MTK_PULL_SET_RSEL_001" & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & + "MTK_PULL_SET_RSEL_111" define in mt8195. It can also support resistance value(ohm) + "75000" & "5000" in mt8195. + + bias-pull-up: + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8195. + For pull up type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance. It can support "MTK_PULL_SET_RSEL_000" & + "MTK_PULL_SET_RSEL_001" & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & + "MTK_PULL_SET_RSEL_111" define in mt8195. It can also support resistance value(ohm) + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. bias-disable: true From patchwork Mon Aug 30 00:36:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 12464395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C15CDC432BE for ; Mon, 30 Aug 2021 00:39:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90E3060ED8 for ; Mon, 30 Aug 2021 00:39:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 90E3060ED8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kFgogQTMWKMqOpnzMkyBMzUEKuj6B98qEjhRjh8G2mA=; b=By62yxi9KXyJOz 0P2BYeLh7mrhuOWETa1sneOOv0MNNVVISC+3Zhj/JKll2A1+uBnIp30EO3YjoXbXNEk9ExZfg9nGX E0h7TtlwUi9ZFRDU8xSNUK1rQS24bNhdOKffWjpcl0yU1xiuJvyoPYUVGdg6BRBxaqdh3awbANWjt Mq4srr2AZxnsAnbE5YGgcu74eKqu3Ad60GwOQE5T4IkRIhkSe/DWDug0MGBE/aDldrq4gXRGfwsku l0sCbxLH26+fTv08dmWnkqpLzYE5OeoWP8ylyhcNUBSrzmkGktKFY1U95sTbFcxhvpH9ecWnrq02g 4hDKms9LmtayuC+nDaMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKVIP-00GBN2-S8; Mon, 30 Aug 2021 00:37:06 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKVHk-00GB8H-CL; Mon, 30 Aug 2021 00:36:25 +0000 X-UUID: 648da0a74f0f4050ae8b5fbe89eb0f7d-20210829 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nHpUSdm18wQ0pNnXPq7IbT/TzUD/y67ldGaHbTX22/o=; b=rLKK9joILNZShXx+Roh5ANGI8fFee0j8Illpr4TD8Y8TxgHWlxH1IF6Wh0jxa64h6cRFTyHlTMG8YSYuuMSN5qQC396RHrTJ5BceDdhgMeQm4ojlkxy9eP+eEAt1B9Clf+ZLzuZG0A8u/7irO6lVZvQ9tM2JnrhrSaVa172noE0=; X-UUID: 648da0a74f0f4050ae8b5fbe89eb0f7d-20210829 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1783270233; Sun, 29 Aug 2021 17:36:19 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 29 Aug 2021 17:36:17 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 Aug 2021 08:36:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 Aug 2021 08:36:15 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v11 3/4] pinctrl: mediatek: mt8195: Add pm_ops Date: Mon, 30 Aug 2021 08:36:02 +0800 Message-ID: <20210830003603.31864-4-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210830003603.31864-1-zhiyong.tao@mediatek.com> References: <20210830003603.31864-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_173624_478428_998873ED X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Setting this up will configure wake from suspend properly, and wake only for the interrupts that are setup in wake_mask, not all interrupts. Signed-off-by: Zhiyong Tao Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index a7500e18bb1d..892e79703f98 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -839,6 +839,7 @@ static struct platform_driver mt8195_pinctrl_driver = { .driver = { .name = "mt8195-pinctrl", .of_match_table = mt8195_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, }, .probe = mt8195_pinctrl_probe, }; From patchwork Mon Aug 30 00:36:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 12464397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9C40C432BE for ; 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Mon, 30 Aug 2021 08:36:16 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v11 4/4] pinctrl: mediatek: add rsel setting on MT8195 Date: Mon, 30 Aug 2021 08:36:03 +0800 Message-ID: <20210830003603.31864-5-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210830003603.31864-1-zhiyong.tao@mediatek.com> References: <20210830003603.31864-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_173624_674179_463BA9BA X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch provides rsel setting on MT8195 Signed-off-by: Zhiyong Tao --- drivers/pinctrl/mediatek/pinctrl-mt8195.c | 133 +++++++++++++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 181 ++++++++++++++++-- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 35 +++- drivers/pinctrl/mediatek/pinctrl-paris.c | 24 ++- drivers/pinctrl/mediatek/pinctrl-paris.h | 2 +- 5 files changed, 348 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 892e79703f98..275b7ba4386d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -779,6 +779,135 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_adv_range[] = { PIN_FIELD_BASE(45, 45, 1, 0x040, 0x10, 9, 3), }; +static const struct mtk_pin_field_calc mt8195_pin_rsel_range[] = { + PIN_FIELD_BASE(8, 8, 4, 0x0c0, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0c0, 0x10, 0, 3), + PIN_FIELD_BASE(10, 10, 4, 0x0c0, 0x10, 18, 3), + PIN_FIELD_BASE(11, 11, 4, 0x0c0, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 4, 0x0c0, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 4, 0x0c0, 0x10, 6, 3), + PIN_FIELD_BASE(14, 14, 4, 0x0c0, 0x10, 24, 3), + PIN_FIELD_BASE(15, 15, 4, 0x0c0, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, 4, 0x0c0, 0x10, 27, 3), + PIN_FIELD_BASE(17, 17, 4, 0x0c0, 0x10, 12, 3), + PIN_FIELD_BASE(29, 29, 2, 0x080, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 2, 0x080, 0x10, 3, 3), + PIN_FIELD_BASE(34, 34, 1, 0x0e0, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 1, 0x0e0, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x0e0, 0x10, 6, 3), + PIN_FIELD_BASE(45, 45, 1, 0x0e0, 0x10, 9, 3), +}; + +static const struct mtk_pin_rsel mt8195_pin_rsel_val_range[] = { + PIN_RSEL(8, 17, 0x0, 75000, 75000), + PIN_RSEL(8, 17, 0x1, 10000, 5000), + PIN_RSEL(8, 17, 0x2, 5000, 75000), + PIN_RSEL(8, 17, 0x3, 4000, 5000), + PIN_RSEL(8, 17, 0x4, 3000, 75000), + PIN_RSEL(8, 17, 0x5, 2000, 5000), + PIN_RSEL(8, 17, 0x6, 1500, 75000), + PIN_RSEL(8, 17, 0x7, 1000, 5000), + PIN_RSEL(29, 30, 0x0, 75000, 75000), + PIN_RSEL(29, 30, 0x1, 10000, 5000), + PIN_RSEL(29, 30, 0x2, 5000, 75000), + PIN_RSEL(29, 30, 0x3, 4000, 5000), + PIN_RSEL(29, 30, 0x4, 3000, 75000), + PIN_RSEL(29, 30, 0x5, 2000, 5000), + PIN_RSEL(29, 30, 0x6, 1500, 75000), + PIN_RSEL(29, 30, 0x7, 1000, 5000), + PIN_RSEL(34, 35, 0x0, 75000, 75000), + PIN_RSEL(34, 35, 0x1, 10000, 5000), + PIN_RSEL(34, 35, 0x2, 5000, 75000), + PIN_RSEL(34, 35, 0x3, 4000, 5000), + PIN_RSEL(34, 35, 0x4, 3000, 75000), + PIN_RSEL(34, 35, 0x5, 2000, 5000), + PIN_RSEL(34, 35, 0x6, 1500, 75000), + PIN_RSEL(34, 35, 0x7, 1000, 5000), + PIN_RSEL(44, 45, 0x0, 75000, 75000), + PIN_RSEL(44, 45, 0x1, 10000, 5000), + PIN_RSEL(44, 45, 0x2, 5000, 75000), + PIN_RSEL(44, 45, 0x3, 4000, 5000), + PIN_RSEL(44, 45, 0x4, 3000, 75000), + PIN_RSEL(44, 45, 0x5, 2000, 5000), + PIN_RSEL(44, 45, 0x6, 1500, 75000), + PIN_RSEL(44, 45, 0x7, 1000, 5000), +}; + +static const unsigned int mt8195_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE /* 0 */, MTK_PULL_PUPD_R1R0_TYPE /* 1 */, + MTK_PULL_PUPD_R1R0_TYPE /* 2 */, MTK_PULL_PUPD_R1R0_TYPE /* 3 */, + MTK_PULL_PUPD_R1R0_TYPE /* 4 */, MTK_PULL_PUPD_R1R0_TYPE /* 5 */, + MTK_PULL_PU_PD_TYPE /* 6 */, MTK_PULL_PU_PD_TYPE /* 7 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 8 */, MTK_PULL_PU_PD_RSEL_TYPE /* 9 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 10 */, MTK_PULL_PU_PD_RSEL_TYPE /* 11 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 12 */, MTK_PULL_PU_PD_RSEL_TYPE /* 13 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 14 */, MTK_PULL_PU_PD_RSEL_TYPE /* 15 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 16 */, MTK_PULL_PU_PD_RSEL_TYPE /* 17 */, + MTK_PULL_PU_PD_TYPE /* 18 */, MTK_PULL_PU_PD_TYPE /* 19 */, + MTK_PULL_PU_PD_TYPE /* 20 */, MTK_PULL_PU_PD_TYPE /* 21 */, + MTK_PULL_PU_PD_TYPE /* 22 */, MTK_PULL_PU_PD_TYPE /* 23 */, + MTK_PULL_PU_PD_TYPE /* 24 */, MTK_PULL_PU_PD_TYPE /* 25 */, + MTK_PULL_PU_PD_TYPE /* 26 */, MTK_PULL_PU_PD_TYPE /* 27 */, + MTK_PULL_PU_PD_TYPE /* 28 */, MTK_PULL_PU_PD_RSEL_TYPE /* 29 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 30 */, MTK_PULL_PU_PD_TYPE /* 31 */, + MTK_PULL_PU_PD_TYPE /* 32 */, MTK_PULL_PU_PD_TYPE /* 33 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 34 */, MTK_PULL_PU_PD_RSEL_TYPE /* 35 */, + MTK_PULL_PU_PD_TYPE /* 36 */, MTK_PULL_PU_PD_TYPE /* 37 */, + MTK_PULL_PU_PD_TYPE /* 38 */, MTK_PULL_PU_PD_TYPE /* 39 */, + MTK_PULL_PU_PD_TYPE /* 40 */, MTK_PULL_PU_PD_TYPE /* 41 */, + MTK_PULL_PU_PD_TYPE /* 42 */, MTK_PULL_PU_PD_TYPE /* 43 */, + MTK_PULL_PU_PD_RSEL_TYPE /* 44 */, MTK_PULL_PU_PD_RSEL_TYPE /* 45 */, + MTK_PULL_PU_PD_TYPE /* 46 */, MTK_PULL_PU_PD_TYPE /* 47 */, + MTK_PULL_PU_PD_TYPE /* 48 */, MTK_PULL_PU_PD_TYPE /* 49 */, + MTK_PULL_PU_PD_TYPE /* 50 */, MTK_PULL_PU_PD_TYPE /* 51 */, + MTK_PULL_PU_PD_TYPE /* 52 */, MTK_PULL_PU_PD_TYPE /* 53 */, + MTK_PULL_PU_PD_TYPE /* 54 */, MTK_PULL_PU_PD_TYPE /* 55 */, + MTK_PULL_PU_PD_TYPE /* 56 */, MTK_PULL_PU_PD_TYPE /* 57 */, + MTK_PULL_PU_PD_TYPE /* 58 */, MTK_PULL_PU_PD_TYPE /* 59 */, + MTK_PULL_PU_PD_TYPE /* 60 */, MTK_PULL_PU_PD_TYPE /* 61 */, + MTK_PULL_PU_PD_TYPE /* 62 */, MTK_PULL_PU_PD_TYPE /* 63 */, + MTK_PULL_PU_PD_TYPE /* 64 */, MTK_PULL_PU_PD_TYPE /* 65 */, + MTK_PULL_PU_PD_TYPE /* 66 */, MTK_PULL_PU_PD_TYPE /* 67 */, + MTK_PULL_PU_PD_TYPE /* 68 */, MTK_PULL_PU_PD_TYPE /* 69 */, + MTK_PULL_PU_PD_TYPE /* 70 */, MTK_PULL_PU_PD_TYPE /* 71 */, + MTK_PULL_PU_PD_TYPE /* 72 */, MTK_PULL_PU_PD_TYPE /* 73 */, + MTK_PULL_PU_PD_TYPE /* 74 */, MTK_PULL_PU_PD_TYPE /* 75 */, + MTK_PULL_PU_PD_TYPE /* 76 */, MTK_PULL_PUPD_R1R0_TYPE /* 77 */, + MTK_PULL_PUPD_R1R0_TYPE /* 78 */, MTK_PULL_PUPD_R1R0_TYPE /* 79 */, + MTK_PULL_PUPD_R1R0_TYPE /* 80 */, MTK_PULL_PUPD_R1R0_TYPE /* 81 */, + MTK_PULL_PUPD_R1R0_TYPE /* 82 */, MTK_PULL_PUPD_R1R0_TYPE /* 83 */, + MTK_PULL_PUPD_R1R0_TYPE /* 84 */, MTK_PULL_PUPD_R1R0_TYPE /* 85 */, + MTK_PULL_PUPD_R1R0_TYPE /* 86 */, MTK_PULL_PUPD_R1R0_TYPE /* 87 */, + MTK_PULL_PUPD_R1R0_TYPE /* 88 */, MTK_PULL_PUPD_R1R0_TYPE /* 89 */, + MTK_PULL_PUPD_R1R0_TYPE /* 90 */, MTK_PULL_PUPD_R1R0_TYPE /* 91 */, + MTK_PULL_PUPD_R1R0_TYPE /* 92 */, MTK_PULL_PUPD_R1R0_TYPE /* 93 */, + MTK_PULL_PUPD_R1R0_TYPE /* 94 */, MTK_PULL_PUPD_R1R0_TYPE /* 95 */, + MTK_PULL_PUPD_R1R0_TYPE /* 96 */, MTK_PULL_PU_PD_TYPE /* 97 */, + MTK_PULL_PU_PD_TYPE /* 98 */, MTK_PULL_PU_PD_TYPE /* 99 */, + MTK_PULL_PU_PD_TYPE /* 100 */, MTK_PULL_PU_PD_TYPE /* 101 */, + MTK_PULL_PU_PD_TYPE /* 102 */, MTK_PULL_PU_PD_TYPE /* 103 */, + MTK_PULL_PUPD_R1R0_TYPE /* 104 */, MTK_PULL_PUPD_R1R0_TYPE /* 105 */, + MTK_PULL_PUPD_R1R0_TYPE /* 106 */, MTK_PULL_PUPD_R1R0_TYPE /* 107 */, + MTK_PULL_PU_PD_TYPE /* 108 */, MTK_PULL_PU_PD_TYPE /* 109 */, + MTK_PULL_PUPD_R1R0_TYPE /* 110 */, MTK_PULL_PUPD_R1R0_TYPE /* 111 */, + MTK_PULL_PUPD_R1R0_TYPE /* 112 */, MTK_PULL_PUPD_R1R0_TYPE /* 113 */, + MTK_PULL_PUPD_R1R0_TYPE /* 114 */, MTK_PULL_PUPD_R1R0_TYPE /* 115 */, + MTK_PULL_PUPD_R1R0_TYPE /* 116 */, MTK_PULL_PUPD_R1R0_TYPE /* 117 */, + MTK_PULL_PUPD_R1R0_TYPE /* 118 */, MTK_PULL_PUPD_R1R0_TYPE /* 119 */, + MTK_PULL_PUPD_R1R0_TYPE /* 120 */, MTK_PULL_PUPD_R1R0_TYPE /* 121 */, + MTK_PULL_PUPD_R1R0_TYPE /* 122 */, MTK_PULL_PUPD_R1R0_TYPE /* 123 */, + MTK_PULL_PUPD_R1R0_TYPE /* 124 */, MTK_PULL_PUPD_R1R0_TYPE /* 125 */, + MTK_PULL_PUPD_R1R0_TYPE /* 126 */, MTK_PULL_PUPD_R1R0_TYPE /* 127 */, + MTK_PULL_PU_PD_TYPE /* 128 */, MTK_PULL_PU_PD_TYPE /* 129 */, + MTK_PULL_PU_PD_TYPE /* 130 */, MTK_PULL_PU_PD_TYPE /* 131 */, + MTK_PULL_PU_PD_TYPE /* 132 */, MTK_PULL_PU_PD_TYPE /* 133 */, + MTK_PULL_PU_PD_TYPE /* 134 */, MTK_PULL_PU_PD_TYPE /* 135 */, + MTK_PULL_PU_PD_TYPE /* 136 */, MTK_PULL_PU_PD_TYPE /* 137 */, + MTK_PULL_PU_PD_TYPE /* 138 */, MTK_PULL_PU_PD_TYPE /* 139 */, + MTK_PULL_PU_PD_TYPE /* 140 */, MTK_PULL_PU_PD_TYPE /* 141 */, + MTK_PULL_PU_PD_TYPE /* 142 */, MTK_PULL_PU_PD_TYPE /* 143 */, +}; + static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), @@ -793,6 +922,7 @@ static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8195_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8195_pin_rsel_range), }; static const char * const mt8195_pinctrl_register_base_names[] = { @@ -817,6 +947,9 @@ static const struct mtk_pin_soc mt8195_data = { .gpio_m = 0, .base_names = mt8195_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names), + .pull_type = mt8195_pull_type, + .pin_rsel = mt8195_pin_rsel_val_range, + .npin_rsel = ARRAY_SIZE(mt8195_pin_rsel_val_range), .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 5b3b048725cc..b6a89d41f040 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -641,6 +641,9 @@ static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw, } else if (arg == MTK_PUPD_SET_R1R0_11) { r0 = 1; r1 = 1; + } else if (arg == MTK_ENABLE) { + r0 = 1; + r1 = 0; } else { err = -EINVAL; goto out; @@ -661,6 +664,75 @@ static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw, return err; } +static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg, u32 *rsel_val) +{ + const struct mtk_pin_rsel *rsel; + int check; + bool found = false; + + rsel = hw->soc->pin_rsel; + + for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { + if (desc->number >= rsel[check].s_pin && + desc->number <= rsel[check].e_pin) { + if (pullup) { + if (rsel[check].up_rsel == arg) { + found = true; + *rsel_val = rsel[check].rsel_index; + break; + } + } else { + if (rsel[check].down_rsel == arg) { + found = true; + *rsel_val = rsel[check].rsel_index; + break; + } + } + } + } + + if (!found) { + dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n", + arg, desc->number, desc->name); + return -EOPNOTSUPP; + } + + return 0; +} + +static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg) +{ + int err, rsel_val; + + if (hw->soc->pin_rsel) { + /* find pin rsel_index from pin_rsel array*/ + err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); + if (err) + goto out; + } else { + if (arg < MTK_PULL_SET_RSEL_000 || + arg > MTK_PULL_SET_RSEL_111) { + err = -EINVAL; + goto out; + } + + rsel_val -= MTK_PULL_SET_RSEL_000; + } + + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); + if (err) + goto out; + + err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE); + +out: + return err; +} + static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *pullup, u32 *enable) @@ -742,44 +814,117 @@ static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw, return err; } -int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 pullup, u32 arg) +static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) { - int err; + int pu, pd, rsel, err; - err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); - if (!err) + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel); + if (err) goto out; - err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); - if (!err) + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); + if (err) goto out; - err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); + + if (pu == 0 && pd == 0) { + *pullup = 0; + *enable = MTK_DISABLE; + } else if (pu == 1 && pd == 0) { + *pullup = 1; + *enable = rsel + MTK_PULL_SET_RSEL_000; + } else if (pu == 0 && pd == 1) { + *pullup = 0; + *enable = rsel + MTK_PULL_SET_RSEL_000; + } else { + err = -EINVAL; + goto out; + } out: return err; } + +int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg) +{ + int err = -EOPNOTSUPP; + bool try_all_type; + + try_all_type = hw->soc->pull_type ? false : true; + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_RSEL_TYPE)) { + err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); + if (!err) + return err; + } + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PU_PD_TYPE)) { + err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); + if (!err) + return err; + } + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PULLSEL_TYPE)) { + err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, + pullup, arg); + if (!err) + return err; + } + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PUPD_R1R0_TYPE)) { + err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); + if (err) + dev_err(hw->dev, "Invalid pull argument\n"); + } + + return err; +} EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *pullup, u32 *enable) { - int err; + int err = -EOPNOTSUPP; + bool try_all_type; - err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); - if (!err) - goto out; + try_all_type = hw->soc->pull_type ? false : true; - err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); - if (!err) - goto out; + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_RSEL_TYPE)) { + err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable); + if (!err) + return err; + } + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PU_PD_TYPE)) { + err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); + if (!err) + return err; + } - err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PULLSEL_TYPE)) { + err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, + pullup, enable); + if (!err) + return err; + } + + if (try_all_type || + (hw->soc->pull_type[desc->number] & MTK_PULL_PUPD_R1R0_TYPE)) + err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); -out: return err; } EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index a6f1bdb2083b..a3d73f153efe 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -17,6 +17,13 @@ #define MTK_ENABLE 1 #define MTK_PULLDOWN 0 #define MTK_PULLUP 1 +#define MTK_PULL_PU_PD_TYPE BIT(0) +#define MTK_PULL_PULLSEL_TYPE BIT(1) +#define MTK_PULL_PUPD_R1R0_TYPE BIT(2) +#define MTK_PULL_RSEL_TYPE BIT(3) +#define MTK_PULL_PU_PD_RSEL_TYPE (MTK_PULL_PU_PD_TYPE \ + | MTK_PULL_RSEL_TYPE) + #define EINT_NA U16_MAX #define NO_EINT_SUPPORT EINT_NA @@ -42,6 +49,14 @@ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ _x_bits, 32, 1) +#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) { \ + .s_pin = _s_pin, \ + .e_pin = _e_pin, \ + .rsel_index = _rsel_index, \ + .up_rsel = _up_resl, \ + .down_rsel = _down_rsel, \ + } + /* List these attributes which could be modified for the pin */ enum { PINCTRL_PIN_REG_MODE, @@ -67,6 +82,7 @@ enum { PINCTRL_PIN_REG_DRV_E0, PINCTRL_PIN_REG_DRV_E1, PINCTRL_PIN_REG_DRV_ADV, + PINCTRL_PIN_REG_RSEL, PINCTRL_PIN_REG_MAX, }; @@ -129,6 +145,21 @@ struct mtk_pin_field_calc { u8 fixed; }; +/* struct mtk_pin_rsel - the structure that providing bias resistance selection. + * @s_pin: the start pin within the rsel range + * @e_pin: the end pin within the rsel range + * @rsel_index: the rsel bias resistance index + * @up_rsel: the pullup rsel bias resistance value + * @down_rsel: the pulldown rsel bias resistance value + */ +struct mtk_pin_rsel { + u16 s_pin; + u16 e_pin; + u16 rsel_index; + u32 up_rsel; + u32 down_rsel; +}; + /* struct mtk_pin_reg_calc - the structure that holds all ranges used to * determine which register the pin would make use of * for certain pin attribute. @@ -206,6 +237,9 @@ struct mtk_pin_soc { bool ies_present; const char * const *base_names; unsigned int nbase_names; + const unsigned int *pull_type; + const struct mtk_pin_rsel *pin_rsel; + unsigned int npin_rsel; /* Specific pinconfig operations */ int (*bias_disable_set)(struct mtk_pinctrl *hw, @@ -237,7 +271,6 @@ struct mtk_pin_soc { const struct mtk_pin_desc *desc, u32 arg); int (*adv_drive_get)(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val); - /* Specific driver data */ void *driver_data; }; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 85db2e4377f0..8990cfe47d72 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -577,9 +577,9 @@ static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV) ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, - unsigned int gpio, char *buf, unsigned int bufLen) + unsigned int gpio, char *buf, unsigned int buf_len) { - int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1; + int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1; const struct mtk_pin_desc *desc; if (gpio >= hw->soc->npins) @@ -591,6 +591,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pinmux -= hw->soc->nfuncs; mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen); + + /* Case for: R1R0 */ if (pullen == MTK_PUPD_SET_R1R0_00) { pullen = 0; r1 = 0; @@ -607,10 +609,16 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pullen = 1; r1 = 1; r0 = 1; - } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) { - pullen = 0; } - len += scnprintf(buf + len, bufLen - len, + + /* Case for: RSEL */ + if (pullen >= MTK_PULL_SET_RSEL_000 && + pullen <= MTK_PULL_SET_RSEL_111) { + rsel = pullen - MTK_PULL_SET_RSEL_000; + pullen = 1; + } + + len += scnprintf(buf + len, buf_len - len, "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d", gpio, pinmux, @@ -624,10 +632,12 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pullup); if (r1 != -1) { - len += scnprintf(buf + len, bufLen - len, " (%1d %1d)\n", + len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", r1, r0); + } else if (rsel != -1) { + len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); } else { - len += scnprintf(buf + len, bufLen - len, "\n"); + len += scnprintf(buf + len, buf_len - len, "\n"); } return len; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h index afb7650fd25b..681267c0e1a4 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.h +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h @@ -61,7 +61,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc); ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, - unsigned int gpio, char *buf, unsigned int bufLen); + unsigned int gpio, char *buf, unsigned int buf_len); extern const struct dev_pm_ops mtk_paris_pinctrl_pm_ops;