From patchwork Tue Aug 31 16:42:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miles Chen X-Patchwork-Id: 12467593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05C81C4320A for ; Tue, 31 Aug 2021 16:42:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DED8D61057 for ; Tue, 31 Aug 2021 16:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240551AbhHaQnW (ORCPT ); Tue, 31 Aug 2021 12:43:22 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:58486 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240457AbhHaQnN (ORCPT ); Tue, 31 Aug 2021 12:43:13 -0400 X-UUID: fa68547cbaba4a59b40603cfac27e6bf-20210901 X-UUID: fa68547cbaba4a59b40603cfac27e6bf-20210901 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 943461963; Wed, 01 Sep 2021 00:42:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 00:42:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 00:42:12 +0800 From: Miles Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger CC: Wendell Lin , Hanks Chen , , , , , , Miles Chen , Lee Jones Subject: [PATCH v2 1/4] clk: composite: export clk_register_composite Date: Wed, 1 Sep 2021 00:42:07 +0800 Message-ID: <20210831164210.15455-2-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210831164210.15455-1-miles.chen@mediatek.com> References: <20210831164210.15455-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To support module build of mediatek clk drivers, it is necessary to export clk_register_composite. Cc: Stephen Boyd Cc: Hanks Chen Cc: Wendell Lin Cc: Lee Jones Signed-off-by: Miles Chen --- drivers/clk/clk-composite.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 0506046a5f4b..c7b97fb0051b 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -362,6 +362,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, return ERR_CAST(hw); return hw->clk; } +EXPORT_SYMBOL_GPL(clk_register_composite); struct clk *clk_register_composite_pdata(struct device *dev, const char *name, const struct clk_parent_data *parent_data, From patchwork Tue Aug 31 16:42:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miles Chen X-Patchwork-Id: 12467589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B3D3C432BE for ; Tue, 31 Aug 2021 16:42:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57E4E610CD for ; Tue, 31 Aug 2021 16:42:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240513AbhHaQnU (ORCPT ); Tue, 31 Aug 2021 12:43:20 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:58462 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240447AbhHaQnM (ORCPT ); Tue, 31 Aug 2021 12:43:12 -0400 X-UUID: f9d12a002fd7498ba245fe0e1adc524f-20210901 X-UUID: f9d12a002fd7498ba245fe0e1adc524f-20210901 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1558391481; Wed, 01 Sep 2021 00:42:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 00:42:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 00:42:12 +0800 From: Miles Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger CC: Wendell Lin , Hanks Chen , , , , , , Miles Chen , Lee Jones Subject: [PATCH v2 2/4] clk: mediatek: support COMMON_CLK_MEDIATEK module build Date: Wed, 1 Sep 2021 00:42:08 +0800 Message-ID: <20210831164210.15455-3-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210831164210.15455-1-miles.chen@mediatek.com> References: <20210831164210.15455-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To support COMMON_CLK_MEDIATEK module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd Cc: Hanks Chen Cc: Wendell Lin Cc: Lee Jones Signed-off-by: Miles Chen --- drivers/clk/mediatek/clk-apmixed.c | 3 +++ drivers/clk/mediatek/clk-cpumux.c | 3 +++ drivers/clk/mediatek/clk-gate.c | 8 ++++++++ drivers/clk/mediatek/clk-mtk.c | 8 ++++++++ drivers/clk/mediatek/clk-mux.c | 4 ++++ drivers/clk/mediatek/clk-pll.c | 4 ++++ drivers/clk/mediatek/reset.c | 2 ++ 7 files changed, 32 insertions(+) diff --git a/drivers/clk/mediatek/clk-apmixed.c b/drivers/clk/mediatek/clk-apmixed.c index 258d128370f2..caa9119413f1 100644 --- a/drivers/clk/mediatek/clk-apmixed.c +++ b/drivers/clk/mediatek/clk-apmixed.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -97,3 +98,5 @@ struct clk * __init mtk_clk_register_ref2usb_tx(const char *name, return clk; } + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index 79fe09028742..f85c755c9fc1 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -6,6 +6,7 @@ #include #include +#include #include #include "clk-mtk.h" @@ -106,3 +107,5 @@ int mtk_clk_register_cpumuxes(struct device_node *node, return 0; } + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index a35cf0b22150..b02d2f74dd0d 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "clk-mtk.h" #include "clk-gate.h" @@ -122,24 +123,28 @@ const struct clk_ops mtk_clk_gate_ops_setclr = { .enable = mtk_cg_enable, .disable = mtk_cg_disable, }; +EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr); const struct clk_ops mtk_clk_gate_ops_setclr_inv = { .is_enabled = mtk_cg_bit_is_set, .enable = mtk_cg_enable_inv, .disable = mtk_cg_disable_inv, }; +EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv); const struct clk_ops mtk_clk_gate_ops_no_setclr = { .is_enabled = mtk_cg_bit_is_cleared, .enable = mtk_cg_enable_no_setclr, .disable = mtk_cg_disable_no_setclr, }; +EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr); const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = { .is_enabled = mtk_cg_bit_is_set, .enable = mtk_cg_enable_inv_no_setclr, .disable = mtk_cg_disable_inv_no_setclr, }; +EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); struct clk *mtk_clk_register_gate( const char *name, @@ -181,3 +186,6 @@ struct clk *mtk_clk_register_gate( return clk; } +EXPORT_SYMBOL_GPL(mtk_clk_register_gate); + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index cec1c8a27211..cb2dabe60aaf 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -41,6 +42,7 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num) return NULL; } +EXPORT_SYMBOL_GPL(mtk_alloc_clk_data); void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data) @@ -67,6 +69,7 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, clk_data->clks[rc->id] = clk; } } +EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks); void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, struct clk_onecell_data *clk_data) @@ -93,6 +96,7 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, clk_data->clks[ff->id] = clk; } } +EXPORT_SYMBOL_GPL(mtk_clk_register_factors); int mtk_clk_register_gates_with_dev(struct device_node *node, const struct mtk_gate *clks, @@ -145,6 +149,7 @@ int mtk_clk_register_gates(struct device_node *node, return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); } +EXPORT_SYMBOL_GPL(mtk_clk_register_gates); struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) @@ -258,6 +263,7 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs, clk_data->clks[mc->id] = clk; } } +EXPORT_SYMBOL_GPL(mtk_clk_register_composites); void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, @@ -286,3 +292,5 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, clk_data->clks[mcd->id] = clk; } } + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index b0c61709bacc..a507eea26cc7 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "clk-mtk.h" #include "clk-mux.h" @@ -190,3 +191,6 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, return 0; } +EXPORT_SYMBOL_GPL(mtk_clk_register_muxes); + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f440f2cd0b69..399e7b4297c8 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -368,3 +369,6 @@ void mtk_clk_register_plls(struct device_node *node, clk_data->clks[pll->id] = clk; } } +EXPORT_SYMBOL_GPL(mtk_clk_register_plls); + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index cb939c071b0c..9079bfc29ec0 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -137,3 +137,5 @@ void mtk_register_reset_controller_set_clr(struct device_node *np, mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops_set_clr); } + +MODULE_LICENSE("GPL"); From patchwork Tue Aug 31 16:42:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miles Chen X-Patchwork-Id: 12467595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8376EC43214 for ; Tue, 31 Aug 2021 16:42:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CEA0610CF for ; Tue, 31 Aug 2021 16:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240541AbhHaQnV (ORCPT ); Tue, 31 Aug 2021 12:43:21 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:58430 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240429AbhHaQnL (ORCPT ); Tue, 31 Aug 2021 12:43:11 -0400 X-UUID: db85c19447594dc9b0ec9cc2e35a46b6-20210901 X-UUID: db85c19447594dc9b0ec9cc2e35a46b6-20210901 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 833026818; Wed, 01 Sep 2021 00:42:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 00:42:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 00:42:12 +0800 From: Miles Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger CC: Wendell Lin , Hanks Chen , , , , , , Miles Chen , Lee Jones Subject: [PATCH v2 3/4] clk: mediatek: support COMMON_CLK_MT6779 module build Date: Wed, 1 Sep 2021 00:42:09 +0800 Message-ID: <20210831164210.15455-4-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210831164210.15455-1-miles.chen@mediatek.com> References: <20210831164210.15455-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To support COMMON_CLK_MT6779* module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd Cc: Hanks Chen Cc: Wendell Lin Cc: Lee Jones Signed-off-by: Miles Chen --- drivers/clk/mediatek/clk-mt6779-aud.c | 4 +++- drivers/clk/mediatek/clk-mt6779-cam.c | 4 +++- drivers/clk/mediatek/clk-mt6779-img.c | 4 +++- drivers/clk/mediatek/clk-mt6779-ipe.c | 4 +++- drivers/clk/mediatek/clk-mt6779-mfg.c | 4 +++- drivers/clk/mediatek/clk-mt6779-mm.c | 4 +++- drivers/clk/mediatek/clk-mt6779-vdec.c | 4 +++- drivers/clk/mediatek/clk-mt6779-venc.c | 4 +++- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 9 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c index 11b209f95e25..9e889e4c361a 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -114,4 +115,5 @@ static struct platform_driver clk_mt6779_aud_drv = { }, }; -builtin_platform_driver(clk_mt6779_aud_drv); +module_platform_driver(clk_mt6779_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c index 244d4208b7fb..7f07a2a139ac 100644 --- a/drivers/clk/mediatek/clk-mt6779-cam.c +++ b/drivers/clk/mediatek/clk-mt6779-cam.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -63,4 +64,5 @@ static struct platform_driver clk_mt6779_cam_drv = { }, }; -builtin_platform_driver(clk_mt6779_cam_drv); +module_platform_driver(clk_mt6779_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c index 26292a45c613..f0961fa1a286 100644 --- a/drivers/clk/mediatek/clk-mt6779-img.c +++ b/drivers/clk/mediatek/clk-mt6779-img.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -55,4 +56,5 @@ static struct platform_driver clk_mt6779_img_drv = { }, }; -builtin_platform_driver(clk_mt6779_img_drv); +module_platform_driver(clk_mt6779_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c index bb519075639c..8c6f3e154bf3 100644 --- a/drivers/clk/mediatek/clk-mt6779-ipe.c +++ b/drivers/clk/mediatek/clk-mt6779-ipe.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -57,4 +58,5 @@ static struct platform_driver clk_mt6779_ipe_drv = { }, }; -builtin_platform_driver(clk_mt6779_ipe_drv); +module_platform_driver(clk_mt6779_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c index c6ee2a89c070..9f3372886e6b 100644 --- a/drivers/clk/mediatek/clk-mt6779-mfg.c +++ b/drivers/clk/mediatek/clk-mt6779-mfg.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include @@ -52,4 +53,5 @@ static struct platform_driver clk_mt6779_mfg_drv = { }, }; -builtin_platform_driver(clk_mt6779_mfg_drv); +module_platform_driver(clk_mt6779_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c index 059c1a41ac7a..33946e647122 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -105,4 +106,5 @@ static struct platform_driver clk_mt6779_mm_drv = { }, }; -builtin_platform_driver(clk_mt6779_mm_drv); +module_platform_driver(clk_mt6779_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c index 1900da2586a1..f4358844c2e0 100644 --- a/drivers/clk/mediatek/clk-mt6779-vdec.c +++ b/drivers/clk/mediatek/clk-mt6779-vdec.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include @@ -64,4 +65,5 @@ static struct platform_driver clk_mt6779_vdec_drv = { }, }; -builtin_platform_driver(clk_mt6779_vdec_drv); +module_platform_driver(clk_mt6779_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c index b41d1f859edc..ff67084af5aa 100644 --- a/drivers/clk/mediatek/clk-mt6779-venc.c +++ b/drivers/clk/mediatek/clk-mt6779-venc.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include @@ -55,4 +56,5 @@ static struct platform_driver clk_mt6779_venc_drv = { }, }; -builtin_platform_driver(clk_mt6779_venc_drv); +module_platform_driver(clk_mt6779_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 6e0d3a166729..9825385c9f94 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -4,6 +4,7 @@ * Author: Wendell Lin */ +#include #include #include #include @@ -1314,3 +1315,4 @@ static int __init clk_mt6779_init(void) } arch_initcall(clk_mt6779_init); +MODULE_LICENSE("GPL"); From patchwork Tue Aug 31 16:42:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miles Chen X-Patchwork-Id: 12467591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2805FC4320E for ; Tue, 31 Aug 2021 16:42:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10824610E5 for ; Tue, 31 Aug 2021 16:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240523AbhHaQnV (ORCPT ); Tue, 31 Aug 2021 12:43:21 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:58416 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240334AbhHaQnM (ORCPT ); Tue, 31 Aug 2021 12:43:12 -0400 X-UUID: a865064f0d914a93a1e7e60d817add79-20210901 X-UUID: a865064f0d914a93a1e7e60d817add79-20210901 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 993845599; Wed, 01 Sep 2021 00:42:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 00:42:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 00:42:12 +0800 From: Miles Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger CC: Wendell Lin , Hanks Chen , , , , , , Miles Chen , Lee Jones Subject: [PATCH v2 4/4] clk: mediatek: use tristate for COMMON_CLK_MEDAITEK and COMMON_CLK_MT6779 Date: Wed, 1 Sep 2021 00:42:10 +0800 Message-ID: <20210831164210.15455-5-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210831164210.15455-1-miles.chen@mediatek.com> References: <20210831164210.15455-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now we have all necessary exported symbols, change COMMON_CLK_MEDAITEK and COMMON_CLK_MT6779* to tristate. Cc: Stephen Boyd Cc: Hanks Chen Cc: Wendell Lin Cc: Lee Jones Signed-off-by: Miles Chen --- drivers/clk/mediatek/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 886e2d9fced5..62ed2054a849 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -6,7 +6,7 @@ menu "Clock driver for MediaTek SoC" depends on ARCH_MEDIATEK || COMPILE_TEST config COMMON_CLK_MEDIATEK - bool + tristate select RESET_CONTROLLER help MediaTek SoCs' clock support. @@ -204,7 +204,7 @@ config COMMON_CLK_MT6765_MIPI2BSYS This driver supports MediaTek MT6765 mipi2bsys clocks. config COMMON_CLK_MT6779 - bool "Clock driver for MediaTek MT6779" + tristate "Clock driver for MediaTek MT6779" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 @@ -212,49 +212,49 @@ config COMMON_CLK_MT6779 This driver supports MediaTek MT6779 basic clocks. config COMMON_CLK_MT6779_MMSYS - bool "Clock driver for MediaTek MT6779 mmsys" + tristate "Clock driver for MediaTek MT6779 mmsys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 mmsys clocks. config COMMON_CLK_MT6779_IMGSYS - bool "Clock driver for MediaTek MT6779 imgsys" + tristate "Clock driver for MediaTek MT6779 imgsys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 imgsys clocks. config COMMON_CLK_MT6779_IPESYS - bool "Clock driver for MediaTek MT6779 ipesys" + tristate "Clock driver for MediaTek MT6779 ipesys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 ipesys clocks. config COMMON_CLK_MT6779_CAMSYS - bool "Clock driver for MediaTek MT6779 camsys" + tristate "Clock driver for MediaTek MT6779 camsys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 camsys clocks. config COMMON_CLK_MT6779_VDECSYS - bool "Clock driver for MediaTek MT6779 vdecsys" + tristate "Clock driver for MediaTek MT6779 vdecsys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 vdecsys clocks. config COMMON_CLK_MT6779_VENCSYS - bool "Clock driver for MediaTek MT6779 vencsys" + tristate "Clock driver for MediaTek MT6779 vencsys" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 vencsys clocks. config COMMON_CLK_MT6779_MFGCFG - bool "Clock driver for MediaTek MT6779 mfgcfg" + tristate "Clock driver for MediaTek MT6779 mfgcfg" depends on COMMON_CLK_MT6779 help This driver supports MediaTek MT6779 mfgcfg clocks. config COMMON_CLK_MT6779_AUDSYS - bool "Clock driver for Mediatek MT6779 audsys" + tristate "Clock driver for Mediatek MT6779 audsys" depends on COMMON_CLK_MT6779 help This driver supports Mediatek MT6779 audsys clocks.