From patchwork Wed Sep 1 05:39:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12468325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B1CEC432BE for ; Wed, 1 Sep 2021 05:39:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 100056108E for ; Wed, 1 Sep 2021 05:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242061AbhIAFkx (ORCPT ); Wed, 1 Sep 2021 01:40:53 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:43051 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242046AbhIAFkw (ORCPT ); Wed, 1 Sep 2021 01:40:52 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 1A5585804EC; Wed, 1 Sep 2021 01:39:56 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 01 Sep 2021 01:39:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=xNxl1EEs8ZC8t hhUYggA/mA77asD+KQkI79V0Cgwm9k=; b=rb6ZY5b0GyM3AmHeW555IzXGQeEyJ tRwWIupsqdj/FJgzo9vawl1Wr0IepLnC4bjsCjPQE39TA9uwHWBvDvQHHyINpNF/ jrEGH5/OS3zQFPNOFA+UB1AaNgqrGltfdS1zQmOXQ3fDk34BXJdM5Ea8JEY0aSo7 YmsK5wTYwbeARfCyzqaAFi+VpILz3hI6k/SSW2eQeJlOva2fOrGCxeza+qj7VKQ5 Ol2s0fDH0n4urAcBp1Gk38wup+E2lkHibuZQMbBGpQW4RXiMQt+8Z+IRS3PHHROQ RnRAQrhUyC/YSpWRk92rer2xEegST8gJar9zsuNAIHHS4MXwbh8gKsbGA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=xNxl1EEs8ZC8thhUYggA/mA77asD+KQkI79V0Cgwm9k=; b=RI1dDRfS jDayyk9cWjw/fbRuwpz7Ux4OPsClzrV8SZXOeVoxBOr7ar0RrcaLyya86NMThEVx L1V7LVmlog9t8uKvGFa4wPuksx109mDdFiiAu/Yc/zaRA5CmVRrsYtU9JEwOBwov zXMOxpzgxmFE8aoZlIZwkDQoVG+Vss/slVyRe+0RNm1fi83jIBYb17aFTsxsb7tE BPH9Bqm18bFk/a7ORV0UF4I5wD6G/jD3omQWRfEIyID8cmY7mszfAjoGFv4lVxQ2 mY7Q+3toYCDBvV5FeypJQ+4l0cicsT1YPxZ1nXGBw3IXXLijILsvECU5N+hrd+fB SqSHMIVyES8M4A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddruddvvddgleejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 1 Sep 2021 01:39:55 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 1/7] dt-bindings: rtc: sun6i: Add H616 and R329 compatibles Date: Wed, 1 Sep 2021 00:39:45 -0500 Message-Id: <20210901053951.60952-2-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org For these new SoCs, start requiring a complete list of input clocks. For H616, this means bus, hosc, and pll-32k. For R329, this means ahb, bus, and hosc; and optionally ext-osc32k. I'm not sure how to best represent this in the binding... Signed-off-by: Samuel Holland --- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 55 +++++++++++++++++-- include/dt-bindings/clock/sun50i-rtc.h | 12 ++++ 2 files changed, 61 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/sun50i-rtc.h diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index beeb90e55727..3e085db1294f 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,8 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-r329-rtc reg: maxItems: 1 @@ -37,7 +39,24 @@ properties: - description: RTC Alarm 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + - anyOf: + - const: ahb + description: AHB parent for SPI bus clock + - const: bus + description: AHB/APB bus clock for register access + - const: ext-osc32k + description: External 32768 Hz oscillator input + - const: hosc + description: 24 MHz oscillator input + - const: pll-32k + description: 32 kHz clock divided from a PLL clock-output-names: minItems: 1 @@ -85,6 +104,9 @@ allOf: enum: - allwinner,sun8i-h3-rtc - allwinner,sun50i-h5-rtc + - allwinner,sun50i-h6-rtc + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc then: properties: @@ -96,13 +118,35 @@ allOf: properties: compatible: contains: - const: allwinner,sun50i-h6-rtc + enum: + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc then: + clocks: + minItems: 3 # bus, hosc, and (pll-32k [H616] or ahb [R329]) + + clock-names: + minItems: 3 + + required: + - clock-names + + else: + required: + - clock-output-names + + - if: + properties: clock-names + + then: + required: + - clocks # hosc is required + + else: properties: - clock-output-names: - minItems: 3 - maxItems: 3 + clocks: + maxItems: 1 # only ext-osc32k is allowed - if: properties: @@ -127,7 +171,6 @@ required: - compatible - reg - interrupts - - clock-output-names additionalProperties: false diff --git a/include/dt-bindings/clock/sun50i-rtc.h b/include/dt-bindings/clock/sun50i-rtc.h new file mode 100644 index 000000000000..d45e3ff4e105 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-rtc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#define CLK_RTC_SPI 8 + +#endif /* _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ */ From patchwork Wed Sep 1 05:39:46 2021 Content-Type: text/plain; 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Wed, 1 Sep 2021 01:39:56 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 2/7] clk: sunxi-ng: div: Add macro using CLK_HW_INIT_FW_NAME Date: Wed, 1 Sep 2021 00:39:46 -0500 Message-Id: <20210901053951.60952-3-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To use the external clock references from the device tree, instead of hardcoded global names, parents should be referenced with .fw_name. Add a variant of the SUNXI_CCU_M_WITH_GATE initializer which does this. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu_div.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 6682fde6043c..4f8c78a4665b 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -166,6 +166,20 @@ struct ccu_div { SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) +#define SUNXI_CCU_M_FW_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, _flags) \ + struct ccu_div _struct = { \ + .enable = _gate, \ + .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_FW_NAME(_name, \ + _parent, \ + &ccu_div_ops, \ + _flags), \ + }, \ + } + static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Wed Sep 1 05:39:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12468329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A19A0C4320E for ; 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Wed, 1 Sep 2021 01:39:57 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 3/7] clk: sunxi-ng: mux: Add macro using CLK_HW_INIT_PARENTS_DATA Date: Wed, 1 Sep 2021 00:39:47 -0500 Message-Id: <20210901053951.60952-4-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some muxes need the flexibility to specify a combination of internal parents (using .hw) and external parents (using .fw_name). Support this with a version of the SUNXI_CCU_MUX_WITH_GATE macro that uses CLK_HW_INIT_PARENTS_DATA to provide the parent information. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu_mux.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index f165395effb5..5aa5a6f49bd8 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -73,6 +73,20 @@ struct ccu_mux { SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \ _reg, _shift, _width, 0, _flags) +#define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \ + _shift, _width, _gate, _flags) \ + struct ccu_mux _struct = { \ + .enable = _gate, \ + .mux = _SUNXI_CCU_MUX(_shift, _width), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + } \ + } + static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Wed Sep 1 05:39:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12468337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E4D4C43214 for ; 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Wed, 1 Sep 2021 01:39:58 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 4/7] clk: sunxi-ng: mux: Allow muxes to have keys Date: Wed, 1 Sep 2021 00:39:48 -0500 Message-Id: <20210901053951.60952-5-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The muxes in the RTC can only be updated when setting a key field to a specific value. Add a feature flag to denote muxes with this property. Since so far the key value is always the same, it does not need to be provided separately for each mux. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu_common.h | 1 + drivers/clk/sunxi-ng/ccu_mux.c | 7 +++++++ drivers/clk/sunxi-ng/ccu_mux.h | 14 ++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index 98a1834b58bb..fbf16c6b896d 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -17,6 +17,7 @@ #define CCU_FEATURE_LOCK_REG BIT(5) #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) +#define CCU_FEATURE_KEY_FIELD BIT(8) /* MMC timing mode switch bit */ #define CCU_MMC_NEW_TIMING_MODE BIT(30) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 785803cd7e51..fb93cea3a502 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -12,6 +12,8 @@ #include "ccu_gate.h" #include "ccu_mux.h" +#define CCU_MUX_KEY_VALUE 0x16aa0000 + static u16 ccu_mux_get_prediv(struct ccu_common *common, struct ccu_mux_internal *cm, int parent_index) @@ -188,6 +190,11 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); + + /* The key field always reads as zero. */ + if (common->features & CCU_FEATURE_KEY_FIELD) + reg |= CCU_MUX_KEY_VALUE; + reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); writel(reg | (index << cm->shift), common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index 5aa5a6f49bd8..6ca15e43f9c8 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -87,6 +87,20 @@ struct ccu_mux { } \ } +#define SUNXI_CCU_MUX_HW_WITH_KEY(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct ccu_mux _struct = { \ + .mux = _SUNXI_CCU_MUX(_shift, _width), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_KEY_FIELD, \ + .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + } \ + } + static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Wed Sep 1 05:39:49 2021 Content-Type: text/plain; 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Wed, 1 Sep 2021 01:39:58 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 5/7] clk: sunxi-ng: Add support for the sun50i RTC clocks Date: Wed, 1 Sep 2021 00:39:49 -0500 Message-Id: <20210901053951.60952-6-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The RTC power domain in sun50i SoCs manages the 16 MHz RC oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power domain handles the 24 MHz DCXO (called "HOSC", "dcxo24M", or "osc24M") as well. The H6 also introduces a calibration circuit for IOSC. Later SoCs introduce further variations on the design: - H616 adds an additional mux for the 32 kHz fanout source. - R329 adds an additional mux for the RTC timekeeping clock, a clock for the SPI bus between power domains inside the RTC, and removes the IOSC calibration functionality. Take advantage of the CCU framework to handle this increased complexity. The CCU framework provides pre-made widgets for the mux/gate/divider combinations. And it allows plugging in different clocks for the same specifiers based on the compatible string. This driver is intended to be a drop-in replacement for the existing RTC clock driver. So some runtime adjustment of the clock parents is needed, both to handle hardware differences, and to support the old binding which omitted some of the input clocks. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/sun50i-rtc-ccu.c | 344 ++++++++++++++++++++++++++ drivers/clk/sunxi-ng/sun50i-rtc-ccu.h | 15 ++ 4 files changed, 366 insertions(+) create mode 100644 drivers/clk/sunxi-ng/sun50i-rtc-ccu.c create mode 100644 drivers/clk/sunxi-ng/sun50i-rtc-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index ee383658ff4d..8d9d486c4673 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -42,6 +42,12 @@ config SUN50I_H6_R_CCU default ARM64 && ARCH_SUNXI depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST +config SUN50I_RTC_CCU + bool "Support for the Allwinner H6/H616/R329 RTC CCU" + default ARM64 && ARCH_SUNXI + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST + depends on SUNXI_CCU=y + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default MACH_SUN4I diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6e9eb004fca0..99554b13d150 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SUN50I_A100_R_CCU) += sun50i-a100-r-ccu.o obj-$(CONFIG_SUN50I_H6_CCU) += sun50i-h6-ccu.o obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN50I_H6_R_CCU) += sun50i-h6-r-ccu.o +obj-$(CONFIG_SUN50I_RTC_CCU) += sun50i-rtc-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o diff --git a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c new file mode 100644 index 000000000000..1dfa05c2f0e9 --- /dev/null +++ b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mux.h" + +#include "sun50i-rtc-ccu.h" + +#define IOSC_ACCURACY 300000000 /* 30% */ +#define IOSC_RATE 16000000 + +#define LOSC_RATE 32768 +#define LOSC_RATE_SHIFT 15 + +#define LOSC_CTRL_KEY 0x16aa0000 + +#define IOSC_32K_CLK_DIV_REG 0x8 +#define IOSC_32K_CLK_DIV GENMASK(4, 0) +#define IOSC_32K_PRE_DIV 32 + +#define IOSC_CLK_CALI_REG 0xc +#define IOSC_CLK_CALI_DIV_ONES 22 +#define IOSC_CLK_CALI_EN BIT(1) +#define IOSC_CLK_CALI_SRC_SEL BIT(0) + +#define DCXO_CTRL_REG 0x160 +#define DCXO_CTRL_CLK16M_RC_EN BIT(0) + +static bool have_iosc_calib; + +static int ccu_iosc_enable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static void ccu_iosc_disable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static int ccu_iosc_is_enabled(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + if (have_iosc_calib) { + u32 reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* + * Recover the IOSC frequency by shifting the ones place of + * (fixed-point divider * 32768) into bit zero. + */ + if (reg & IOSC_CLK_CALI_EN) + return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT); + } + + return IOSC_RATE; +} + +static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + return IOSC_ACCURACY; +} + +static const struct clk_ops ccu_iosc_ops = { + .enable = ccu_iosc_enable, + .disable = ccu_iosc_disable, + .is_enabled = ccu_iosc_is_enabled, + .recalc_rate = ccu_iosc_recalc_rate, + .recalc_accuracy = ccu_iosc_recalc_accuracy, +}; + +static struct ccu_common iosc_clk = { + .reg = DCXO_CTRL_REG, + .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, + CLK_GET_RATE_NOCACHE), +}; + +static int ccu_iosc_32k_enable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + unsigned long flags; + u32 reg; + + if (!have_iosc_calib) + return 0; + + spin_lock_irqsave(cm->lock, flags); + + reg = readl(cm->base + IOSC_CLK_CALI_REG); + writel(reg | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL, + cm->base + IOSC_CLK_CALI_REG); + + spin_unlock_irqrestore(cm->lock, flags); + + return 0; +} + +static void ccu_iosc_32k_disable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + unsigned long flags; + u32 reg; + + if (!have_iosc_calib) + return; + + spin_lock_irqsave(cm->lock, flags); + + reg = readl(cm->base + IOSC_CLK_CALI_REG); + writel(reg & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL), + cm->base + IOSC_CLK_CALI_REG); + + spin_unlock_irqrestore(cm->lock, flags); +} + +static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + u32 reg; + + if (have_iosc_calib) { + reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (reg & IOSC_CLK_CALI_SRC_SEL) + return LOSC_RATE; + } + + reg = readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV; + + return parent_rate / IOSC_32K_PRE_DIV / (reg + 1); +} + +static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + u32 reg; + + if (have_iosc_calib) { + reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (reg & IOSC_CLK_CALI_SRC_SEL) + return 0; + } + + return parent_accuracy; +} + +static const struct clk_ops ccu_iosc_32k_ops = { + .enable = ccu_iosc_32k_enable, + .disable = ccu_iosc_32k_disable, + .recalc_rate = ccu_iosc_32k_recalc_rate, + .recalc_accuracy = ccu_iosc_32k_recalc_accuracy, +}; + +static struct ccu_common iosc_32k_clk = { + .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, + &ccu_iosc_32k_ops, 0), +}; + +/* The old binding did not use clock-names, so fw_name may get cleared out. */ +static struct clk_parent_data ext_osc32k[] = { + { .fw_name = "ext-osc32k", .index = 0 } +}; +static SUNXI_CCU_GATE_DATA(ext_osc32k_gate_clk, "ext-osc32k-gate", + ext_osc32k, 0x0, BIT(4), 0); + +static const struct clk_hw *osc32k_parents[] = { &iosc_32k_clk.hw, + &ext_osc32k_gate_clk.common.hw }; +static SUNXI_CCU_MUX_HW_WITH_KEY(osc32k_clk, "osc32k", osc32k_parents, + 0x0, 0, 1, 0); + +/* Fall back to the global name for RTC nodes without an osc24M reference. */ +static struct clk_parent_data osc24M[] = { + { .fw_name = "hosc", .name = "osc24M" } +}; +static struct ccu_gate osc24M_32k_clk = { + .enable = BIT(16), + .common = { + .reg = 0x60, + .prediv = 750, + .features = CCU_FEATURE_ALL_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M, + &ccu_gate_ops, 0), + }, +}; + +static CLK_FIXED_FACTOR_HW(rtc_32k_fixed_clk, "rtc-32k", + &osc32k_clk.common.hw, 1, 1, 0); + +static const struct clk_hw *rtc_32k_parents[] = { &osc32k_clk.common.hw, + &osc24M_32k_clk.common.hw }; +static SUNXI_CCU_MUX_HW_WITH_KEY(rtc_32k_mux_clk, "rtc-32k", rtc_32k_parents, + 0x0, 1, 1, 0); + +static struct clk_parent_data osc32k_fanout_parents[] = { + { .hw = &osc32k_clk.common.hw }, + /* Parent is modified depending on the hardware variant. */ + { .fw_name = "pll-32k" }, + { .hw = &osc24M_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "rtc-32k-fanout", + osc32k_fanout_parents, + 0x60, 1, 2, BIT(0), 0); + +static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", + 0x310, 0, 5, BIT(31), 0); + +static struct ccu_common *sun50i_h616_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &osc32k_fanout_clk.common, +}; + +static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &rtc_32k_mux_clk.common, + &osc32k_fanout_clk.common, + &rtc_spi_clk.common, +}; + +static struct clk_hw_onecell_data sun50i_h616_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = NULL, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_fixed_clk.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + +static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_mux_clk.common.hw, + [CLK_RTC_SPI] = &rtc_spi_clk.common.hw, + }, +}; + +static const struct sunxi_ccu_desc sun50i_h616_rtc_ccu_desc = { + .ccu_clks = sun50i_h616_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_rtc_ccu_clks), + + .hw_clks = &sun50i_h616_rtc_ccu_hw_clks, +}; + +static const struct sunxi_ccu_desc sun50i_r329_rtc_ccu_desc = { + .ccu_clks = sun50i_r329_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_r329_rtc_ccu_clks), + + .hw_clks = &sun50i_r329_rtc_ccu_hw_clks, +}; + +static void __init sunxi_rtc_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *desc) +{ + void __iomem *reg; + int i; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("%pOF: Failed to map registers\n", node); + return; + } + + /* ext-osc32k was the only input clock in the old binding. */ + if (!of_property_read_bool(node, "clock-names")) + ext_osc32k[0].fw_name = NULL; + + /* Rename the first 3 clocks to respect clock-output-names. */ + for (i = 0; i < 3; ++i) { + struct clk_init_data *init = (struct clk_init_data *) + desc->hw_clks->hws[i]->init; + + of_property_read_string_index(node, "clock-output-names", i, + &init->name); + } + + of_sunxi_ccu_probe(node, reg, desc); +} + +static void __init sun50i_h616_rtc_ccu_setup(struct device_node *node) +{ + have_iosc_calib = 1; + + /* Remove the second parent as external osc32k is not supported. */ + osc32k_parents[1] = &iosc_32k_clk.hw; + + sunxi_rtc_ccu_init(node, &sun50i_h616_rtc_ccu_desc); +} +CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_ccu, "allwinner,sun50i-h616-rtc", + sun50i_h616_rtc_ccu_setup); + +static void __init sun50i_r329_rtc_ccu_setup(struct device_node *node) +{ + have_iosc_calib = 0; + + osc32k_fanout_parents[1] = (struct clk_parent_data) { + .hw = &ext_osc32k_gate_clk.common.hw + }; + + sunxi_rtc_ccu_init(node, &sun50i_r329_rtc_ccu_desc); +} +CLK_OF_DECLARE_DRIVER(sun50i_r329_rtc_ccu, "allwinner,sun50i-r329-rtc", + sun50i_r329_rtc_ccu_setup); diff --git a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.h b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.h new file mode 100644 index 000000000000..7bd4d8700612 --- /dev/null +++ b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _CCU_SUN50I_RTC_H +#define _CCU_SUN50I_RTC_H + +#include + +#define CLK_IOSC_32K 4 +#define CLK_EXT_OSC32K_GATE 5 +#define CLK_OSC24M_32K 6 +#define CLK_RTC_32K 7 + +#define CLK_NUMBER (CLK_RTC_SPI + 1) + +#endif /* _CCU_SUN50I_RTC_H */ From patchwork Wed Sep 1 05:39:50 2021 Content-Type: text/plain; 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Wed, 1 Sep 2021 01:39:59 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 6/7] [DO NOT MERGE] clk: sunxi-ng: Add support for H6 Date: Wed, 1 Sep 2021 00:39:50 -0500 Message-Id: <20210901053951.60952-7-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org H6 has IOSC calibration and an ext-osc32k input. H6 has the osc32k mux and the rtc-32k mux, but no fanout mux. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/sun50i-rtc-ccu.c | 49 +++++++++++++++++++++++++++ drivers/rtc/rtc-sun6i.c | 17 ---------- 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c index 1dfa05c2f0e9..9603dc0d3d7b 100644 --- a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c +++ b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c @@ -227,6 +227,16 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "rtc-32k-fanout", static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", 0x310, 0, 5, BIT(31), 0); +static struct ccu_common *sun50i_h6_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &rtc_32k_mux_clk.common, + &osc32k_fanout_clk.common, +}; + static struct ccu_common *sun50i_h616_rtc_ccu_clks[] = { &iosc_clk, &iosc_32k_clk, @@ -246,6 +256,21 @@ static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { &rtc_spi_clk.common, }; +static struct clk_hw_onecell_data sun50i_h6_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_mux_clk.common.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + static struct clk_hw_onecell_data sun50i_h616_rtc_ccu_hw_clks = { .num = CLK_NUMBER, .hws = { @@ -276,6 +301,13 @@ static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { }, }; +static const struct sunxi_ccu_desc sun50i_h6_rtc_ccu_desc = { + .ccu_clks = sun50i_h6_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_rtc_ccu_clks), + + .hw_clks = &sun50i_h6_rtc_ccu_hw_clks, +}; + static const struct sunxi_ccu_desc sun50i_h616_rtc_ccu_desc = { .ccu_clks = sun50i_h616_rtc_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h616_rtc_ccu_clks), @@ -318,6 +350,23 @@ static void __init sunxi_rtc_ccu_init(struct device_node *node, of_sunxi_ccu_probe(node, reg, desc); } +static void __init sun50i_h6_rtc_ccu_setup(struct device_node *node) +{ + struct clk_init_data *init; + + have_iosc_calib = 1; + + /* Casting away the const from a pointer to a non-const anonymous object... */ + init = (struct clk_init_data *)osc32k_fanout_clk.common.hw.init; + + /* Fanout only has one parent: osc32k. */ + init->num_parents = 1; + + sunxi_rtc_ccu_init(node, &sun50i_h6_rtc_ccu_desc); +} +CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_ccu, "allwinner,sun50i-h6-rtc", + sun50i_h6_rtc_ccu_setup); + static void __init sun50i_h616_rtc_ccu_setup(struct device_node *node) { have_iosc_calib = 1; diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index adec1b14a8de..f7cbbf57f112 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -363,23 +363,6 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", sun8i_h3_rtc_clk_init); -static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { - .rc_osc_rate = 16000000, - .fixed_prescaler = 32, - .has_prescaler = 1, - .has_out_clk = 1, - .export_iosc = 1, - .has_losc_en = 1, - .has_auto_swt = 1, -}; - -static void __init sun50i_h6_rtc_clk_init(struct device_node *node) -{ - sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); -} -CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", - sun50i_h6_rtc_clk_init); - /* * The R40 user manual is self-conflicting on whether the prescaler is * fixed or configurable. The clock diagram shows it as fixed, but there From patchwork Wed Sep 1 05:39:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12468331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3E1DC43214 for ; Wed, 1 Sep 2021 05:40:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 995186108E for ; Wed, 1 Sep 2021 05:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242105AbhIAFk7 (ORCPT ); Wed, 1 Sep 2021 01:40:59 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:50255 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242046AbhIAFk5 (ORCPT ); Wed, 1 Sep 2021 01:40:57 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 911A45805C3; Wed, 1 Sep 2021 01:40:00 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 01 Sep 2021 01:40:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=AW1628GhGotzk KH/YttaXfCJmdGOn33kQwWfNnzFq50=; b=nGipR7Dph/pipc/kQf2JrU8+ilLQT jXi/e+flhRlG2lEpHK7GwU538Th5XnZx01WburK5hTt0Au7ILf89VX1SvcRstO8O WpN7sQYS069HxziKPLicRBgcIYrPeqUzHoKRggNyXivIBCAEkCr9N+9R6PFVHSgl wmaT2vP8Nz8IieSGAdqMWPcXYVsJeQX7P1JAYucjFv1LaxHAulJsAFDJ+fbLakK3 lVq/T2JoVjlUEX7M54oTz544cJ5pgP0fsfdLG8T/dvHeVDOvgJ9UA2/yWZEnZNhb 7zxAV2aUFggisKUZjoB26S0L2ChHjZnR+NIoCK6TC+dKdahl8r0c5H2Qg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=AW1628GhGotzkKH/YttaXfCJmdGOn33kQwWfNnzFq50=; b=VRQ0urmm Ez12LOISmZhfRTOwNMl3S95eNhoAUi10A3IGnE4hF8GP8ZIJ+8akBWZPMcKq5Cl2 lKuSJWAVeWtbMKzbYdqe9MjxtQ4XK24mUi8NvhdRmLj3xvarLeumvtUfVLFxi+Ba KrG/k5uDQgIpGabKJGSJnqj+cMmZsn0CFcJpY1OjAr9/Cu0Cah37ZniAgHKOw2/6 fPl4ltmZoJh0H3NBsWrVZ4058sBozGoaqEQOd12qGY/aU+7ux6ZDXrqSN+C0OIWP TeSWuSQFwQ9vyKN38zYPjVdgVl+Ax5e4gZxd8E9533qWYvtvf+ImAJ6ek58iEsOK PFVdOPesQBr/VQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddruddvvddgleejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 1 Sep 2021 01:39:59 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 7/7] [DO NOT MERGE] clk: sunxi-ng: Add support for T5 Date: Wed, 1 Sep 2021 00:39:51 -0500 Message-Id: <20210901053951.60952-8-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The T5 RTC is similar to the H616 RTC (no rtc-32k mux, pll-32k as the second fanout input), except that it adds the ext-osc32k input. It also isn't a "sun50i" SoC, so it creates a bit of a naming problem... Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/sun50i-rtc-ccu.c | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c index 9603dc0d3d7b..fe6b21a24193 100644 --- a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c +++ b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c @@ -227,6 +227,15 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "rtc-32k-fanout", static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", 0x310, 0, 5, BIT(31), 0); +static struct ccu_common *sun8i_t5_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &osc32k_fanout_clk.common, +}; + static struct ccu_common *sun50i_h6_rtc_ccu_clks[] = { &iosc_clk, &iosc_32k_clk, @@ -256,6 +265,21 @@ static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { &rtc_spi_clk.common, }; +static struct clk_hw_onecell_data sun8i_t5_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_fixed_clk.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + static struct clk_hw_onecell_data sun50i_h6_rtc_ccu_hw_clks = { .num = CLK_NUMBER, .hws = { @@ -301,6 +325,13 @@ static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { }, }; +static const struct sunxi_ccu_desc sun8i_t5_rtc_ccu_desc = { + .ccu_clks = sun8i_t5_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_t5_rtc_ccu_clks), + + .hw_clks = &sun8i_t5_rtc_ccu_hw_clks, +}; + static const struct sunxi_ccu_desc sun50i_h6_rtc_ccu_desc = { .ccu_clks = sun50i_h6_rtc_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_rtc_ccu_clks), @@ -350,6 +381,15 @@ static void __init sunxi_rtc_ccu_init(struct device_node *node, of_sunxi_ccu_probe(node, reg, desc); } +static void __init sun8i_t5_rtc_ccu_setup(struct device_node *node) +{ + have_iosc_calib = 1; + + sunxi_rtc_ccu_init(node, &sun8i_t5_rtc_ccu_desc); +} +CLK_OF_DECLARE_DRIVER(sun8i_t5_rtc_ccu, "allwinner,sun8i-t5-rtc", + sun8i_t5_rtc_ccu_setup); + static void __init sun50i_h6_rtc_ccu_setup(struct device_node *node) { struct clk_init_data *init;