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Mon, 10 Dec 2018 04:10:48 +0000 Received: from VI1PR04MB5726.eurprd04.prod.outlook.com ([fe80::595a:9890:8397:5d51]) by VI1PR04MB5726.eurprd04.prod.outlook.com ([fe80::595a:9890:8397:5d51%4]) with mapi id 15.20.1404.026; Mon, 10 Dec 2018 04:10:48 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "boris.brezillon@bootlin.com" , "broonie@kernel.org" , "marek.vasut@gmail.com" , "vigneshr@ti.com" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" CC: "robh@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [RESEND PATCH v5 5/7] mtd: m25p80: add support of octal mode I/O transfer Thread-Topic: [RESEND PATCH v5 5/7] mtd: m25p80: add support of octal mode I/O transfer Thread-Index: AQHUkD5UftDKlfWJEUCGwj0wjo/Y/w== Date: Mon, 10 Dec 2018 04:10:48 +0000 Message-ID: <1544414934-5286-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR02CA0047.apcprd02.prod.outlook.com (2603:1096:3:18::35) To VI1PR04MB5726.eurprd04.prod.outlook.com (2603:10a6:803:e4::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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Assign hw-capability mask bits for octal transfer. Signed-off-by: Yogesh Gaur --- Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Incorporated review comments of Boris. drivers/mtd/devices/m25p80.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index c4a1d04..651bab6 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem) spi_mem_set_drvdata(spimem, flash); flash->spimem = spimem; - if (spi->mode & SPI_RX_QUAD) { + if (spi->mode & SPI_RX_OCTAL) { + hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; + + if (spi->mode & SPI_TX_OCTAL) + hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 | + SNOR_HWCAPS_PP_1_1_8 | + SNOR_HWCAPS_PP_1_8_8); + } else if (spi->mode & SPI_RX_QUAD) { hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; if (spi->mode & SPI_TX_QUAD)