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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=oss.nxp.com; Received: from VI1PR04MB5151.eurprd04.prod.outlook.com (2603:10a6:803:61::28) by VI1PR0401MB2654.eurprd04.prod.outlook.com (2603:10a6:800:58::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.21; Fri, 3 Sep 2021 14:53:55 +0000 Received: from VI1PR04MB5151.eurprd04.prod.outlook.com ([fe80::499b:ba92:db2e:3f28]) by VI1PR04MB5151.eurprd04.prod.outlook.com ([fe80::499b:ba92:db2e:3f28%7]) with mapi id 15.20.4457.026; Fri, 3 Sep 2021 14:53:55 +0000 From: Daniel Baluta To: broonie@kernel.org, pierre-louis.bossart@linux.intel.com, lgirdwood@gmail.com, robh+dt@kernel.org, ranjani.sridharan@linux.intel.com, kai.vehmanen@linux.intel.com Subject: [PATCH v2 1/2] ASoC: SOF: imx: Add code to manage DSP related clocks Date: Fri, 3 Sep 2021 17:53:39 +0300 Message-Id: <20210903145340.225511-2-daniel.baluta@oss.nxp.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210903145340.225511-1-daniel.baluta@oss.nxp.com> References: <20210903145340.225511-1-daniel.baluta@oss.nxp.com> X-ClientProxiedBy: VI1PR07CA0200.eurprd07.prod.outlook.com (2603:10a6:802:3f::24) To VI1PR04MB5151.eurprd04.prod.outlook.com (2603:10a6:803:61::28) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (2a02:2f08:5708:8600:fd8d:b9e7:97b5:dd4a) by VI1PR07CA0200.eurprd07.prod.outlook.com (2603:10a6:802:3f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.4 via Frontend Transport; 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We choose to enable DAI clocks here because of the way i.MX8/i.MX8X design handles resources (including clocks). All clocks are managed by a separate core (named SCU) which communicates with Linux managed ARM core via a well known API. We parse and enable the clocks in probe function and disable them in remove function. Future patches will introduce Power Management support so that we disable clocks while DSP is not used or system enters power save. Signed-off-by: Daniel Baluta Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/imx/imx-common.c | 44 ++++++++++++++++++++++++++++++++++ sound/soc/sof/imx/imx-common.h | 13 ++++++++++ sound/soc/sof/imx/imx8.c | 37 ++++++++++++++++++++++++++++ sound/soc/sof/imx/imx8m.c | 34 ++++++++++++++++++++++++++ 4 files changed, 128 insertions(+) diff --git a/sound/soc/sof/imx/imx-common.c b/sound/soc/sof/imx/imx-common.c index 8826ef94f04a..f9d650ad3846 100644 --- a/sound/soc/sof/imx/imx-common.c +++ b/sound/soc/sof/imx/imx-common.c @@ -74,4 +74,48 @@ void imx8_dump(struct snd_sof_dev *sdev, u32 flags) } EXPORT_SYMBOL(imx8_dump); +int imx8_parse_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) +{ + int ret; + + ret = devm_clk_bulk_get(sdev->dev, clks->num_dsp_clks, clks->dsp_clks); + if (ret) { + dev_err(sdev->dev, "Failed to request DSP clocks\n"); + return ret; + } + + ret = devm_clk_bulk_get_optional(sdev->dev, clks->num_dai_clks, clks->dai_clks); + if (ret) { + dev_err(sdev->dev, "Failed to request DAI clks\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(imx8_parse_clocks); + +int imx8_enable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) +{ + int ret; + + ret = clk_bulk_prepare_enable(clks->num_dsp_clks, clks->dsp_clks); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(clks->num_dai_clks, clks->dai_clks); + if (ret) { + clk_bulk_disable_unprepare(clks->num_dsp_clks, clks->dsp_clks); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(imx8_enable_clocks); + +void imx8_disable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) +{ + clk_bulk_disable_unprepare(clks->num_dsp_clks, clks->dsp_clks); + clk_bulk_disable_unprepare(clks->num_dai_clks, clks->dai_clks); +} +EXPORT_SYMBOL(imx8_disable_clocks); + MODULE_LICENSE("Dual BSD/GPL"); diff --git a/sound/soc/sof/imx/imx-common.h b/sound/soc/sof/imx/imx-common.h index 1cc7d6704182..54fba9fcd861 100644 --- a/sound/soc/sof/imx/imx-common.h +++ b/sound/soc/sof/imx/imx-common.h @@ -3,6 +3,8 @@ #ifndef __IMX_COMMON_H__ #define __IMX_COMMON_H__ +#include + #define EXCEPT_MAX_HDR_SIZE 0x400 #define IMX8_STACK_DUMP_SIZE 32 @@ -13,4 +15,15 @@ void imx8_get_registers(struct snd_sof_dev *sdev, void imx8_dump(struct snd_sof_dev *sdev, u32 flags); +struct imx_clocks { + struct clk_bulk_data *dsp_clks; + int num_dsp_clks; + struct clk_bulk_data *dai_clks; + int num_dai_clks; +}; + +int imx8_parse_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks); +int imx8_enable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks); +void imx8_disable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks); + #endif diff --git a/sound/soc/sof/imx/imx8.c b/sound/soc/sof/imx/imx8.c index fc1720c211a3..5370d34edd61 100644 --- a/sound/soc/sof/imx/imx8.c +++ b/sound/soc/sof/imx/imx8.c @@ -41,6 +41,25 @@ #define MBOX_OFFSET 0x800000 #define MBOX_SIZE 0x1000 +/* DSP clocks */ +struct clk_bulk_data imx8_dsp_clks[] = { + { .id = "ipg" }, + { .id = "ocram" }, + { .id = "core" }, +}; + +/* DAI clocks */ +struct clk_bulk_data imx8_dai_clks[] = { + { .id = "esai0_core" }, + { .id = "esai0_extal" }, + { .id = "esai0_spba" }, + { .id = "sai1_bus" }, + { .id = "sai1_mclk0" }, + { .id = "sai1_mclk1" }, + { .id = "sai1_mclk2" }, + { .id = "sai1_mclk3" }, +}; + struct imx8_priv { struct device *dev; struct snd_sof_dev *sdev; @@ -57,6 +76,7 @@ struct imx8_priv { struct device **pd_dev; struct device_link **link; + struct imx_clocks *clks; }; static void imx8_get_reply(struct snd_sof_dev *sdev) @@ -223,6 +243,10 @@ static int imx8_probe(struct snd_sof_dev *sdev) if (!priv) return -ENOMEM; + priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + sdev->num_cores = 1; sdev->pdata->hw_pdata = priv; priv->dev = sdev->dev; @@ -336,6 +360,18 @@ static int imx8_probe(struct snd_sof_dev *sdev) /* set default mailbox offset for FW ready message */ sdev->dsp_box.offset = MBOX_OFFSET; + /* init clocks info */ + priv->clks->dsp_clks = imx8_dsp_clks; + priv->clks->num_dsp_clks = ARRAY_SIZE(imx8_dsp_clks); + priv->clks->dai_clks = imx8_dai_clks; + priv->clks->num_dai_clks = ARRAY_SIZE(imx8_dai_clks); + + ret = imx8_parse_clocks(sdev, priv->clks); + if (ret < 0) + goto exit_pdev_unregister; + + imx8_enable_clocks(sdev, priv->clks); + return 0; exit_pdev_unregister: @@ -354,6 +390,7 @@ static int imx8_remove(struct snd_sof_dev *sdev) struct imx8_priv *priv = sdev->pdata->hw_pdata; int i; + imx8_disable_clocks(sdev, priv->clks); platform_device_unregister(priv->ipc_dev); for (i = 0; i < priv->num_domains; i++) { diff --git a/sound/soc/sof/imx/imx8m.c b/sound/soc/sof/imx/imx8m.c index 30624fafc632..fea1b72bebaa 100644 --- a/sound/soc/sof/imx/imx8m.c +++ b/sound/soc/sof/imx/imx8m.c @@ -23,6 +23,21 @@ #define MBOX_OFFSET 0x800000 #define MBOX_SIZE 0x1000 +struct clk_bulk_data imx8m_dsp_clks[] = { + { .id = "ipg" }, + { .id = "ocram" }, + { .id = "core" }, +}; + +struct clk_bulk_data imx8m_dai_clks[] = { + { .id = "sai3_bus" }, + { .id = "sai3_mclk0" }, + { .id = "sai3_mclk1" }, + { .id = "sai3_mclk2" }, + { .id = "sai3_mclk3" }, + { .id = "sdma3_root" }, +}; + struct imx8m_priv { struct device *dev; struct snd_sof_dev *sdev; @@ -30,6 +45,8 @@ struct imx8m_priv { /* DSP IPC handler */ struct imx_dsp_ipc *dsp_ipc; struct platform_device *ipc_dev; + + struct imx_clocks *clks; }; static void imx8m_get_reply(struct snd_sof_dev *sdev) @@ -143,6 +160,10 @@ static int imx8m_probe(struct snd_sof_dev *sdev) if (!priv) return -ENOMEM; + priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + sdev->num_cores = 1; sdev->pdata->hw_pdata = priv; priv->dev = sdev->dev; @@ -211,6 +232,18 @@ static int imx8m_probe(struct snd_sof_dev *sdev) /* set default mailbox offset for FW ready message */ sdev->dsp_box.offset = MBOX_OFFSET; + /* init clocks info */ + priv->clks->dsp_clks = imx8m_dsp_clks; + priv->clks->num_dsp_clks = ARRAY_SIZE(imx8m_dsp_clks); + priv->clks->dai_clks = imx8m_dai_clks; + priv->clks->num_dai_clks = ARRAY_SIZE(imx8m_dai_clks); + + ret = imx8_parse_clocks(sdev, priv->clks); + if (ret < 0) + goto exit_pdev_unregister; + + imx8_enable_clocks(sdev, priv->clks); + return 0; exit_pdev_unregister: @@ -222,6 +255,7 @@ static int imx8m_remove(struct snd_sof_dev *sdev) { struct imx8m_priv *priv = sdev->pdata->hw_pdata; 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By design we choose to manage DAI/DMA clocks from the kernel side because of the architecture of some i.MX8 boards. Clocks are handled by a special M4 core which runs a special firmware called SCFW (System Controler firmware). This communicates with A cores running Linux via a special Messaging Unit and implements a custom API which is already implemented by the Linux kernel i.MX clocks implementation. Note that these clocks are optional. We can use the DSP without them. Signed-off-by: Daniel Baluta --- .../devicetree/bindings/dsp/fsl,dsp.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index 7afc9f2be13a..1453668c0194 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -24,16 +24,49 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: ipg clock - description: ocram clock - description: core clock + - description: esai0 core clock for accessing registers + - description: esai0 baud clock + - description: esai0 system clock + - description: esai0 spba clock required when ESAI is placed in slave mode + - description: SAI1 bus clock + - description: SAI1 master clock 0 + - description: SAI1 master clock 1 + - description: SAI1 master clock 2 + - description: SAI1 master clock 3 + - description: SAI3 bus clock + - description: SAI3 master clock 0 + - description: SAI3 master clock 1 + - description: SAI3 master clock 2 + - description: SAI3 master clock 3 + - description: SDMA3 root clock used for accessing registers + clock-names: + minItems: 3 items: - const: ipg - const: ocram - const: core + - const: esai0_core + - const: esai0_extal + - const: esai0_fsys + - const: esai0_spba + - const: sai1_bus + - const: sai1_mclk0 + - const: sai1_mclk1 + - const: sai1_mclk2 + - const: sai1_mclk3 + - const: sai3_bus + - const: sai3_mclk0 + - const: sai3_mclk1 + - const: sai3_mclk2 + - const: sai3_mclk3 + - const: smda3_root power-domains: description: