From patchwork Thu Sep 9 02:18:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1603BC433FE for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE8FF6113A for ; Thu, 9 Sep 2021 02:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245131AbhIICUS (ORCPT ); Wed, 8 Sep 2021 22:20:18 -0400 Received: from mga04.intel.com ([192.55.52.120]:63723 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236189AbhIICUQ (ORCPT ); Wed, 8 Sep 2021 22:20:16 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793846" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793846" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:54 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916521" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:53 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 1/6] fpga: image-load: fpga image load class driver Date: Wed, 8 Sep 2021 19:18:41 -0700 Message-Id: <20210909021846.681121-2-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The FPGA Image Load class driver provides an API to transfer update files to an FPGA device. Image files are self-describing. They could contain FPGA images, BMC images, Root Entry Hashes, or other device specific files. It is up to the device driver and the target device to authenticate and disposition the file data. Signed-off-by: Russ Weight --- v15: - Compare to previous patch: [PATCH v14 1/6] fpga: sec-mgr: fpga security manager class driver - Changed file, symbol, and config names to reflect the new driver name - Rewrote documentation. The documentation will be added to in later patches. - Removed signed-off/reviewed-by tags v14: - Updated copyright to 2021 - Removed the name sysfs entry - Removed MAINTAINERS reference to Documentation/ABI/testing/sysfs-class-fpga-sec-mgr - Use xa_alloc() instead of ida_simple_get() - Rename dev to parent for parent devices - Remove fpga_sec_mgr_create(), devm_fpga_sec_mgr_create(), and fpga_sec_mgr_free() functions and update the fpga_sec_mgr_register() function to both create and register a new security manager. - Populate the fpga_sec_mgr_dev_release() function. v13: - No change v12: - Updated Date and KernelVersion fields in ABI documentation v11: - No change v10: - Rebased to 5.12-rc2 next - Updated Date and KernelVersion in ABI documentation v9: - Updated Date and KernelVersion in ABI documentation v8: - Fixed grammatical error in Documentation/fpga/fpga-sec-mgr.rst v7: - Changed Date in documentation file to December 2020 v6: - Removed sysfs support and documentation for the display of the flash count, root entry hashes, and code-signing-key cancelation vectors. v5: - Added the devm_fpga_sec_mgr_unregister() function, following recent changes to the fpga_manager() implementation. - Changed some *_show() functions to use sysfs_emit() instead of sprintf( v4: - Changed from "Intel FPGA Security Manager" to FPGA Security Manager" and removed unnecessary references to "Intel". - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ v3: - Modified sysfs handler check in check_sysfs_handler() to make it more readable. v2: - Bumped documentation dates and versions - Added Documentation/fpga/ifpga-sec-mgr.rst - Removed references to bmc_flash_count & smbus_flash_count (not supported) - Split ifpga_sec_mgr_register() into create() and register() functions - Added devm_ifpga_sec_mgr_create() - Removed typedefs for imgr ops --- --- Documentation/fpga/fpga-image-load.rst | 10 ++ Documentation/fpga/index.rst | 1 + MAINTAINERS | 8 ++ drivers/fpga/Kconfig | 10 ++ drivers/fpga/Makefile | 3 + drivers/fpga/fpga-image-load.c | 124 +++++++++++++++++++++++++ include/linux/fpga/fpga-image-load.h | 35 +++++++ 7 files changed, 191 insertions(+) create mode 100644 Documentation/fpga/fpga-image-load.rst create mode 100644 drivers/fpga/fpga-image-load.c create mode 100644 include/linux/fpga/fpga-image-load.h diff --git a/Documentation/fpga/fpga-image-load.rst b/Documentation/fpga/fpga-image-load.rst new file mode 100644 index 000000000000..a6e53ac66026 --- /dev/null +++ b/Documentation/fpga/fpga-image-load.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================ +FPGA Image Load Class Driver +============================ + +The FPGA Image Load class driver provides a common API for user-space +tools to manage image uploads to FPGA devices. Device drivers that +instantiate the FPGA Image Load class driver will interact with the +target device to transfer and authenticate the image data. diff --git a/Documentation/fpga/index.rst b/Documentation/fpga/index.rst index f80f95667ca2..85d25fb22c08 100644 --- a/Documentation/fpga/index.rst +++ b/Documentation/fpga/index.rst @@ -8,6 +8,7 @@ fpga :maxdepth: 1 dfl + fpga-image-load .. only:: subproject and html diff --git a/MAINTAINERS b/MAINTAINERS index 6c63415d2ac2..4e7f48fa7e5c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7358,6 +7358,14 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +FPGA SECURITY MANAGER DRIVERS +M: Russ Weight +L: linux-fpga@vger.kernel.org +S: Maintained +F: Documentation/fpga/fpga-image-load.rst +F: drivers/fpga/fpga-image-load.c +F: include/linux/fpga/fpga-image-load.h + FPU EMULATOR M: Bill Metzenthen S: Maintained diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 991b3f361ec9..c12a14e62fff 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -243,4 +243,14 @@ config FPGA_MGR_VERSAL_FPGA configure the programmable logic(PL). To compile this as a module, choose M here. + +config FPGA_IMAGE_LOAD + tristate "FPGA Image Load Driver" + help + The FPGA Image Load class driver presents a common user API for + uploading an image file to an FPGA device. The image file is + expected to be self-describing. It is up to the device driver + and/or the device itself to authenticate and disposition the + image data. + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 0bff783d1b61..adf228ee4f5e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -22,6 +22,9 @@ obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +# FPGA Image Load Framework +obj-$(CONFIG_FPGA_IMAGE_LOAD) += fpga-image-load.o + # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c new file mode 100644 index 000000000000..7d75bbcff541 --- /dev/null +++ b/drivers/fpga/fpga-image-load.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FPGA Image Load Class Driver + * + * Copyright (C) 2019-2021 Intel Corporation, Inc. + */ + +#include +#include +#include +#include + +#define IMAGE_LOAD_XA_LIMIT XA_LIMIT(0, INT_MAX) +static DEFINE_XARRAY_ALLOC(fpga_image_load_xa); + +static struct class *fpga_image_load_class; + +#define to_image_load(d) container_of(d, struct fpga_image_load, dev) + +/** + * fpga_image_load_register - create and register an FPGA Image Load Device + * + * @parent: fpga image load device from pdev + * @lops: pointer to a structure of image load callback functions + * @priv: fpga image load private data + * + * Returns a struct fpga_image_load pointer on success, or ERR_PTR() on + * error. The caller of this function is responsible for calling + * fpga_image_load_unregister(). + */ +struct fpga_image_load * +fpga_image_load_register(struct device *parent, + const struct fpga_image_load_ops *lops, void *priv) +{ + struct fpga_image_load *imgld; + int id, ret; + + imgld = kzalloc(sizeof(*imgld), GFP_KERNEL); + if (!imgld) + return NULL; + + ret = xa_alloc(&fpga_image_load_xa, &imgld->dev.id, imgld, IMAGE_LOAD_XA_LIMIT, + GFP_KERNEL); + if (ret) + goto error_kfree; + + mutex_init(&imgld->lock); + + imgld->priv = priv; + imgld->lops = lops; + + imgld->dev.class = fpga_image_load_class; + imgld->dev.parent = parent; + + ret = dev_set_name(&imgld->dev, "fpga_image%d", id); + if (ret) { + dev_err(parent, "Failed to set device name: fpga_image%d\n", id); + goto error_device; + } + + ret = device_register(&imgld->dev); + if (ret) { + put_device(&imgld->dev); + return ERR_PTR(ret); + } + + return imgld; + +error_device: + xa_erase(&fpga_image_load_xa, imgld->dev.id); + +error_kfree: + kfree(imgld); + + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(fpga_image_load_register); + +/** + * fpga_image_load_unregister - unregister an FPGA image load device + * + * @imgld: pointer to struct fpga_image_load + * + * This function is intended for use in an FPGA Image Load driver's + * remove() function. + */ +void fpga_image_load_unregister(struct fpga_image_load *imgld) +{ + device_unregister(&imgld->dev); +} +EXPORT_SYMBOL_GPL(fpga_image_load_unregister); + +static void fpga_image_load_dev_release(struct device *dev) +{ + struct fpga_image_load *imgld = to_image_load(dev); + + xa_erase(&fpga_image_load_xa, imgld->dev.id); + kfree(imgld); +} + +static int __init fpga_image_load_class_init(void) +{ + pr_info("FPGA Image Load Driver\n"); + + fpga_image_load_class = class_create(THIS_MODULE, "fpga_image_load"); + if (IS_ERR(fpga_image_load_class)) + return PTR_ERR(fpga_image_load_class); + + fpga_image_load_class->dev_release = fpga_image_load_dev_release; + + return 0; +} + +static void __exit fpga_image_load_class_exit(void) +{ + class_destroy(fpga_image_load_class); + WARN_ON(!xa_empty(&fpga_image_load_xa)); +} + +MODULE_DESCRIPTION("FPGA Image Load Driver"); +MODULE_LICENSE("GPL v2"); + +subsys_initcall(fpga_image_load_class_init); +module_exit(fpga_image_load_class_exit) diff --git a/include/linux/fpga/fpga-image-load.h b/include/linux/fpga/fpga-image-load.h new file mode 100644 index 000000000000..a9cef9e1056b --- /dev/null +++ b/include/linux/fpga/fpga-image-load.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Header file for FPGA Image Load Driver + * + * Copyright (C) 2019-2021 Intel Corporation, Inc. + */ +#ifndef _LINUX_FPGA_IMAGE_LOAD_H +#define _LINUX_FPGA_IMAGE_LOAD_H + +#include +#include +#include + +struct fpga_image_load; + +/** + * struct fpga_image_load_ops - device specific operations + */ +struct fpga_image_load_ops { +}; + +struct fpga_image_load { + struct device dev; + const struct fpga_image_load_ops *lops; + struct mutex lock; /* protect data structure contents */ + void *priv; +}; + +struct fpga_image_load * +fpga_image_load_register(struct device *dev, + const struct fpga_image_load_ops *lops, void *priv); + +void fpga_image_load_unregister(struct fpga_image_load *imgld); + +#endif From patchwork Thu Sep 9 02:18:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01556C433EF for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D74DA61139 for ; Thu, 9 Sep 2021 02:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234374AbhIICUS (ORCPT ); Wed, 8 Sep 2021 22:20:18 -0400 Received: from mga04.intel.com ([192.55.52.120]:63720 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234720AbhIICUQ (ORCPT ); Wed, 8 Sep 2021 22:20:16 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793848" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793848" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:54 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916527" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:54 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 2/6] fpga: image-load: enable image loads Date: Wed, 8 Sep 2021 19:18:42 -0700 Message-Id: <20210909021846.681121-3-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the FPGA Image Load class driver to include IOCTL support (FPGA_IMAGE_LOAD_WRITE) for initiating an upload of an image to a device. The IOCTL will return immediately, and the update will begin in the context of a kernel worker thread. Signed-off-by: Russ Weight --- v15: - Compare to previous patch: [PATCH v14 2/6] fpga: sec-mgr: enable secure updates - Changed file, symbol, and config names to reflect the new driver name - Removed update/filename sysfs file and added the FPGA_IMAGE_LOAD_WRITE IOCTL for writing the image data to the FPGA card. The driver no longer uses the request_firmware framework. - Fixed some error return values in fpga_image_load_register() - Removed signed-off/reviewed-by tags v14: - Added MAINTAINERS reference for Documentation/ABI/testing/sysfs-class-fpga-sec-mgr - Updated ABI documentation date and kernel version - Updated copyright to 2021 v13: - Change "if (count == 0 || " to "if (!count || " - Improve error message: "Attempt to register without all required ops\n" v12: - Updated Date and KernelVersion fields in ABI documentation - Removed size parameter from write_blk() op - it is now up to the lower-level driver to determine the appropriate size and to update smgr->remaining_size accordingly. v11: - Fixed a spelling error in a comment - Initialize smgr->err_code and smgr->progress explicitly in fpga_sec_mgr_create() instead of accepting the default 0 value. v10: - Rebased to 5.12-rc2 next - Updated Date and KernelVersion in ABI documentation v9: - Updated Date and KernelVersion in ABI documentation v8: - No change v7: - Changed Date in documentation file to December 2020 - Changed filename_store() to use kmemdup_nul() instead of kstrndup() and changed the count to not assume a line-return. v6: - Changed "security update" to "secure update" in commit message v5: - When checking the return values for functions of type enum fpga_sec_err err_code, test for FPGA_SEC_ERR_NONE instead of 0 v4: - Changed from "Intel FPGA Security Manager" to FPGA Security Manager" and removed unnecessary references to "Intel". - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ v3: - Removed unnecessary "goto done" - Added a comment to explain imgr->driver_unload in ifpga_sec_mgr_unregister() v2: - Bumped documentation date and version - Removed explicit value assignments in enums - Other minor code cleanup per review comments --- Documentation/fpga/fpga-image-load.rst | 21 +++ MAINTAINERS | 1 + drivers/fpga/fpga-image-load.c | 224 ++++++++++++++++++++++++- include/linux/fpga/fpga-image-load.h | 29 ++++ include/uapi/linux/fpga-image-load.h | 58 +++++++ 5 files changed, 329 insertions(+), 4 deletions(-) create mode 100644 include/uapi/linux/fpga-image-load.h diff --git a/Documentation/fpga/fpga-image-load.rst b/Documentation/fpga/fpga-image-load.rst index a6e53ac66026..2ca8d2f0212d 100644 --- a/Documentation/fpga/fpga-image-load.rst +++ b/Documentation/fpga/fpga-image-load.rst @@ -8,3 +8,24 @@ The FPGA Image Load class driver provides a common API for user-space tools to manage image uploads to FPGA devices. Device drivers that instantiate the FPGA Image Load class driver will interact with the target device to transfer and authenticate the image data. + +User API +======== + +open +---- + +An FPGA Image Load device is opened exclusively to control an image load. +Image loads are processed by a kernel worker thread. A user may choose +close the device while the upload continues. + +ioctl +----- + +FPGA_IMAGE_LOAD_WRITE: + +Start an image load with the provided image buffer. This IOCTL returns +immediately after starting a kernel worker thread to process the image load +which could take as long a 40 minutes depending on the actual device being +updated. This is an exclusive operation; an attempt to start concurrent image +load for the same device will fail with EBUSY. diff --git a/MAINTAINERS b/MAINTAINERS index 4e7f48fa7e5c..637bc003ca81 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7365,6 +7365,7 @@ S: Maintained F: Documentation/fpga/fpga-image-load.rst F: drivers/fpga/fpga-image-load.c F: include/linux/fpga/fpga-image-load.h +F: include/uapi/linux/fpga-image-load.h FPU EMULATOR M: Bill Metzenthen diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c index 7d75bbcff541..f5ccfa9dd977 100644 --- a/drivers/fpga/fpga-image-load.c +++ b/drivers/fpga/fpga-image-load.c @@ -5,18 +5,181 @@ * Copyright (C) 2019-2021 Intel Corporation, Inc. */ +#include #include +#include +#include #include #include +#include #include #define IMAGE_LOAD_XA_LIMIT XA_LIMIT(0, INT_MAX) static DEFINE_XARRAY_ALLOC(fpga_image_load_xa); static struct class *fpga_image_load_class; +static dev_t fpga_image_devt; #define to_image_load(d) container_of(d, struct fpga_image_load, dev) +static void fpga_image_dev_error(struct fpga_image_load *imgld, + enum fpga_image_err err_code) +{ + imgld->err_code = err_code; + imgld->lops->cancel(imgld); +} + +static void fpga_image_prog_complete(struct fpga_image_load *imgld) +{ + mutex_lock(&imgld->lock); + imgld->progress = FPGA_IMAGE_PROG_IDLE; + complete_all(&imgld->update_done); + mutex_unlock(&imgld->lock); +} + +static void fpga_image_do_load(struct work_struct *work) +{ + struct fpga_image_load *imgld; + enum fpga_image_err ret; + u32 size, offset = 0; + + imgld = container_of(work, struct fpga_image_load, work); + size = imgld->remaining_size; + + get_device(&imgld->dev); + if (!try_module_get(imgld->dev.parent->driver->owner)) { + imgld->err_code = FPGA_IMAGE_ERR_BUSY; + goto idle_exit; + } + + imgld->progress = FPGA_IMAGE_PROG_PREPARING; + ret = imgld->lops->prepare(imgld); + if (ret != FPGA_IMAGE_ERR_NONE) { + fpga_image_dev_error(imgld, ret); + goto modput_exit; + } + + imgld->progress = FPGA_IMAGE_PROG_WRITING; + while (imgld->remaining_size) { + ret = imgld->lops->write_blk(imgld, offset); + if (ret != FPGA_IMAGE_ERR_NONE) { + fpga_image_dev_error(imgld, ret); + goto done; + } + + offset = size - imgld->remaining_size; + } + + imgld->progress = FPGA_IMAGE_PROG_PROGRAMMING; + ret = imgld->lops->poll_complete(imgld); + if (ret != FPGA_IMAGE_ERR_NONE) + fpga_image_dev_error(imgld, ret); + +done: + if (imgld->lops->cleanup) + imgld->lops->cleanup(imgld); + +modput_exit: + module_put(imgld->dev.parent->driver->owner); + +idle_exit: + /* + * Note: imgld->remaining_size is left unmodified here to provide + * additional information on errors. It will be reinitialized when + * the next image load begins. + */ + vfree(imgld->data); + imgld->data = NULL; + put_device(&imgld->dev); + fpga_image_prog_complete(imgld); +} + +static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, + unsigned long arg) +{ + struct fpga_image_write wb; + unsigned long minsz; + u8 *buf; + + if (imgld->driver_unload || imgld->progress != FPGA_IMAGE_PROG_IDLE) + return -EBUSY; + + minsz = offsetofend(struct fpga_image_write, buf); + if (copy_from_user(&wb, (void __user *)arg, minsz)) + return -EFAULT; + + if (wb.flags) + return -EINVAL; + + /* Enforce 32-bit alignment on the write data */ + if (wb.size & 0x3) + return -EINVAL; + + buf = vzalloc(wb.size); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, u64_to_user_ptr(wb.buf), wb.size)) { + vfree(buf); + return -EFAULT; + } + + imgld->data = buf; + imgld->remaining_size = wb.size; + imgld->err_code = FPGA_IMAGE_ERR_NONE; + imgld->progress = FPGA_IMAGE_PROG_STARTING; + reinit_completion(&imgld->update_done); + schedule_work(&imgld->work); + + return 0; +} + +static long fpga_image_load_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct fpga_image_load *imgld = filp->private_data; + int ret = -ENOTTY; + + switch (cmd) { + case FPGA_IMAGE_LOAD_WRITE: + mutex_lock(&imgld->lock); + ret = fpga_image_load_ioctl_write(imgld, arg); + mutex_unlock(&imgld->lock); + break; + } + + return ret; +} + +static int fpga_image_load_open(struct inode *inode, struct file *filp) +{ + struct fpga_image_load *imgld = container_of(inode->i_cdev, + struct fpga_image_load, cdev); + + if (test_and_set_bit(0, &imgld->opened)) + return -EBUSY; + + filp->private_data = imgld; + + return 0; +} + +static int fpga_image_load_release(struct inode *inode, struct file *filp) +{ + struct fpga_image_load *imgld = filp->private_data; + + clear_bit(0, &imgld->opened); + + return 0; +} + +static const struct file_operations fpga_image_load_fops = { + .owner = THIS_MODULE, + .open = fpga_image_load_open, + .release = fpga_image_load_release, + .unlocked_ioctl = fpga_image_load_ioctl, +}; + /** * fpga_image_load_register - create and register an FPGA Image Load Device * @@ -33,11 +196,17 @@ fpga_image_load_register(struct device *parent, const struct fpga_image_load_ops *lops, void *priv) { struct fpga_image_load *imgld; - int id, ret; + int ret; + + if (!lops || !lops->cancel || !lops->prepare || + !lops->write_blk || !lops->poll_complete) { + dev_err(parent, "Attempt to register without all required ops\n"); + return ERR_PTR(-ENOMEM); + } imgld = kzalloc(sizeof(*imgld), GFP_KERNEL); if (!imgld) - return NULL; + return ERR_PTR(-ENOMEM); ret = xa_alloc(&fpga_image_load_xa, &imgld->dev.id, imgld, IMAGE_LOAD_XA_LIMIT, GFP_KERNEL); @@ -48,13 +217,19 @@ fpga_image_load_register(struct device *parent, imgld->priv = priv; imgld->lops = lops; + imgld->err_code = FPGA_IMAGE_ERR_NONE; + imgld->progress = FPGA_IMAGE_PROG_IDLE; + init_completion(&imgld->update_done); + INIT_WORK(&imgld->work, fpga_image_do_load); imgld->dev.class = fpga_image_load_class; imgld->dev.parent = parent; + imgld->dev.devt = MKDEV(MAJOR(fpga_image_devt), imgld->dev.id); - ret = dev_set_name(&imgld->dev, "fpga_image%d", id); + ret = dev_set_name(&imgld->dev, "fpga_image%d", imgld->dev.id); if (ret) { - dev_err(parent, "Failed to set device name: fpga_image%d\n", id); + dev_err(parent, "Failed to set device name: fpga_image%d\n", + imgld->dev.id); goto error_device; } @@ -64,6 +239,16 @@ fpga_image_load_register(struct device *parent, return ERR_PTR(ret); } + cdev_init(&imgld->cdev, &fpga_image_load_fops); + imgld->cdev.owner = parent->driver->owner; + imgld->cdev.kobj.parent = &imgld->dev.kobj; + + ret = cdev_add(&imgld->cdev, imgld->dev.devt, 1); + if (ret) { + put_device(&imgld->dev); + return ERR_PTR(ret); + } + return imgld; error_device: @@ -83,9 +268,29 @@ EXPORT_SYMBOL_GPL(fpga_image_load_register); * * This function is intended for use in an FPGA Image Load driver's * remove() function. + * + * For some devices, once authentication of the uploaded image has begun, + * the hardware cannot be signaled to stop, and the driver will not exit + * until the hardware signals completion. This could be 30+ minutes of + * waiting. The driver_unload flag enables a force-unload of the driver + * (e.g. modprobe -r) by signaling the parent driver to exit even if the + * hardware update is incomplete. The driver_unload flag also prevents + * new updates from starting once the unregister process has begun. */ void fpga_image_load_unregister(struct fpga_image_load *imgld) { + mutex_lock(&imgld->lock); + imgld->driver_unload = true; + if (imgld->progress == FPGA_IMAGE_PROG_IDLE) { + mutex_unlock(&imgld->lock); + goto unregister; + } + + mutex_unlock(&imgld->lock); + wait_for_completion(&imgld->update_done); + +unregister: + cdev_del(&imgld->cdev); device_unregister(&imgld->dev); } EXPORT_SYMBOL_GPL(fpga_image_load_unregister); @@ -100,19 +305,30 @@ static void fpga_image_load_dev_release(struct device *dev) static int __init fpga_image_load_class_init(void) { + int ret; pr_info("FPGA Image Load Driver\n"); fpga_image_load_class = class_create(THIS_MODULE, "fpga_image_load"); if (IS_ERR(fpga_image_load_class)) return PTR_ERR(fpga_image_load_class); + ret = alloc_chrdev_region(&fpga_image_devt, 0, MINORMASK, + "fpga_image_load"); + if (ret) + goto exit_destroy_class; + fpga_image_load_class->dev_release = fpga_image_load_dev_release; return 0; + +exit_destroy_class: + class_destroy(fpga_image_load_class); + return ret; } static void __exit fpga_image_load_class_exit(void) { + unregister_chrdev_region(fpga_image_devt, MINORMASK); class_destroy(fpga_image_load_class); WARN_ON(!xa_empty(&fpga_image_load_xa)); } diff --git a/include/linux/fpga/fpga-image-load.h b/include/linux/fpga/fpga-image-load.h index a9cef9e1056b..b3d790e5d943 100644 --- a/include/linux/fpga/fpga-image-load.h +++ b/include/linux/fpga/fpga-image-load.h @@ -7,22 +7,51 @@ #ifndef _LINUX_FPGA_IMAGE_LOAD_H #define _LINUX_FPGA_IMAGE_LOAD_H +#include +#include #include #include #include +#include struct fpga_image_load; /** * struct fpga_image_load_ops - device specific operations + * @prepare: Required: Prepare secure update + * @write_blk: Required: Write a block of data + * @poll_complete: Required: Check for the completion of the + * HW authentication/programming process. This + * function should check for imgld->driver_unload + * and abort with FPGA_IMAGE_ERR_CANCELED when true. + * @cancel: Required: Signal HW to cancel update + * @cleanup: Optional: Complements the prepare() + * function and is called at the completion + * of the update, whether success or failure, + * if the prepare function succeeded. */ struct fpga_image_load_ops { + enum fpga_image_err (*prepare)(struct fpga_image_load *imgld); + enum fpga_image_err (*write_blk)(struct fpga_image_load *imgld, u32 offset); + enum fpga_image_err (*poll_complete)(struct fpga_image_load *imgld); + enum fpga_image_err (*cancel)(struct fpga_image_load *imgld); + void (*cleanup)(struct fpga_image_load *imgld); }; struct fpga_image_load { struct device dev; + struct cdev cdev; const struct fpga_image_load_ops *lops; struct mutex lock; /* protect data structure contents */ + unsigned long opened; + struct work_struct work; + struct completion update_done; + const u8 *data; /* pointer to update data */ + u32 remaining_size; /* size remaining to transfer */ + enum fpga_image_prog progress; + enum fpga_image_prog err_progress; /* progress at time of failure */ + enum fpga_image_err err_code; /* image load error code */ + bool driver_unload; void *priv; }; diff --git a/include/uapi/linux/fpga-image-load.h b/include/uapi/linux/fpga-image-load.h new file mode 100644 index 000000000000..4146a0a9e408 --- /dev/null +++ b/include/uapi/linux/fpga-image-load.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Header File for FPGA Image Load User API + * + * Copyright (C) 2019-2021 Intel Corporation, Inc. + * + */ + +#ifndef _UAPI_LINUX_FPGA_IMAGE_LOAD_H +#define _UAPI_LINUX_FPGA_IMAGE_LOAD_H + +#include +#include + +#define FPGA_IMAGE_LOAD_MAGIC 0xB9 + +/* Image load progress codes */ +enum fpga_image_prog { + FPGA_IMAGE_PROG_IDLE, + FPGA_IMAGE_PROG_STARTING, + FPGA_IMAGE_PROG_PREPARING, + FPGA_IMAGE_PROG_WRITING, + FPGA_IMAGE_PROG_PROGRAMMING, + FPGA_IMAGE_PROG_MAX +}; + +/* Image error progress codes */ +enum fpga_image_err { + FPGA_IMAGE_ERR_NONE, + FPGA_IMAGE_ERR_HW_ERROR, + FPGA_IMAGE_ERR_TIMEOUT, + FPGA_IMAGE_ERR_CANCELED, + FPGA_IMAGE_ERR_BUSY, + FPGA_IMAGE_ERR_INVALID_SIZE, + FPGA_IMAGE_ERR_RW_ERROR, + FPGA_IMAGE_ERR_WEAROUT, + FPGA_IMAGE_ERR_MAX +}; + +#define FPGA_IMAGE_LOAD_WRITE _IOW(FPGA_IMAGE_LOAD_MAGIC, 0, struct fpga_image_write) + +/** + * FPGA_IMAGE_LOAD_WRITE - _IOW(FPGA_IMAGE_LOAD_MAGIC, 0, + * struct fpga_image_write) + * + * Upload a data buffer to the target device. The user must provide the + * data buffer, size, and an eventfd file descriptor. + * + * Return: 0 on success, -errno on failure. + */ +struct fpga_image_write { + /* Input */ + __u32 flags; /* Zero for now */ + __u32 size; /* Data size (in bytes) to be written */ + __u64 buf; /* User space address of source data */ +}; + +#endif /* _UAPI_LINUX_FPGA_IMAGE_LOAD_H */ From patchwork Thu Sep 9 02:18:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54CD4C4321E for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42DED611C7 for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346657AbhIICUT (ORCPT ); Wed, 8 Sep 2021 22:20:19 -0400 Received: from mga04.intel.com ([192.55.52.120]:63717 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236112AbhIICUQ (ORCPT ); Wed, 8 Sep 2021 22:20:16 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793849" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793849" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:55 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916533" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:54 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 3/6] fpga: image-load: signal eventfd when complete Date: Wed, 8 Sep 2021 19:18:43 -0700 Message-Id: <20210909021846.681121-4-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Amend the FPGA_IMAGE_LOAD_WRITE IOCTL implementation to include and eventfd file descriptor as a parameter. The eventfd will be triggered when the image upload completes. Signed-off-by: Russ Weight --- v15: - This patch is new to the patch-set, and adds an eventfd to the FPGA_IMAGE_LOAD_WRITE IOCTL. The eventfd is signalled upon completion of an update. --- Documentation/fpga/fpga-image-load.rst | 4 +++- drivers/fpga/fpga-image-load.c | 23 ++++++++++++++++++++--- include/linux/fpga/fpga-image-load.h | 2 ++ include/uapi/linux/fpga-image-load.h | 1 + 4 files changed, 26 insertions(+), 4 deletions(-) diff --git a/Documentation/fpga/fpga-image-load.rst b/Documentation/fpga/fpga-image-load.rst index 2ca8d2f0212d..739d735592a5 100644 --- a/Documentation/fpga/fpga-image-load.rst +++ b/Documentation/fpga/fpga-image-load.rst @@ -28,4 +28,6 @@ Start an image load with the provided image buffer. This IOCTL returns immediately after starting a kernel worker thread to process the image load which could take as long a 40 minutes depending on the actual device being updated. This is an exclusive operation; an attempt to start concurrent image -load for the same device will fail with EBUSY. +load for the same device will fail with EBUSY. An eventfd file descriptor +parameter is provided to this IOCTL, and it will be signalled at the +completion of the image load. diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c index f5ccfa9dd977..b784456765b0 100644 --- a/drivers/fpga/fpga-image-load.c +++ b/drivers/fpga/fpga-image-load.c @@ -33,6 +33,7 @@ static void fpga_image_prog_complete(struct fpga_image_load *imgld) { mutex_lock(&imgld->lock); imgld->progress = FPGA_IMAGE_PROG_IDLE; + eventfd_signal(imgld->finished, 1); complete_all(&imgld->update_done); mutex_unlock(&imgld->lock); } @@ -92,6 +93,8 @@ static void fpga_image_do_load(struct work_struct *work) imgld->data = NULL; put_device(&imgld->dev); fpga_image_prog_complete(imgld); + eventfd_ctx_put(imgld->finished); + imgld->finished = NULL; } static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, @@ -99,6 +102,7 @@ static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, { struct fpga_image_write wb; unsigned long minsz; + int ret; u8 *buf; if (imgld->driver_unload || imgld->progress != FPGA_IMAGE_PROG_IDLE) @@ -115,13 +119,23 @@ static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, if (wb.size & 0x3) return -EINVAL; + if (wb.evtfd < 0) + return -EINVAL; + buf = vzalloc(wb.size); if (!buf) return -ENOMEM; if (copy_from_user(buf, u64_to_user_ptr(wb.buf), wb.size)) { - vfree(buf); - return -EFAULT; + ret = -EFAULT; + goto exit_free; + } + + imgld->finished = eventfd_ctx_fdget(wb.evtfd); + if (IS_ERR(imgld->finished)) { + ret = PTR_ERR(imgld->finished); + imgld->finished = NULL; + goto exit_free; } imgld->data = buf; @@ -130,8 +144,11 @@ static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, imgld->progress = FPGA_IMAGE_PROG_STARTING; reinit_completion(&imgld->update_done); schedule_work(&imgld->work); - return 0; + +exit_free: + vfree(buf); + return ret; } static long fpga_image_load_ioctl(struct file *filp, unsigned int cmd, diff --git a/include/linux/fpga/fpga-image-load.h b/include/linux/fpga/fpga-image-load.h index b3d790e5d943..68f3105b51d2 100644 --- a/include/linux/fpga/fpga-image-load.h +++ b/include/linux/fpga/fpga-image-load.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,7 @@ struct fpga_image_load { enum fpga_image_prog err_progress; /* progress at time of failure */ enum fpga_image_err err_code; /* image load error code */ bool driver_unload; + struct eventfd_ctx *finished; void *priv; }; diff --git a/include/uapi/linux/fpga-image-load.h b/include/uapi/linux/fpga-image-load.h index 4146a0a9e408..a60da115adf5 100644 --- a/include/uapi/linux/fpga-image-load.h +++ b/include/uapi/linux/fpga-image-load.h @@ -52,6 +52,7 @@ struct fpga_image_write { /* Input */ __u32 flags; /* Zero for now */ __u32 size; /* Data size (in bytes) to be written */ + __s32 evtfd; /* File descriptor for completion signal */ __u64 buf; /* User space address of source data */ }; From patchwork Thu Sep 9 02:18:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8354C433F5 for ; Thu, 9 Sep 2021 02:19:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8A3F61139 for ; Thu, 9 Sep 2021 02:19:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236229AbhIICUP (ORCPT ); Wed, 8 Sep 2021 22:20:15 -0400 Received: from mga04.intel.com ([192.55.52.120]:63717 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234374AbhIICUM (ORCPT ); Wed, 8 Sep 2021 22:20:12 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793850" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793850" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:55 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916536" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:55 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 4/6] fpga: image-load: add status ioctl Date: Wed, 8 Sep 2021 19:18:44 -0700 Message-Id: <20210909021846.681121-5-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the FPGA Image Load class driver to include an FPGA_IMAGE_LOAD_STATUS IOCTL that can be used to monitor the progress of an ongoing image load. The status returned includes how much data remains to be transferred, the progress of the image load, and error information in the case of a failure. Signed-off-by: Russ Weight --- V15: - This patch is new to the patchset and provides an FPGA_IMAGE_LOAD_STATUS IOCTL to return the current values for: remaining_size, progress, err_progress, and err_code. - This patch has elements of the following three patches from the previous patch-set: [PATCH v14 3/6] fpga: sec-mgr: expose sec-mgr update status [PATCH v14 4/6] fpga: sec-mgr: expose sec-mgr update errors [PATCH v14 5/6] fpga: sec-mgr: expose sec-mgr update size - Changed file, symbol, and config names to reflect the new driver name - There are some minor changes to locking to enable this ioctl to return coherent data. --- Documentation/fpga/fpga-image-load.rst | 6 +++ drivers/fpga/fpga-image-load.c | 53 ++++++++++++++++++++++---- include/uapi/linux/fpga-image-load.h | 18 +++++++++ 3 files changed, 70 insertions(+), 7 deletions(-) diff --git a/Documentation/fpga/fpga-image-load.rst b/Documentation/fpga/fpga-image-load.rst index 739d735592a5..3d5eb51223e3 100644 --- a/Documentation/fpga/fpga-image-load.rst +++ b/Documentation/fpga/fpga-image-load.rst @@ -31,3 +31,9 @@ updated. This is an exclusive operation; an attempt to start concurrent image load for the same device will fail with EBUSY. An eventfd file descriptor parameter is provided to this IOCTL, and it will be signalled at the completion of the image load. + +FPGA_IMAGE_LOAD_STATUS: + +Collect status for an on-going image upload. The status returned includes +how much data remains to be transferred, the progress of the image load, +and error information in the case of a failure. diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c index b784456765b0..99a47b21c995 100644 --- a/drivers/fpga/fpga-image-load.c +++ b/drivers/fpga/fpga-image-load.c @@ -22,10 +22,27 @@ static dev_t fpga_image_devt; #define to_image_load(d) container_of(d, struct fpga_image_load, dev) -static void fpga_image_dev_error(struct fpga_image_load *imgld, +static void fpga_image_update_progress(struct fpga_image_load *imgld, + enum fpga_image_prog new_progress) +{ + mutex_lock(&imgld->lock); + imgld->progress = new_progress; + mutex_unlock(&imgld->lock); +} + +static void fpga_image_set_error(struct fpga_image_load *imgld, enum fpga_image_err err_code) { + mutex_lock(&imgld->lock); + imgld->err_progress = imgld->progress; imgld->err_code = err_code; + mutex_unlock(&imgld->lock); +} + +static void fpga_image_dev_error(struct fpga_image_load *imgld, + enum fpga_image_err err_code) +{ + fpga_image_set_error(imgld, err_code); imgld->lops->cancel(imgld); } @@ -49,18 +66,18 @@ static void fpga_image_do_load(struct work_struct *work) get_device(&imgld->dev); if (!try_module_get(imgld->dev.parent->driver->owner)) { - imgld->err_code = FPGA_IMAGE_ERR_BUSY; + fpga_image_set_error(imgld, FPGA_IMAGE_ERR_BUSY); goto idle_exit; } - imgld->progress = FPGA_IMAGE_PROG_PREPARING; + fpga_image_update_progress(imgld, FPGA_IMAGE_PROG_PREPARING); ret = imgld->lops->prepare(imgld); if (ret != FPGA_IMAGE_ERR_NONE) { fpga_image_dev_error(imgld, ret); goto modput_exit; } - imgld->progress = FPGA_IMAGE_PROG_WRITING; + fpga_image_update_progress(imgld, FPGA_IMAGE_PROG_WRITING); while (imgld->remaining_size) { ret = imgld->lops->write_blk(imgld, offset); if (ret != FPGA_IMAGE_ERR_NONE) { @@ -71,7 +88,7 @@ static void fpga_image_do_load(struct work_struct *work) offset = size - imgld->remaining_size; } - imgld->progress = FPGA_IMAGE_PROG_PROGRAMMING; + fpga_image_update_progress(imgld, FPGA_IMAGE_PROG_PROGRAMMING); ret = imgld->lops->poll_complete(imgld); if (ret != FPGA_IMAGE_ERR_NONE) fpga_image_dev_error(imgld, ret); @@ -151,20 +168,42 @@ static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, return ret; } +static int fpga_image_load_ioctl_status(struct fpga_image_load *imgld, + unsigned long arg) +{ + struct fpga_image_status status; + + memset(&status, 0, sizeof(status)); + status.progress = imgld->progress; + status.remaining_size = imgld->remaining_size; + status.err_progress = imgld->err_progress; + status.err_code = imgld->err_code; + + if (copy_to_user((void __user *)arg, &status, sizeof(status))) + return -EFAULT; + + return 0; +} + static long fpga_image_load_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct fpga_image_load *imgld = filp->private_data; int ret = -ENOTTY; + mutex_lock(&imgld->lock); + switch (cmd) { case FPGA_IMAGE_LOAD_WRITE: - mutex_lock(&imgld->lock); ret = fpga_image_load_ioctl_write(imgld, arg); - mutex_unlock(&imgld->lock); + break; + case FPGA_IMAGE_LOAD_STATUS: + ret = fpga_image_load_ioctl_status(imgld, arg); break; } + mutex_unlock(&imgld->lock); + return ret; } diff --git a/include/uapi/linux/fpga-image-load.h b/include/uapi/linux/fpga-image-load.h index a60da115adf5..6a995bcc0fb7 100644 --- a/include/uapi/linux/fpga-image-load.h +++ b/include/uapi/linux/fpga-image-load.h @@ -38,6 +38,7 @@ enum fpga_image_err { }; #define FPGA_IMAGE_LOAD_WRITE _IOW(FPGA_IMAGE_LOAD_MAGIC, 0, struct fpga_image_write) +#define FPGA_IMAGE_LOAD_STATUS _IOR(FPGA_IMAGE_LOAD_MAGIC, 1, struct fpga_image_status) /** * FPGA_IMAGE_LOAD_WRITE - _IOW(FPGA_IMAGE_LOAD_MAGIC, 0, @@ -56,4 +57,21 @@ struct fpga_image_write { __u64 buf; /* User space address of source data */ }; +/** + * FPGA_IMAGE_LOAD_STATUS - _IOR(FPGA_IMAGE_LOAD_MAGIC, 1, + * struct fpga_image_status) + * + * Request status information for an ongoing update. + * data buffer, size, and an eventfd file descriptor. + * + * Return: 0 on success, -errno on failure. + */ +struct fpga_image_status { + /* Output */ + __u32 remaining_size; /* size remaining to transfer */ + enum fpga_image_prog progress; /* current progress of image load */ + enum fpga_image_prog err_progress; /* progress at time of error */ + enum fpga_image_err err_code; /* error code */ +}; + #endif /* _UAPI_LINUX_FPGA_IMAGE_LOAD_H */ From patchwork Thu Sep 9 02:18:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6C9FC433FE for ; Thu, 9 Sep 2021 02:19:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 903EA61139 for ; Thu, 9 Sep 2021 02:19:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237372AbhIICUQ (ORCPT ); Wed, 8 Sep 2021 22:20:16 -0400 Received: from mga04.intel.com ([192.55.52.120]:63720 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233710AbhIICUO (ORCPT ); Wed, 8 Sep 2021 22:20:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793851" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793851" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:56 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916539" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:55 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 5/6] fpga: image-load: create status sysfs node Date: Wed, 8 Sep 2021 19:18:45 -0700 Message-Id: <20210909021846.681121-6-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the FPGA Image Load class driver to include a status sysfs node that can be viewed to determine from the command line if an image load is in progress. Status will be one of: idle, starting, preparing, writing, or programming. Signed-off-by: Russ Weight --- v15: - Compare to previous patch: [PATCH v14 3/6] fpga: sec-mgr: expose sec-mgr update status - Changed file, symbol, and config names to reflect the new driver name - Removed signed-off/reviewed-by tags v14: - Updated ABI documentation date and kernel version v13: - No change v12: - Updated Date and KernelVersion fields in ABI documentation - Changed syntax of sec_mgr_prog_str[] array definition from: "idle", /* FPGA_SEC_PROG_IDLE */ to: [FPGA_SEC_PROG_IDLE] = "idle", v11: - No change v10: - Rebased to 5.12-rc2 next - Updated Date and KernelVersion in ABI documentation v9: - Updated Date and KernelVersion in ABI documentation v8: - No change v7: - Changed Date in documentation file to December 2020 v6: - No change v5: - Use new function sysfs_emit() in the status_show() function v4: - Changed from "Intel FPGA Security Manager" to FPGA Security Manager" and removed unnecessary references to "Intel". - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ v3: - Use a local variable to read progress once in status_show() - Use dev_err to report invalid progress status v2: - Bumped documentation date and version - Changed progress state "read_file" to "reading" --- .../ABI/testing/sysfs-class-fpga-image-load | 7 ++++ MAINTAINERS | 1 + drivers/fpga/fpga-image-load.c | 33 +++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-image-load diff --git a/Documentation/ABI/testing/sysfs-class-fpga-image-load b/Documentation/ABI/testing/sysfs-class-fpga-image-load new file mode 100644 index 000000000000..6c04a49f01cc --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-fpga-image-load @@ -0,0 +1,7 @@ +What: /sys/class/fpga_image_load/fpga_imageX/status +Date: Aug 2021 +KernelVersion: 5.15 +Contact: Russ Weight +Description: Read-only. Returns a string describing the current status + of an FPGA image upload. The string will be one of the + following: idle, starting, preparing, writing, programming. diff --git a/MAINTAINERS b/MAINTAINERS index 637bc003ca81..e3fbc1bde9bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7362,6 +7362,7 @@ FPGA SECURITY MANAGER DRIVERS M: Russ Weight L: linux-fpga@vger.kernel.org S: Maintained +F: Documentation/ABI/testing/sysfs-class-fpga-image-load F: Documentation/fpga/fpga-image-load.rst F: drivers/fpga/fpga-image-load.c F: include/linux/fpga/fpga-image-load.h diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c index 99a47b21c995..6ec0a39f07b3 100644 --- a/drivers/fpga/fpga-image-load.c +++ b/drivers/fpga/fpga-image-load.c @@ -236,6 +236,38 @@ static const struct file_operations fpga_image_load_fops = { .unlocked_ioctl = fpga_image_load_ioctl, }; +static const char * const image_load_prog_str[] = { + [FPGA_IMAGE_PROG_IDLE] = "idle", + [FPGA_IMAGE_PROG_STARTING] = "starting", + [FPGA_IMAGE_PROG_PREPARING] = "preparing", + [FPGA_IMAGE_PROG_WRITING] = "writing", + [FPGA_IMAGE_PROG_PROGRAMMING] = "programming" +}; + +static ssize_t +status_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fpga_image_load *imgld = to_image_load(dev); + const char *status = "unknown-status"; + enum fpga_image_prog progress; + + progress = imgld->progress; + if (progress < FPGA_IMAGE_PROG_MAX) + status = image_load_prog_str[progress]; + else + dev_err(dev, "Invalid status during secure update: %d\n", + progress); + + return sysfs_emit(buf, "%s\n", status); +} +static DEVICE_ATTR_RO(status); + +static struct attribute *fpga_image_load_attrs[] = { + &dev_attr_status.attr, + NULL, +}; +ATTRIBUTE_GROUPS(fpga_image_load); + /** * fpga_image_load_register - create and register an FPGA Image Load Device * @@ -373,6 +405,7 @@ static int __init fpga_image_load_class_init(void) if (ret) goto exit_destroy_class; + fpga_image_load_class->dev_groups = fpga_image_load_groups; fpga_image_load_class->dev_release = fpga_image_load_dev_release; return 0; From patchwork Thu Sep 9 02:18:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12482313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF5FC4332F for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0EB2B61186 for ; Thu, 9 Sep 2021 02:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244290AbhIICUT (ORCPT ); Wed, 8 Sep 2021 22:20:19 -0400 Received: from mga04.intel.com ([192.55.52.120]:63720 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236166AbhIICUQ (ORCPT ); Wed, 8 Sep 2021 22:20:16 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10101"; a="218793852" X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="218793852" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:56 -0700 X-IronPort-AV: E=Sophos;i="5.85,279,1624345200"; d="scan'208";a="503916542" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.194.237]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 19:18:56 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v15 6/6] fpga: image-load: enable cancel of image upload Date: Wed, 8 Sep 2021 19:18:46 -0700 Message-Id: <20210909021846.681121-7-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210909021846.681121-1-russell.h.weight@intel.com> References: <20210909021846.681121-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the FPGA Image Load class driver to include a cancel IOCTL that can be used to request that an image upload be canceled. The IOCTL may return EBUSY if it cannot be canceled by software or ENODEV if there is no update in progress. Signed-off-by: Russ Weight --- v15: - Compare to previous patch: [PATCH v14 6/6] fpga: sec-mgr: enable cancel of secure update - Changed file, symbol, and config names to reflect the new driver name - Cancel is now initiated by IOCT instead of sysfs - Removed signed-off/reviewed-by tags v14: - Updated ABI documentation date and kernel version v13: - No change v12: - Updated Date and KernelVersion fields in ABI documentation v11: - No change v10: - Rebased to 5.12-rc2 next - Updated Date and KernelVersion in ABI documentation v9: - Updated Date and KernelVersion in ABI documentation v8: - No change v7: - Changed Date in documentation file to December 2020 v6: - No change v5: - No change v4: - Changed from "Intel FPGA Security Manager" to FPGA Security Manager" and removed unnecessary references to "Intel". - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ v3: - No change v2: - Bumped documentation date and version - Minor code cleanup per review comments --- --- Documentation/fpga/fpga-image-load.rst | 6 ++++ drivers/fpga/fpga-image-load.c | 45 +++++++++++++++++++++++--- include/linux/fpga/fpga-image-load.h | 1 + include/uapi/linux/fpga-image-load.h | 1 + 4 files changed, 49 insertions(+), 4 deletions(-) diff --git a/Documentation/fpga/fpga-image-load.rst b/Documentation/fpga/fpga-image-load.rst index 3d5eb51223e3..763e7833a6ea 100644 --- a/Documentation/fpga/fpga-image-load.rst +++ b/Documentation/fpga/fpga-image-load.rst @@ -37,3 +37,9 @@ FPGA_IMAGE_LOAD_STATUS: Collect status for an on-going image upload. The status returned includes how much data remains to be transferred, the progress of the image load, and error information in the case of a failure. + +FPGA_IMAGE_LOAD_CANCEL: + +Request that a on-going image upload be cancelled. This IOCTL may return +EBUSY if it cannot be cancelled by software or ENODEV if there is no update +in progress. diff --git a/drivers/fpga/fpga-image-load.c b/drivers/fpga/fpga-image-load.c index 6ec0a39f07b3..c32e4b1ea35a 100644 --- a/drivers/fpga/fpga-image-load.c +++ b/drivers/fpga/fpga-image-load.c @@ -46,6 +46,24 @@ static void fpga_image_dev_error(struct fpga_image_load *imgld, imgld->lops->cancel(imgld); } +static int fpga_image_prog_transition(struct fpga_image_load *imgld, + enum fpga_image_prog new_progress) +{ + int ret = 0; + + mutex_lock(&imgld->lock); + if (imgld->request_cancel) { + imgld->err_progress = imgld->progress; + imgld->err_code = FPGA_IMAGE_ERR_CANCELED; + imgld->lops->cancel(imgld); + ret = -ECANCELED; + } else { + imgld->progress = new_progress; + } + mutex_unlock(&imgld->lock); + return ret; +} + static void fpga_image_prog_complete(struct fpga_image_load *imgld) { mutex_lock(&imgld->lock); @@ -77,8 +95,10 @@ static void fpga_image_do_load(struct work_struct *work) goto modput_exit; } - fpga_image_update_progress(imgld, FPGA_IMAGE_PROG_WRITING); - while (imgld->remaining_size) { + if (fpga_image_prog_transition(imgld, FPGA_IMAGE_PROG_WRITING)) + goto done; + + while (imgld->remaining_size && !imgld->request_cancel) { ret = imgld->lops->write_blk(imgld, offset); if (ret != FPGA_IMAGE_ERR_NONE) { fpga_image_dev_error(imgld, ret); @@ -88,7 +108,9 @@ static void fpga_image_do_load(struct work_struct *work) offset = size - imgld->remaining_size; } - fpga_image_update_progress(imgld, FPGA_IMAGE_PROG_PROGRAMMING); + if (fpga_image_prog_transition(imgld, FPGA_IMAGE_PROG_PROGRAMMING)) + goto done; + ret = imgld->lops->poll_complete(imgld); if (ret != FPGA_IMAGE_ERR_NONE) fpga_image_dev_error(imgld, ret); @@ -159,6 +181,7 @@ static int fpga_image_load_ioctl_write(struct fpga_image_load *imgld, imgld->remaining_size = wb.size; imgld->err_code = FPGA_IMAGE_ERR_NONE; imgld->progress = FPGA_IMAGE_PROG_STARTING; + imgld->request_cancel = false; reinit_completion(&imgld->update_done); schedule_work(&imgld->work); return 0; @@ -189,7 +212,7 @@ static long fpga_image_load_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct fpga_image_load *imgld = filp->private_data; - int ret = -ENOTTY; + int ret = 0; mutex_lock(&imgld->lock); @@ -200,6 +223,17 @@ static long fpga_image_load_ioctl(struct file *filp, unsigned int cmd, case FPGA_IMAGE_LOAD_STATUS: ret = fpga_image_load_ioctl_status(imgld, arg); break; + case FPGA_IMAGE_LOAD_CANCEL: + if (imgld->progress == FPGA_IMAGE_PROG_PROGRAMMING) + ret = -EBUSY; + else if (imgld->progress == FPGA_IMAGE_PROG_IDLE) + ret = -ENODEV; + else + imgld->request_cancel = true; + break; + default: + ret = -ENOTTY; + break; } mutex_unlock(&imgld->lock); @@ -374,6 +408,9 @@ void fpga_image_load_unregister(struct fpga_image_load *imgld) goto unregister; } + if (imgld->progress != FPGA_IMAGE_PROG_PROGRAMMING) + imgld->request_cancel = true; + mutex_unlock(&imgld->lock); wait_for_completion(&imgld->update_done); diff --git a/include/linux/fpga/fpga-image-load.h b/include/linux/fpga/fpga-image-load.h index 68f3105b51d2..4e51b9fd1724 100644 --- a/include/linux/fpga/fpga-image-load.h +++ b/include/linux/fpga/fpga-image-load.h @@ -52,6 +52,7 @@ struct fpga_image_load { enum fpga_image_prog progress; enum fpga_image_prog err_progress; /* progress at time of failure */ enum fpga_image_err err_code; /* image load error code */ + bool request_cancel; bool driver_unload; struct eventfd_ctx *finished; void *priv; diff --git a/include/uapi/linux/fpga-image-load.h b/include/uapi/linux/fpga-image-load.h index 6a995bcc0fb7..8d0dfa1f9b77 100644 --- a/include/uapi/linux/fpga-image-load.h +++ b/include/uapi/linux/fpga-image-load.h @@ -39,6 +39,7 @@ enum fpga_image_err { #define FPGA_IMAGE_LOAD_WRITE _IOW(FPGA_IMAGE_LOAD_MAGIC, 0, struct fpga_image_write) #define FPGA_IMAGE_LOAD_STATUS _IOR(FPGA_IMAGE_LOAD_MAGIC, 1, struct fpga_image_status) +#define FPGA_IMAGE_LOAD_CANCEL _IO(FPGA_IMAGE_LOAD_MAGIC, 2) /** * FPGA_IMAGE_LOAD_WRITE - _IOW(FPGA_IMAGE_LOAD_MAGIC, 0,