From patchwork Thu Sep 9 19:49:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12483803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 783D0C433EF for ; Thu, 9 Sep 2021 19:44:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F9F76103D for ; Thu, 9 Sep 2021 19:44:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3F9F76103D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F36386E903; Thu, 9 Sep 2021 19:44:00 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 255D06E902 for ; Thu, 9 Sep 2021 19:43:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="243205710" X-IronPort-AV: E=Sophos;i="5.85,281,1624345200"; d="scan'208";a="243205710" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 12:43:58 -0700 X-IronPort-AV: E=Sophos;i="5.85,281,1624345200"; d="scan'208";a="450112664" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 12:43:58 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: Gwan-gyeong Mun , Daniel Vetter , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Jani Nikula , Rodrigo Vivi , =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= Date: Thu, 9 Sep 2021 12:49:16 -0700 Message-Id: <20210909194917.66433-1-jose.souza@intel.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 1/2] drm/i915/display/skl+: Drop frontbuffer rendering support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" By now all the userspace applications should have migrated to atomic or at least be calling DRM_IOCTL_MODE_DIRTYFB. With that we can kill frontbuffer rendering support in i915 for modern platforms. So here converting legacy APIs into atomic commits so it can be properly handled by driver i915. Several IGT tests will fail with this changes, because some tests were stressing those frontbuffer rendering scenarios that no userspace should be using by now, fixes to IGT should be sent soon. v2: - return earlier to not set fb_tracking.busy/flip_bits - added a warn on to make sure we are not setting the busy/flip_bits Reviewed-by: Gwan-gyeong Mun Cc: Daniel Vetter Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cursor.c | 6 ++---- drivers/gpu/drm/i915/display/intel_fb.c | 8 +++++++- .../gpu/drm/i915/display/intel_frontbuffer.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ 4 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index c7618fef01439..5aa996c3b7980 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -617,6 +617,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, u32 src_w, u32 src_h, struct drm_modeset_acquire_ctx *ctx) { + struct drm_i915_private *i915 = to_i915(_crtc->dev); struct intel_plane *plane = to_intel_plane(_plane); struct intel_crtc *crtc = to_intel_crtc(_crtc); struct intel_plane_state *old_plane_state = @@ -633,12 +634,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane, * PSR2 selective fetch also requires the slow path as * PSR2 plane and transcoder registers can only be updated during * vblank. - * - * FIXME bigjoiner fastpath would be good */ if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || - crtc_state->update_pipe || crtc_state->bigjoiner || - crtc_state->enable_psr2_sel_fetch) + crtc_state->update_pipe || !HAS_FRONTBUFFER_RENDERING(i915)) goto slow; /* diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e4b8602ec0cd2..3eb60785c9f29 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -3,6 +3,7 @@ * Copyright © 2021 Intel Corporation */ +#include #include #include @@ -1235,10 +1236,15 @@ static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, unsigned int num_clips) { struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct drm_i915_private *i915 = to_i915(obj->base.dev); i915_gem_object_flush_if_display(obj); - intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); + if (!HAS_FRONTBUFFER_RENDERING(i915)) + return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips, + num_clips); + + intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 0492446cd04ad..3860f87dac31c 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -112,6 +112,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915, void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915, unsigned frontbuffer_bits) { + if (!HAS_FRONTBUFFER_RENDERING(i915)) + return; + spin_lock(&i915->fb_tracking.lock); i915->fb_tracking.flip_bits |= frontbuffer_bits; /* Remove stale busy bits due to the old buffer. */ @@ -132,6 +135,12 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915, void intel_frontbuffer_flip_complete(struct drm_i915_private *i915, unsigned frontbuffer_bits) { + if (!HAS_FRONTBUFFER_RENDERING(i915)) { + drm_WARN_ON_ONCE(&i915->drm, i915->fb_tracking.flip_bits | + i915->fb_tracking.busy_bits); + return; + } + spin_lock(&i915->fb_tracking.lock); /* Mask any cancelled flips. */ frontbuffer_bits &= i915->fb_tracking.flip_bits; @@ -156,6 +165,9 @@ void intel_frontbuffer_flip_complete(struct drm_i915_private *i915, void intel_frontbuffer_flip(struct drm_i915_private *i915, unsigned frontbuffer_bits) { + if (!HAS_FRONTBUFFER_RENDERING(i915)) + return; + spin_lock(&i915->fb_tracking.lock); /* Remove stale busy bits due to the old buffer. */ i915->fb_tracking.busy_bits &= ~frontbuffer_bits; @@ -170,6 +182,9 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front, { struct drm_i915_private *i915 = to_i915(front->obj->base.dev); + if (!HAS_FRONTBUFFER_RENDERING(i915)) + return; + if (origin == ORIGIN_CS) { spin_lock(&i915->fb_tracking.lock); i915->fb_tracking.busy_bits |= frontbuffer_bits; @@ -191,6 +206,9 @@ void __intel_fb_flush(struct intel_frontbuffer *front, { struct drm_i915_private *i915 = to_i915(front->obj->base.dev); + if (!HAS_FRONTBUFFER_RENDERING(i915)) + return; + if (origin == ORIGIN_CS) { spin_lock(&i915->fb_tracking.lock); /* Filter out new bits since rendering started. */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcdf..3324ba8d8523c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1699,6 +1699,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) +#define HAS_FRONTBUFFER_RENDERING(i915) (DISPLAY_VER(i915) < 9) + /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) From patchwork Thu Sep 9 19:49:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12483801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1479C433F5 for ; Thu, 9 Sep 2021 19:44:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BBA1F61026 for ; Thu, 9 Sep 2021 19:44:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BBA1F61026 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CF356E902; Thu, 9 Sep 2021 19:44:00 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 428326E903 for ; Thu, 9 Sep 2021 19:43:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="243205711" X-IronPort-AV: E=Sophos;i="5.85,281,1624345200"; d="scan'208";a="243205711" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 12:43:58 -0700 X-IronPort-AV: E=Sophos;i="5.85,281,1624345200"; d="scan'208";a="450112666" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 12:43:58 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: Gwan-gyeong Mun , =?utf-8?q?Jos=C3=A9_Roberto?= =?utf-8?q?_de_Souza?= Date: Thu, 9 Sep 2021 12:49:17 -0700 Message-Id: <20210909194917.66433-2-jose.souza@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210909194917.66433-1-jose.souza@intel.com> References: <20210909194917.66433-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 2/2] drm/i915/display: Drop PSR frontbuffer rendering support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After commit "drm/i915/display/skl+: Drop frontbuffer rendering support" frontbuffer rendering is not supported for display 9 and newer and as PSR is only supported by default in display 9 and newer we can now drop all frontbuffer rendering support for PSR code. Some DC3CO code was commented with a macro, because the function caller is being dropped. As DC3CO is already disabled by default because it requires changes in its sequences Two DC3CO functions lost their callers while dropping frontbuffer rendering but as DC3CO is already disabled by default because it requires fixes, will leave this task to whoever will fix DC3CO. Reviewed-by: Gwan-gyeong Mun Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_debugfs.c | 2 - .../drm/i915/display/intel_display_types.h | 2 - .../gpu/drm/i915/display/intel_frontbuffer.c | 2 - drivers/gpu/drm/i915/display/intel_psr.c | 186 ++---------------- drivers/gpu/drm/i915/display/intel_psr.h | 8 +- 5 files changed, 18 insertions(+), 182 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 68f4ba8c46e75..33d71edfc0630 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -374,8 +374,6 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", enableddisabled(enabled), val); psr_source_status(intel_dp, m); - seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", - psr->busy_frontbuffer_bits); /* * SKL+ Perf counter is reset to 0 everytime DC state is entered diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index c7bcf9183447b..ddd51aa1649c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1512,7 +1512,6 @@ struct intel_psr { enum transcoder transcoder; bool active; struct work_struct work; - unsigned int busy_frontbuffer_bits; bool sink_psr2_support; bool link_standby; bool colorimetry_support; @@ -1523,7 +1522,6 @@ struct intel_psr { ktime_t last_entry_attempt; ktime_t last_exit; bool sink_not_reliable; - bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; u32 dc3co_exitline; diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 3860f87dac31c..1d8314d3712f4 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -93,7 +93,6 @@ static void frontbuffer_flush(struct drm_i915_private *i915, might_sleep(); intel_drrs_flush(i915, frontbuffer_bits); - intel_psr_flush(i915, frontbuffer_bits, origin); intel_fbc_flush(i915, frontbuffer_bits, origin); } @@ -195,7 +194,6 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front, trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin); might_sleep(); - intel_psr_invalidate(i915, frontbuffer_bits, origin); intel_drrs_invalidate(i915, frontbuffer_bits); intel_fbc_invalidate(i915, frontbuffer_bits, origin); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3f6fb7d67f84d..8c9bd5846a8d0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -224,15 +224,12 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", transcoder_name(cpu_transcoder)); - intel_dp->psr.irq_aux_error = true; - /* * If this interruption is not masked it will keep * interrupting so fast that it prevents the scheduled * work to run. * Also after a PSR error, we don't want to arm PSR * again so we don't care about unmask the interruption - * or unset irq_aux_error. */ val = intel_de_read(dev_priv, imr_reg); val |= EDP_PSR_ERROR(trans_shift); @@ -614,14 +611,6 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp, intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); } -static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) -{ - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - - psr2_program_idle_frames(intel_dp, 0); - intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); -} - static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1177,7 +1166,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); intel_dp->psr.psr2_enabled = crtc_state->has_psr2; - intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; intel_dp->psr.transcoder = crtc_state->cpu_transcoder; /* DC5/DC6 requires at least 6 idle frames */ @@ -1784,36 +1772,6 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) } } -static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) -{ - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - i915_reg_t reg; - u32 mask; - int err; - - if (!intel_dp->psr.enabled) - return false; - - if (intel_dp->psr.psr2_enabled) { - reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); - mask = EDP_PSR2_STATUS_STATE_MASK; - } else { - reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); - mask = EDP_PSR_STATUS_STATE_MASK; - } - - mutex_unlock(&intel_dp->psr.lock); - - err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); - if (err) - drm_err(&dev_priv->drm, - "Timed out waiting for PSR Idle for re-enable\n"); - - /* After the unlocked wait, verify that PSR is still wanted! */ - mutex_lock(&intel_dp->psr.lock); - return err == 0 && intel_dp->psr.enabled; -} - static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) { struct drm_connector_list_iter conn_iter; @@ -1912,16 +1870,6 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) return ret; } -static void intel_psr_handle_irq(struct intel_dp *intel_dp) -{ - struct intel_psr *psr = &intel_dp->psr; - - intel_psr_disable_locked(intel_dp); - psr->sink_not_reliable = true; - /* let's make sure that sink is awaken */ - drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); -} - static void intel_psr_work(struct work_struct *work) { struct intel_dp *intel_dp = @@ -1929,75 +1877,30 @@ static void intel_psr_work(struct work_struct *work) mutex_lock(&intel_dp->psr.lock); - if (!intel_dp->psr.enabled) - goto unlock; - - if (READ_ONCE(intel_dp->psr.irq_aux_error)) - intel_psr_handle_irq(intel_dp); - - /* - * We have to make sure PSR is ready for re-enable - * otherwise it keeps disabled until next full enable/disable cycle. - * PSR might take some time to get fully disabled - * and be ready for re-enable. - */ - if (!__psr_wait_for_idle_locked(intel_dp)) - goto unlock; - - /* - * The delayed work can race with an invalidate hence we need to - * recheck. Since psr_flush first clears this and then reschedules we - * won't ever miss a flush when bailing out here. - */ - if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) - goto unlock; + /* Handling PSR error interruption */ + intel_psr_disable_locked(intel_dp); + intel_dp->psr.sink_not_reliable = true; + /* let's make sure that sink is awaken */ + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - intel_psr_activate(intel_dp); -unlock: mutex_unlock(&intel_dp->psr.lock); } -/** - * intel_psr_invalidate - Invalidade PSR - * @dev_priv: i915 device - * @frontbuffer_bits: frontbuffer plane tracking bits - * @origin: which operation caused the invalidate - * - * Since the hardware frontbuffer tracking has gaps we need to integrate - * with the software frontbuffer tracking. This function gets called every - * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be - * disabled if the frontbuffer mask contains a buffer relevant to PSR. - * - * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." +/* + * TODO: Functions below lost their callers to a refactor but as DC3CO is + * already disabled by default because it requires fixes, will leave this task + * to whoever will fix DC3CO. */ -void intel_psr_invalidate(struct drm_i915_private *dev_priv, - unsigned frontbuffer_bits, enum fb_op_origin origin) -{ - struct intel_encoder *encoder; - - if (origin == ORIGIN_FLIP) - return; - - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { - unsigned int pipe_frontbuffer_bits = frontbuffer_bits; - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - - mutex_lock(&intel_dp->psr.lock); - if (!intel_dp->psr.enabled) { - mutex_unlock(&intel_dp->psr.lock); - continue; - } - - pipe_frontbuffer_bits &= - INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); - intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; +#if 0 - if (pipe_frontbuffer_bits) - intel_psr_exit(intel_dp); +static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - mutex_unlock(&intel_dp->psr.lock); - } + psr2_program_idle_frames(intel_dp, 0); + intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); } + /* * When we will be completely rely on PSR2 S/W tracking in future, * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP @@ -2032,62 +1935,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, mutex_unlock(&intel_dp->psr.lock); } -/** - * intel_psr_flush - Flush PSR - * @dev_priv: i915 device - * @frontbuffer_bits: frontbuffer plane tracking bits - * @origin: which operation caused the flush - * - * Since the hardware frontbuffer tracking has gaps we need to integrate - * with the software frontbuffer tracking. This function gets called every - * time frontbuffer rendering has completed and flushed out to memory. PSR - * can be enabled again if no other frontbuffer relevant to PSR is dirty. - * - * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. - */ -void intel_psr_flush(struct drm_i915_private *dev_priv, - unsigned frontbuffer_bits, enum fb_op_origin origin) -{ - struct intel_encoder *encoder; - - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { - unsigned int pipe_frontbuffer_bits = frontbuffer_bits; - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - - if (origin == ORIGIN_FLIP) { - tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin); - continue; - } - - mutex_lock(&intel_dp->psr.lock); - if (!intel_dp->psr.enabled) { - mutex_unlock(&intel_dp->psr.lock); - continue; - } - - pipe_frontbuffer_bits &= - INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); - intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; - - /* - * If the PSR is paused by an explicit intel_psr_paused() call, - * we have to ensure that the PSR is not activated until - * intel_psr_resume() is called. - */ - if (intel_dp->psr.paused) { - mutex_unlock(&intel_dp->psr.lock); - continue; - } - - /* By definition flush = invalidate + flush */ - if (pipe_frontbuffer_bits) - psr_force_hw_tracking_exit(intel_dp); - - if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) - schedule_work(&intel_dp->psr.work); - mutex_unlock(&intel_dp->psr.lock); - } -} +#endif /** * intel_psr_init - Init basic PSR work and mutex. diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 641521b101c82..58e2e5c2b81ef 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -6,7 +6,7 @@ #ifndef __INTEL_PSR_H__ #define __INTEL_PSR_H__ -#include "intel_frontbuffer.h" +#include struct drm_connector; struct drm_connector_state; @@ -29,12 +29,6 @@ void intel_psr_update(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value); -void intel_psr_invalidate(struct drm_i915_private *dev_priv, - unsigned frontbuffer_bits, - enum fb_op_origin origin); -void intel_psr_flush(struct drm_i915_private *dev_priv, - unsigned frontbuffer_bits, - enum fb_op_origin origin); void intel_psr_init(struct intel_dp *intel_dp); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state);