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Mon, 13 Sep 2021 17:36:47 +0000 From: Sunil Muthuswamy To: Michael Kelley , Boqun Feng , KY Srinivasan , Haiyang Zhang , Stephen Hemminger , Dexuan Cui , Lorenzo Pieralisi , Rob Herring , =?iso-8859-2?q?=22Krzysztof_Wilczy=F1ski=22?= , Bjorn Helgaas , Wei Liu CC: "linux-hyperv@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 1/2] PCI: hv: Make the code arch neutral Thread-Topic: [PATCH 1/2] PCI: hv: Make the code arch neutral Thread-Index: AdeoxSGQR+XTDCnuQJejgIDf8UzhEg== Date: Mon, 13 Sep 2021 17:36:46 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microsoft.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a4fa2991-034c-423e-c0f3-08d976dd0ffc x-ms-traffictypediagnostic: MWHPR21MB0830: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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This allows for the implementation of Hyper-V vPCI for other architecture such as ARM64. There are no functional changes expected from this patch. Signed-off-by: Sunil Muthuswamy --- arch/x86/include/asm/hyperv-tlfs.h | 33 ++++++++++++++++++++++ arch/x86/include/asm/mshyperv.h | 25 ++++++++++++++++ drivers/pci/controller/pci-hyperv.c | 44 +++++++++++++++++++---------- include/asm-generic/hyperv-tlfs.h | 33 ---------------------- 4 files changed, 87 insertions(+), 48 deletions(-) diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h index 2322d6bd5883..fdf3d28fbdd5 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -585,6 +585,39 @@ enum hv_interrupt_type { HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, }; +union hv_msi_address_register { + u32 as_uint32; + struct { + u32 reserved1:2; + u32 destination_mode:1; + u32 redirection_hint:1; + u32 reserved2:8; + u32 destination_id:8; + u32 msi_base:12; + }; +} __packed; + +union hv_msi_data_register { + u32 as_uint32; + struct { + u32 vector:8; + u32 delivery_mode:3; + u32 reserved1:3; + u32 level_assert:1; + u32 trigger_mode:1; + u32 reserved2:16; + }; +} __packed; + +/* HvRetargetDeviceInterrupt hypercall */ +union hv_msi_entry { + u64 as_uint64; + struct { + union hv_msi_address_register address; + union hv_msi_data_register data; + } __packed; +}; + #include #endif diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h index adccbc209169..9c53dfef360c 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -10,6 +10,7 @@ #include #include #include +#include typedef int (*hyperv_fill_flush_list_func)( struct hv_guest_mapping_flush_list *flush, @@ -168,6 +169,30 @@ int hyperv_fill_flush_guest_mapping_list( struct hv_guest_mapping_flush_list *flush, u64 start_gfn, u64 end_gfn); +#define hv_msi_handler handle_edge_irq +#define hv_msi_handler_name "edge" +#define hv_msi_prepare pci_msi_prepare +#define hv_msi_irq_delivery_mode APIC_DELIVERY_MODE_FIXED + +static inline struct irq_domain *hv_msi_parent_vector_domain(void) +{ + return x86_vector_domain; +} + +static inline unsigned int hv_msi_get_int_vector(struct irq_data *data) +{ + struct irq_cfg *cfg = irqd_cfg(data); + + return cfg->vector; +} + +static inline int hv_pci_arch_init(void) +{ + return 0; +} + +static inline void hv_pci_arch_free(void) {} + #ifdef CONFIG_X86_64 void hv_apic_init(void); void __init hv_init_spinlocks(void); diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c index 62dbe98d1fe1..b7213b57b4ec 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -44,8 +44,8 @@ #include #include #include -#include -#include +//#include +//#include #include #include #include @@ -1192,7 +1192,6 @@ static void hv_irq_mask(struct irq_data *data) static void hv_irq_unmask(struct irq_data *data) { struct msi_desc *msi_desc = irq_data_get_msi_desc(data); - struct irq_cfg *cfg = irqd_cfg(data); struct hv_retarget_device_interrupt *params; struct hv_pcibus_device *hbus; struct cpumask *dest; @@ -1221,11 +1220,12 @@ static void hv_irq_unmask(struct irq_data *data) (hbus->hdev->dev_instance.b[7] << 8) | (hbus->hdev->dev_instance.b[6] & 0xf8) | PCI_FUNC(pdev->devfn); - params->int_target.vector = cfg->vector; + params->int_target.vector = hv_msi_get_int_vector(data); /* - * Honoring apic->delivery_mode set to APIC_DELIVERY_MODE_FIXED by - * setting the HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a + * For x64, honoring apic->delivery_mode set to + * APIC_DELIVERY_MODE_FIXED by setting the + * HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a * spurious interrupt storm. Not doing so does not seem to have a * negative effect (yet?). */ @@ -1322,7 +1322,7 @@ static u32 hv_compose_msi_req_v1( int_pkt->wslot.slot = slot; int_pkt->int_desc.vector = vector; int_pkt->int_desc.vector_count = 1; - int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED; + int_pkt->int_desc.delivery_mode = hv_msi_irq_delivery_mode; /* * Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in @@ -1343,7 +1343,7 @@ static u32 hv_compose_msi_req_v2( int_pkt->wslot.slot = slot; int_pkt->int_desc.vector = vector; int_pkt->int_desc.vector_count = 1; - int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED; + int_pkt->int_desc.delivery_mode = hv_msi_irq_delivery_mode; /* * Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten @@ -1370,7 +1370,6 @@ static u32 hv_compose_msi_req_v2( */ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct irq_cfg *cfg = irqd_cfg(data); struct hv_pcibus_device *hbus; struct vmbus_channel *channel; struct hv_pci_dev *hpdev; @@ -1420,7 +1419,7 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1, dest, hpdev->desc.win_slot.slot, - cfg->vector); + hv_msi_get_int_vector(data)); break; case PCI_PROTOCOL_VERSION_1_2: @@ -1428,7 +1427,7 @@ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2, dest, hpdev->desc.win_slot.slot, - cfg->vector); + hv_msi_get_int_vector(data)); break; default: @@ -1544,7 +1543,7 @@ static struct irq_chip hv_msi_irq_chip = { }; static struct msi_domain_ops hv_msi_ops = { - .msi_prepare = pci_msi_prepare, + .msi_prepare = hv_msi_prepare, .msi_free = hv_msi_free, }; @@ -1563,17 +1562,26 @@ static struct msi_domain_ops hv_msi_ops = { */ static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus) { + struct irq_domain *parent_domain; + + parent_domain = hv_msi_parent_vector_domain(); + if (!parent_domain) { + dev_err(&hbus->hdev->device, + "Failed to get parent MSI domain\n"); + return -ENODEV; + } + hbus->msi_info.chip = &hv_msi_irq_chip; hbus->msi_info.ops = &hv_msi_ops; hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX); - hbus->msi_info.handler = handle_edge_irq; - hbus->msi_info.handler_name = "edge"; + hbus->msi_info.handler = hv_msi_handler; + hbus->msi_info.handler_name = hv_msi_handler_name; hbus->msi_info.data = hbus; hbus->irq_domain = pci_msi_create_irq_domain(hbus->fwnode, &hbus->msi_info, - x86_vector_domain); + parent_domain); if (!hbus->irq_domain) { dev_err(&hbus->hdev->device, "Failed to build an MSI IRQ domain\n"); @@ -3478,9 +3486,15 @@ static void __exit exit_hv_pci_drv(void) static int __init init_hv_pci_drv(void) { + int ret; + if (!hv_is_hyperv_initialized()) return -ENODEV; + ret = hv_pci_arch_init(); + if (ret) + return ret; + /* Set the invalid domain number's bit, so it will not be used */ set_bit(HVPCI_DOM_INVALID, hvpci_dom_map); diff --git a/include/asm-generic/hyperv-tlfs.h b/include/asm-generic/hyperv-tlfs.h index 56348a541c50..45cc0c3b8ed7 100644 --- a/include/asm-generic/hyperv-tlfs.h +++ b/include/asm-generic/hyperv-tlfs.h @@ -539,39 +539,6 @@ enum hv_interrupt_source { HV_INTERRUPT_SOURCE_IOAPIC, }; -union hv_msi_address_register { - u32 as_uint32; - struct { - u32 reserved1:2; - u32 destination_mode:1; - u32 redirection_hint:1; - u32 reserved2:8; - u32 destination_id:8; - u32 msi_base:12; - }; -} __packed; - -union hv_msi_data_register { - u32 as_uint32; - struct { - u32 vector:8; - u32 delivery_mode:3; - u32 reserved1:3; - u32 level_assert:1; - u32 trigger_mode:1; - u32 reserved2:16; - }; -} __packed; - -/* HvRetargetDeviceInterrupt hypercall */ -union hv_msi_entry { - u64 as_uint64; - struct { - union hv_msi_address_register address; - union hv_msi_data_register data; - } __packed; -}; - union hv_ioapic_rte { u64 as_uint64; From patchwork Mon Sep 13 17:37:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Muthuswamy X-Patchwork-Id: 12490255 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49CDFC433FE for ; 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Mon, 13 Sep 2021 17:37:22 +0000 Received: from MW4PR21MB2002.namprd21.prod.outlook.com ([fe80::b134:7809:fcff:8c8b]) by MW4PR21MB2002.namprd21.prod.outlook.com ([fe80::b134:7809:fcff:8c8b%4]) with mapi id 15.20.4523.011; Mon, 13 Sep 2021 17:37:22 +0000 From: Sunil Muthuswamy To: Michael Kelley , Boqun Feng , KY Srinivasan , Haiyang Zhang , Stephen Hemminger , Dexuan Cui , Lorenzo Pieralisi , Rob Herring , =?iso-8859-2?q?=22Krzysztof_Wilczy=F1ski=22?= , Bjorn Helgaas , Wei Liu CC: "linux-hyperv@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 2/2] PCI: hv: Support for Hyper-V vPCI for ARM64 Thread-Topic: [PATCH 2/2] PCI: hv: Support for Hyper-V vPCI for ARM64 Thread-Index: AdeoxTZsllWVtNf9RIGrn88zMhJayQ== Date: Mon, 13 Sep 2021 17:37:22 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microsoft.com; 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The IRQ domain parents itself to the arch GIC IRQ domain for basic vector management. Signed-off-by: Sunil Muthuswamy --- arch/arm64/hyperv/Makefile | 2 +- arch/arm64/hyperv/hv_pci.c | 275 +++++++++++++++++++++++++++ arch/arm64/include/asm/hyperv-tlfs.h | 9 + arch/arm64/include/asm/mshyperv.h | 26 +++ drivers/pci/Kconfig | 2 +- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pci-hyperv.c | 5 + 7 files changed, 318 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/hyperv/hv_pci.c diff --git a/arch/arm64/hyperv/Makefile b/arch/arm64/hyperv/Makefile index 87c31c001da9..af7a66e43ef4 100644 --- a/arch/arm64/hyperv/Makefile +++ b/arch/arm64/hyperv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y := hv_core.o mshyperv.o +obj-y := hv_core.o mshyperv.o hv_pci.o diff --git a/arch/arm64/hyperv/hv_pci.c b/arch/arm64/hyperv/hv_pci.c new file mode 100644 index 000000000000..06179e4a6a2d --- /dev/null +++ b/arch/arm64/hyperv/hv_pci.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Architecture specific vector management for the Hyper-V vPCI. + * + * Copyright (C) 2018, Microsoft, Inc. + * + * Author : Sunil Muthuswamy + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + */ + +#include +#include +#include +#include +#include + +/* + * SPI vectors to use for vPCI; arch SPIs range is [32, 1019], but leaving a bit + * of room at the start to allow for SPIs to be specified through ACPI. + */ +#define HV_PCI_MSI_SPI_START 50 +#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START) + +struct hv_pci_chip_data { + spinlock_t lock; + DECLARE_BITMAP(bm, HV_PCI_MSI_SPI_NR); +}; + +/* Hyper-V vPCI MSI GIC IRQ domain */ +static struct irq_domain *hv_msi_gic_irq_domain; + +static struct irq_chip hv_msi_irq_chip = { + .name = "Hyper-V ARM64 PCI MSI", + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent +}; + +/** + * Frees the specified number of interrupts. + * @domain: The IRQ domain + * @virq: The virtual IRQ number. + * @nr_irqs: Number of IRQ's to free. + */ +static void hv_pci_vec_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct hv_pci_chip_data *chip_data = domain->host_data; + unsigned long flags; + unsigned int i; + + for (i = 0; i < nr_irqs; i++) { + struct irq_data *irqd = irq_domain_get_irq_data(domain, + virq + i); + + spin_lock_irqsave(&chip_data->lock, flags); + clear_bit(irqd->hwirq - HV_PCI_MSI_SPI_START, chip_data->bm); + spin_unlock_irqrestore(&chip_data->lock, flags); + irq_domain_reset_irq_data(irqd); + } + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +/** + * Allocate an interrupt from the domain. + * @hwirq: Will be set to the allocated H/W IRQ. + * + * Return: 0 on success and error value on failure. + */ +static int hv_pci_vec_alloc_device_irq(struct irq_domain *domain, + unsigned int virq, irq_hw_number_t *hwirq) +{ + struct hv_pci_chip_data *chip_data = domain->host_data; + unsigned long flags; + unsigned int index; + + spin_lock_irqsave(&chip_data->lock, flags); + index = find_first_zero_bit(chip_data->bm, HV_PCI_MSI_SPI_NR); + if (index == HV_PCI_MSI_SPI_NR) { + spin_unlock_irqrestore(&chip_data->lock, flags); + pr_err("No more free IRQ vector available\n"); + return -ENOSPC; + } + + set_bit(index, chip_data->bm); + spin_unlock_irqrestore(&chip_data->lock, flags); + *hwirq = index + HV_PCI_MSI_SPI_START; + + return 0; +} + +/** + * Allocate an interrupt from the parent GIC domain. + * @domain: The IRQ domain. + * @virq: The virtual IRQ number. + * @hwirq: The H/W IRQ number that needs to be allocated. + * + * Return: 0 on success and error value on failure. + */ +static int hv_pci_vec_irq_gic_domain_alloc(struct irq_domain *domain, + unsigned int virq, + irq_hw_number_t hwirq) +{ + struct irq_fwspec fwspec; + + fwspec.fwnode = domain->parent->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = hwirq; + fwspec.param[1] = IRQ_TYPE_EDGE_RISING; + + return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); +} + +/** + * Allocate specified number of interrupts from the domain. + * @domain: The IRQ domain. + * @virq: The starting virtual IRQ number. + * @nr_irqs: Number of IRQ's to allocate. + * @args: The MSI alloc information. + * + * Return: 0 on success and error value on failure. + */ +static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + irq_hw_number_t hwirq; + unsigned int i; + int ret; + + for (i = 0; i < nr_irqs; i++) { + ret = hv_pci_vec_alloc_device_irq(domain, virq, &hwirq); + if (ret) + goto free_irq; + + ret = hv_pci_vec_irq_gic_domain_alloc(domain, virq + i, hwirq); + if (ret) + goto free_irq; + + ret = irq_domain_set_hwirq_and_chip(domain, virq + i, + hwirq, &hv_msi_irq_chip, + domain->host_data); + if (ret) + goto free_irq; + + irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); + pr_debug("pID:%d vID:%u\n", (int)hwirq, virq + i); + } + + return 0; + +free_irq: + if (i > 0) + hv_pci_vec_irq_domain_free(domain, virq, i - 1); + + return ret; +} + +/** + * Activate the interrupt. + * @domain: The IRQ domain. + * @irqd: IRQ data. + * @reserve: Indicates whether the IRQ's can be reserved. + * + * Return: 0 on success and error value on failure. + */ +static int hv_pci_vec_irq_domain_activate(struct irq_domain *domain, + struct irq_data *irqd, bool reserve) +{ + /* All available online CPUs are available for targeting */ + irq_data_update_effective_affinity(irqd, cpu_online_mask); + return 0; +} + +static const struct irq_domain_ops hv_pci_domain_ops = { + .alloc = hv_pci_vec_irq_domain_alloc, + .free = hv_pci_vec_irq_domain_free, + .activate = hv_pci_vec_irq_domain_activate, +}; + + +/** + * This routine performs the architecture specific initialization for vector + * domain to operate. It allocates an IRQ domain tree as a child of the GIC + * IRQ domain. + * + * Return: 0 on success and error value on failure. + */ +int hv_pci_vector_init(void) +{ + static struct hv_pci_chip_data *chip_data; + struct fwnode_handle *fn = NULL; + int ret = -ENOMEM; + + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL); + if (!chip_data) + return ret; + + spin_lock_init(&chip_data->lock); + fn = irq_domain_alloc_named_fwnode("Hyper-V ARM64 vPCI"); + if (!fn) + goto free_chip; + + hv_msi_gic_irq_domain = acpi_irq_create_hierarchy(0, HV_PCI_MSI_SPI_NR, + fn, &hv_pci_domain_ops, chip_data); + + if (!hv_msi_gic_irq_domain) { + pr_err("Failed to create Hyper-V ARMV vPCI MSI IRQ domain\n"); + goto free_chip; + } + + return 0; + +free_chip: + kfree(chip_data); + if (fn) + irq_domain_free_fwnode(fn); + + return ret; +} + +/* This routine performs the cleanup for the IRQ domain. */ +void hv_pci_vector_free(void) +{ + static struct hv_pci_chip_data *chip_data; + + if (!hv_msi_gic_irq_domain) + return; + + /* Host data cannot be null if the domain was created successfully */ + chip_data = hv_msi_gic_irq_domain->host_data; + irq_domain_remove(hv_msi_gic_irq_domain); + hv_msi_gic_irq_domain = NULL; + kfree(chip_data); +} + +/* Performs the architecture specific initialization for Hyper-V vPCI. */ +int hv_pci_arch_init(void) +{ + return hv_pci_vector_init(); +} +EXPORT_SYMBOL_GPL(hv_pci_arch_init); + +/* Architecture specific cleanup for Hyper-V vPCI. */ +void hv_pci_arch_free(void) +{ + hv_pci_vector_free(); +} +EXPORT_SYMBOL_GPL(hv_pci_arch_free); + +struct irq_domain *hv_msi_parent_vector_domain(void) +{ + return hv_msi_gic_irq_domain; +} +EXPORT_SYMBOL_GPL(hv_msi_parent_vector_domain); + +unsigned int hv_msi_get_int_vector(struct irq_data *irqd) +{ + irqd = irq_domain_get_irq_data(hv_msi_gic_irq_domain, irqd->irq); + + return irqd->hwirq; +} +EXPORT_SYMBOL_GPL(hv_msi_get_int_vector); diff --git a/arch/arm64/include/asm/hyperv-tlfs.h b/arch/arm64/include/asm/hyperv-tlfs.h index 4d964a7f02ee..bc6c7ac934a1 100644 --- a/arch/arm64/include/asm/hyperv-tlfs.h +++ b/arch/arm64/include/asm/hyperv-tlfs.h @@ -64,6 +64,15 @@ #define HV_REGISTER_STIMER0_CONFIG 0x000B0000 #define HV_REGISTER_STIMER0_COUNT 0x000B0001 +union hv_msi_entry { + u64 as_uint64[2]; + struct { + u64 address; + u32 data; + u32 reserved; + } __packed; +}; + #include #endif diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/mshyperv.h index 20070a847304..68bc1617707b 100644 --- a/arch/arm64/include/asm/mshyperv.h +++ b/arch/arm64/include/asm/mshyperv.h @@ -20,6 +20,8 @@ #include #include +#include +#include #include /* @@ -49,6 +51,30 @@ static inline u64 hv_get_register(unsigned int reg) ARM_SMCCC_OWNER_VENDOR_HYP, \ HV_SMCCC_FUNC_NUMBER) +#define hv_msi_handler NULL +#define hv_msi_handler_name NULL +#define hv_msi_irq_delivery_mode 0 +#define hv_msi_prepare NULL + +int hv_pci_arch_init(void); +void hv_pci_arch_free(void); +struct irq_domain *hv_msi_parent_vector_domain(void); +unsigned int hv_msi_get_int_vector(struct irq_data *data); +static inline irq_hw_number_t +hv_msi_domain_ops_get_hwirq(struct msi_domain_info *info, + msi_alloc_info_t *arg) +{ + return arg->hwirq; +} + +static inline void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry, + struct msi_desc *msi_desc) +{ + msi_entry->address = ((u64)msi_desc->msg.address_hi << 32) | + msi_desc->msg.address_lo; + msi_entry->data = msi_desc->msg.data; +} + #include #endif diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 0c473d75e625..36dc94407510 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -184,7 +184,7 @@ config PCI_LABEL config PCI_HYPERV tristate "Hyper-V PCI Frontend" - depends on X86_64 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS + depends on (X86_64 || ARM64) && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS select PCI_HYPERV_INTERFACE help The PCI device frontend driver allows the kernel to import arbitrary diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5e1e3796efa4..8a19a3dc339c 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -279,7 +279,7 @@ config PCIE_BRCMSTB config PCI_HYPERV_INTERFACE tristate "Hyper-V PCI Interface" - depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64 + depends on (X86_64 || ARM64) && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN help The Hyper-V PCI Interface is a helper driver allows other drivers to have a common interface with the Hyper-V PCI frontend driver. diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c index b7213b57b4ec..79a29a18e84e 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -1177,6 +1177,8 @@ static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest, static void hv_irq_mask(struct irq_data *data) { pci_msi_mask_irq(data); + if (data->parent_data->chip->irq_mask) + irq_chip_mask_parent(data); } /** @@ -1294,6 +1296,8 @@ static void hv_irq_unmask(struct irq_data *data) dev_err(&hbus->hdev->device, "%s() failed: %#llx", __func__, res); + if (data->parent_data->chip->irq_unmask) + irq_chip_unmask_parent(data); pci_msi_unmask_irq(data); } @@ -1538,6 +1542,7 @@ static struct irq_chip hv_msi_irq_chip = { .irq_compose_msi_msg = hv_compose_msi_msg, .irq_set_affinity = hv_set_affinity, .irq_ack = irq_chip_ack_parent, + .irq_eoi = irq_chip_eoi_parent, .irq_mask = hv_irq_mask, .irq_unmask = hv_irq_unmask, };