From patchwork Thu Sep 16 08:49:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 12498317 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D28BEC4332F for ; Thu, 16 Sep 2021 08:49:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC72061178 for ; Thu, 16 Sep 2021 08:49:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235373AbhIPIuz (ORCPT ); Thu, 16 Sep 2021 04:50:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235388AbhIPIuz (ORCPT ); Thu, 16 Sep 2021 04:50:55 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F097BC061574; Thu, 16 Sep 2021 01:49:34 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id q3so13975660edt.5; Thu, 16 Sep 2021 01:49:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RnSNDopoK7uzkv1l2SFpaqjIdHMpI/zWn43dXT0r6aQ=; b=XuVDccirWBzX5u3qll6e3uICln4x1nn+9tWbpk0R3yo9+Uwdb9lzlYLLr2cW1EMaJm g2iBpH25FcxDol2db3LHMNqNPbRl75LzSguzoaeQ03X56FTHG8lPH+Q2BGNpxgLqLKqz oilUu5MC1Bzasct0SHtbG/ufKxh87qE4ztEO7h5cF4mPD76bgB8xlz5lmdCzk2RU4ppe dVX7ty3uxm0CSo5p+2ROSq0B3DoDwq0Yk+b7aZe54qLWyv5D6r7Y1X68bgT4nx8tHxH2 7kja2EchsSxhVc0SWcNSBeM+4X+USskLSnvf2qhso5/VQZyOcKTO2hxavPINn5gaJNHE CO5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RnSNDopoK7uzkv1l2SFpaqjIdHMpI/zWn43dXT0r6aQ=; b=D1pmA0u2bb87+tdACKZqLYq0uejy9DaBc7p/T9dtz1nYWzCeWbfzMRFdtV5hs2xLWl AFviFHZFYeZ4QmrhQYH9suERTNR+Lt0ejejXWXlKNQHcZlwIW7MPz5NJ3L4vCFcVsx4G ZMSbSvn82K+o433ED6A3Cz+Etq1HPneBPjGXGO8PAcnpW6B0/Qz7sL+jP7hrOwmBxMQj WKcLlgqH7b1XV1le/uHfqVLeDEDA5n9rBFnPwxmlhz5eSkw1d4qRMkLRsNZD6XmPf+q+ +Wwokp++n4IJaXls5D4xrCo9xvNCIphPVTK6r2zIzz+PSYdP483gXgdiQbVGN0RjEU5V L9qw== X-Gm-Message-State: AOAM532M+dYCOhpY0CaEOJetpLM8kNfM33qwho/nynI1PZbkpDGrmSyR IeIN3t1iVS/0L2OmKn528RQ= X-Google-Smtp-Source: ABdhPJzmRbZZ8GIc6Eaea4I/H8qx3qX7CGhUJbMarWSz2ENbCxHg1ERF/bEheLjZy6l6xtNZCeuq4g== X-Received: by 2002:a17:906:f289:: with SMTP id gu9mr4816673ejb.559.1631782173499; Thu, 16 Sep 2021 01:49:33 -0700 (PDT) Received: from localhost.localdomain (catv-176-63-0-115.catv.broadband.hu. [176.63.0.115]) by smtp.googlemail.com with ESMTPSA id dh16sm1085838edb.63.2021.09.16.01.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 01:49:33 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com Subject: [RFC PATCH 1/3 v1] PCI/ASPM: Remove cached latencies in struct pcie_link_state Date: Thu, 16 Sep 2021 10:49:24 +0200 Message-Id: <20210916084926.32614-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210916084926.32614-1-refactormyself@gmail.com> References: <20210916084926.32614-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The latencies of the upstream and downstream are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.latency_* These values are only used in pcie_aspm_check_latency() where they are compared with the acceptable latencies on the link. This patch: - removes `latency_*` entries from struct pcie_link_state. - calculates the latencies directly where they are needed. - moves pci_function_0() upward, so that the downstream device can be obtained directly. - further removes dependencies on struct pcie_link_state. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 013a47f587ce..9e85dfc56657 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -66,9 +66,6 @@ struct pcie_link_state { u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - /* Exit latencies */ - struct aspm_latency latency_up; /* Upstream direction exit latency */ - struct aspm_latency latency_dw; /* Downstream direction exit latency */ /* * Endpoint acceptable latencies. A pcie downstream port only * has one slot under it, so at most there are 8 functions. @@ -376,9 +373,25 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } } +/* + * The L1 PM substate capability is only implemented in function 0 in a + * multi function device. + */ +static struct pci_dev *pci_function_0(struct pci_bus *linkbus) +{ + struct pci_dev *child; + + list_for_each_entry(child, &linkbus->devices, bus_list) + if (PCI_FUNC(child->devfn) == 0) + return child; + return NULL; +} + static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, l1_switch_latency = 0; + u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + struct pci_dev *downstream; + struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; struct pcie_link_state *link; @@ -388,17 +401,26 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) return; link = endpoint->bus->self->link_state; + downstream = pci_function_0(link->pdev->subordinate); acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; while (link) { + /* Read direction exit latencies */ + pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, &lnkcap_up); + pcie_capability_read_dword(downstream, PCI_EXP_LNKCAP, &lnkcap_dw); + latency_up.l0s = calc_l0s_latency(lnkcap_up); + latency_up.l1 = calc_l1_latency(lnkcap_up); + latency_dw.l0s = calc_l0s_latency(lnkcap_dw); + latency_dw.l1 = calc_l1_latency(lnkcap_dw); + /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (link->latency_up.l0s > acceptable->l0s)) + (latency_up.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (link->latency_dw.l0s > acceptable->l0s)) + (latency_dw.l0s > acceptable->l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -413,7 +435,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); + latency = max_t(u32, latency_up.l1, latency_dw.l1); if ((link->aspm_capable & ASPM_STATE_L1) && (latency + l1_switch_latency > acceptable->l1)) link->aspm_capable &= ~ASPM_STATE_L1; @@ -423,20 +445,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) } } -/* - * The L1 PM substate capability is only implemented in function 0 in a - * multi function device. - */ -static struct pci_dev *pci_function_0(struct pci_bus *linkbus) -{ - struct pci_dev *child; - - list_for_each_entry(child, &linkbus->devices, bus_list) - if (PCI_FUNC(child->devfn) == 0) - return child; - return NULL; -} - static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, u32 clear, u32 set) { @@ -593,8 +601,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(parent_lnkcap); - link->latency_dw.l0s = calc_l0s_latency(child_lnkcap); /* Setup L1 state */ if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) @@ -602,8 +608,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(parent_lnkcap); - link->latency_dw.l1 = calc_l1_latency(child_lnkcap); /* Setup L1 substate */ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, From patchwork Thu Sep 16 08:49:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 12498319 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65C46C433EF for ; Thu, 16 Sep 2021 08:49:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E2D161178 for ; Thu, 16 Sep 2021 08:49:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235391AbhIPIu5 (ORCPT ); Thu, 16 Sep 2021 04:50:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235394AbhIPIu4 (ORCPT ); Thu, 16 Sep 2021 04:50:56 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE4CCC061574; Thu, 16 Sep 2021 01:49:35 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id g8so13982266edt.7; Thu, 16 Sep 2021 01:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PwaW7JRfkg2Q5KKUNVzg/WW9DNNysT3PVbxSJWsPSXg=; b=UatcTCrS5N7oQ2y78QP3HdyTNmmTz15jSyAC2IMZ9hkwrwIiC4lgukQismBMfocrl7 yxXqVzw/1sIT3sbt335ZT4SUT1fYNT2dwrSFYhkoyNreRkFNwsMPAwfHunTIQu9lHaaz 1Jnim7nkY3TGQAuShwzQ1IXs1Gp8oDPqfHPNwOvVr5bmjM4r8zmvERpU/f/AWrDZd+hS 1kKx3CZZbmMjkvzbJDA6h3KBq5eimp588mGPsux2gccEJQpvZxd54diaILGKmZZF/QzW BCC98dbnIMWB626CIA8ZAWJjtHWTJZWzEjNCxYL8pM10HvD8/PNYWfIQXe27si7fznP1 xHzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PwaW7JRfkg2Q5KKUNVzg/WW9DNNysT3PVbxSJWsPSXg=; b=pZJG1j/7plv4KCme1sngeJ8QSzmTtECMSqDzdFveZbaAP6OMBp5C/M6S2GU6FMFYf5 wKE31RB5FpRR6InOymZE14pKaF6L+MKq+OSB1XvNLFEjW78nw6BMV9FFe2VP5/S8baq7 SqyCmlaqkcBQDSUujShYXu4eqiTKCjz5fmgc6xnrqSPQGbfglULzvQBaG50nfnDPbYKC D+XhzORZljz8k87ydUefNOLjlPs5IcWjEpq72LbHYFJwuTnoBTZ+F3VSwui+GKBnq3Rl TSTXc6HO4vRe9D/d6OM/IO1Z+GpafPwgcd7J37y2JvJeb/pswtHqywMl07qlJf1XVxEk XuYA== X-Gm-Message-State: AOAM533SLkNTNBa2YScq88cIqR5Gadiy2FA1AJwqoIuApP8cFmuHQxz0 I6+90K1iHhzPPtDQuPpvJqCvE42+CTw= X-Google-Smtp-Source: ABdhPJw0/V1UJd/o+YFUm4pAAphEB+/pIqt9VfxkC0tuTsS8zLODNECTdi16yGwvOzP1YID702tryA== X-Received: by 2002:a17:906:f74f:: with SMTP id jp15mr5118428ejb.423.1631782174458; Thu, 16 Sep 2021 01:49:34 -0700 (PDT) Received: from localhost.localdomain (catv-176-63-0-115.catv.broadband.hu. [176.63.0.115]) by smtp.googlemail.com with ESMTPSA id dh16sm1085838edb.63.2021.09.16.01.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 01:49:34 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com Subject: [RFC PATCH 2/3 v2] PCI/ASPM: Remove struct pcie_link_state.acceptable Date: Thu, 16 Sep 2021 10:49:25 +0200 Message-Id: <20210916084926.32614-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210916084926.32614-1-refactormyself@gmail.com> References: <20210916084926.32614-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The acceptable latencies for each device on the bus are calculated within pcie_aspm_cap_init() and cached in struct pcie_link_state.acceptable. They are only used in pcie_aspm_check_latency() to validate actual latencies. Thus, it is possible to avoid caching these values. This patch: - removes `acceptable` from struct pcie_link_state - calculates the acceptable latency for each device directly - removes the calculations done within pcie_aspm_cap_init() Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 9e85dfc56657..0c0c055823f1 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -65,12 +65,6 @@ struct pcie_link_state { u32 clkpm_enabled:1; /* Current Clock PM state */ u32 clkpm_default:1; /* Default Clock PM state by BIOS */ u32 clkpm_disable:1; /* Clock PM disabled */ - - /* - * Endpoint acceptable latencies. A pcie downstream port only - * has one slot under it, so at most there are 8 functions. - */ - struct aspm_latency acceptable[8]; }; static int aspm_disabled, aspm_force; @@ -389,7 +383,7 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; struct pci_dev *downstream; struct aspm_latency latency_up, latency_dw; struct aspm_latency *acceptable; @@ -402,7 +396,13 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) link = endpoint->bus->self->link_state; downstream = pci_function_0(link->pdev->subordinate); - acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; + pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); + /* Calculate endpoint L0s acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; + acceptable->l0s = calc_l0s_acceptable(encoding); + /* Calculate endpoint L1 acceptable latency */ + encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; + acceptable->l1 = calc_l1_acceptable(encoding); while (link) { /* Read direction exit latencies */ @@ -664,22 +664,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - u32 reg32, encoding; - struct aspm_latency *acceptable = - &link->acceptable[PCI_FUNC(child->devfn)]; if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue; - pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); - /* Calculate endpoint L0s acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); - /* Calculate endpoint L1 acceptable latency */ - encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); - pcie_aspm_check_latency(child); } } From patchwork Thu Sep 16 08:49:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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[176.63.0.115]) by smtp.googlemail.com with ESMTPSA id dh16sm1085838edb.63.2021.09.16.01.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 01:49:34 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com Subject: [RFC PATCH 3/3 v1] PCI/ASPM: Remove struct aspm_latency Date: Thu, 16 Sep 2021 10:49:26 +0200 Message-Id: <20210916084926.32614-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210916084926.32614-1-refactormyself@gmail.com> References: <20210916084926.32614-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The struct aspm_latency is now used only inside pcie_aspm_check_latency(). Since this struct is trivial, this patch: - replaces struct aspm_latency variables with u32 variables - removes struct aspm_latency Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 0c0c055823f1..8093c9335e1f 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -41,11 +41,6 @@ #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ ASPM_STATE_L1SS) -struct aspm_latency { - u32 l0s; /* L0s latency (nsec) */ - u32 l1; /* L1 latency (nsec) */ -}; - struct pcie_link_state { struct pci_dev *pdev; /* Upstream component of the Link */ struct pci_dev *downstream; /* Downstream component, function 0 */ @@ -384,9 +379,9 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw, l1_switch_latency = 0; + u32 latency_up_l0s, latency_up_l1, latency_dw_l0s, latency_dw_l1; + u32 acceptable_l0s, acceptable_l1; struct pci_dev *downstream; - struct aspm_latency latency_up, latency_dw; - struct aspm_latency *acceptable; struct pcie_link_state *link; /* Device not in D0 doesn't need latency check */ @@ -399,28 +394,28 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32); /* Calculate endpoint L0s acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; - acceptable->l0s = calc_l0s_acceptable(encoding); + acceptable_l0s = calc_l0s_acceptable(encoding); /* Calculate endpoint L1 acceptable latency */ encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; - acceptable->l1 = calc_l1_acceptable(encoding); + acceptable_l1 = calc_l1_acceptable(encoding); while (link) { /* Read direction exit latencies */ pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, &lnkcap_up); pcie_capability_read_dword(downstream, PCI_EXP_LNKCAP, &lnkcap_dw); - latency_up.l0s = calc_l0s_latency(lnkcap_up); - latency_up.l1 = calc_l1_latency(lnkcap_up); - latency_dw.l0s = calc_l0s_latency(lnkcap_dw); - latency_dw.l1 = calc_l1_latency(lnkcap_dw); + latency_up_l0s = calc_l0s_latency(lnkcap_up); + latency_up_l1 = calc_l1_latency(lnkcap_up); + latency_dw_l0s = calc_l0s_latency(lnkcap_dw); + latency_dw_l1 = calc_l1_latency(lnkcap_dw); /* Check upstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (latency_up.l0s > acceptable->l0s)) + (latency_up_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_UP; /* Check downstream direction L0s latency */ if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (latency_dw.l0s > acceptable->l0s)) + (latency_dw_l0s > acceptable_l0s)) link->aspm_capable &= ~ASPM_STATE_L0S_DW; /* * Check L1 latency. @@ -435,9 +430,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * L1 exit latencies advertised by a device include L1 * substate latencies (and hence do not do any check). */ - latency = max_t(u32, latency_up.l1, latency_dw.l1); + latency = max_t(u32, latency_up_l1, latency_dw_l1); if ((link->aspm_capable & ASPM_STATE_L1) && - (latency + l1_switch_latency > acceptable->l1)) + (latency + l1_switch_latency > acceptable_l1)) link->aspm_capable &= ~ASPM_STATE_L1; l1_switch_latency += 1000; @@ -664,7 +659,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Get and check endpoint acceptable latencies */ list_for_each_entry(child, &linkbus->devices, bus_list) { - if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) continue;