From patchwork Tue Sep 28 08:03:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F197C4332F for ; Tue, 28 Sep 2021 08:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC8E560F9B for ; Tue, 28 Sep 2021 08:04:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239483AbhI1IF7 (ORCPT ); Tue, 28 Sep 2021 04:05:59 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:52695 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239299AbhI1IF3 (ORCPT ); Tue, 28 Sep 2021 04:05:29 -0400 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailnew.west.internal (Postfix) with ESMTP id 69A2F2B01457; Tue, 28 Sep 2021 04:03:39 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 28 Sep 2021 04:03:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=JytbvXDUrvEuY lSDKA4dbMchRQzLLS6KYGETkodTZPc=; b=FT0ljHoZpM6nJZmt6+oyBK9M0U/3Q pTDqmDUACY0BPyjsoVqJ8f5eMB1GK51GJHH08twrWi6xxFXz6J01hluEtLvsb14g xRenKXuiBdirVrUtAYvaMGeJdd6LgJIOQ8DKt0Hc4f4oglnJLPU7coIIfELv42xH grgTxvU0wWRtmMIaN/+EjNjIuQrisEnQbBZDYtLmaj1BJyhIQMrQzfViXJugnwMq Z32+pDOMZL6pLg/HvyJmBVkWZn7SIrtbZ8DFhNoSSgGIpEP5UEV9Pr4FOKOXH9UF XKWBX41/yifxTfiRUw38vd0UVxT69nifj8+JTIFtctmzSSPJuPeMr0vhg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=JytbvXDUrvEuYlSDKA4dbMchRQzLLS6KYGETkodTZPc=; b=fIwBZgg+ np7Y3NzI51tpWPUw/dCs0GgHLglg+7A1sHDn5i1QBNH5B/Gn/HoYm4Xc+VPS6Oc2 xGIXZYEavbN+nwQPX5peLANGO7I/4jwvAvdGWH6hrrqoR/3rE7laSvSmiKxsGnUr +0KqNFnGje4qCngnrY/MWN9bVOJdm+WLeXxIU8WOV5oVSuixt1TFippg+8wZxZJW wBRipGDJ/YEPxZVLYHdnu8QMsXYawsDjkD+3ZeW/4HzQklAeKfU3HttUqY6Qlh0B lXkgJqzqSiDGQDen/hteNZnpnksazGbGl7c4OGLqYIxLVMgn0AZyv8OewaGztdWD uF0KFZWGx9MEVg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudejledguddvfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheej vdfgjeehueeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 28 Sep 2021 04:03:38 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 1/9] dt-bindings: rtc: sun6i: Clean up repetition Date: Tue, 28 Sep 2021 03:03:27 -0500 Message-Id: <20210928080335.36706-2-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org - Use "enum" for compatibles instead of several "const" alternatives. - Merge the H6 clock-output-names minItems/maxItems constraint into the identical block above. Signed-off-by: Samuel Holland Reviewed-by: Rob Herring --- Changes since v1: - New patch. .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 28 ++++++------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index beeb90e55727..a88d46ffb457 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -16,16 +16,17 @@ properties: compatible: oneOf: - - const: allwinner,sun6i-a31-rtc - - const: allwinner,sun8i-a23-rtc - - const: allwinner,sun8i-h3-rtc - - const: allwinner,sun8i-r40-rtc - - const: allwinner,sun8i-v3-rtc - - const: allwinner,sun50i-h5-rtc + - enum: + - allwinner,sun6i-a31-rtc + - allwinner,sun8i-a23-rtc + - allwinner,sun8i-h3-rtc + - allwinner,sun8i-r40-rtc + - allwinner,sun8i-v3-rtc + - allwinner,sun50i-h5-rtc + - allwinner,sun50i-h6-rtc - items: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - - const: allwinner,sun50i-h6-rtc reg: maxItems: 1 @@ -85,18 +86,7 @@ allOf: enum: - allwinner,sun8i-h3-rtc - allwinner,sun50i-h5-rtc - - then: - properties: - clock-output-names: - minItems: 3 - maxItems: 3 - - - if: - properties: - compatible: - contains: - const: allwinner,sun50i-h6-rtc + - allwinner,sun50i-h6-rtc then: properties: From patchwork Tue Sep 28 08:03:28 2021 Content-Type: text/plain; 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Tue, 28 Sep 2021 04:03:40 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 2/9] dt-bindings: rtc: sun6i: Add H616, R329, and D1 support Date: Tue, 28 Sep 2021 03:03:28 -0500 Message-Id: <20210928080335.36706-3-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These new RTC variants all have a single alarm, like the R40 variant. For the new SoCs, start requiring a complete list of input clocks. The H616 has three required clocks. The R329 also has three required clocks (but one is different), plus an optional crystal oscillator input. The D1 RTC is identical to the one in the R329. And since these new SoCs will have a well-defined output clock order as well, they do not need the clock-output-names property. Signed-off-by: Samuel Holland --- Changes since v1: - Properly update the DT binding clocks and clock-names properties. .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 72 ++++++++++++++++++- include/dt-bindings/clock/sun6i-rtc.h | 10 +++ 2 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/clock/sun6i-rtc.h diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index a88d46ffb457..b971510a5ae7 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -24,9 +24,14 @@ properties: - allwinner,sun8i-v3-rtc - allwinner,sun50i-h5-rtc - allwinner,sun50i-h6-rtc + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc - items: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc + - items: + - const: allwinner,sun20i-d1-rtc + - const: allwinner,sun50i-r329-rtc reg: maxItems: 1 @@ -38,7 +43,10 @@ properties: - description: RTC Alarm 1 clocks: - maxItems: 1 + minItems: 1 + + clock-names: + minItems: 1 clock-output-names: minItems: 1 @@ -98,7 +106,66 @@ allOf: properties: compatible: contains: - const: allwinner,sun8i-r40-rtc + const: allwinner,sun50i-h616-rtc + + then: + clocks: + minItems: 3 + maxItems: 3 + items: + - description: Bus clock for register access + - description: 24 MHz oscillator + - description: 32 kHz clock derived from a PLL + + clock-names: + minItems: 3 + minItems: 3 + items: + - const: bus + - const: hosc + - const: pll-32k + + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-r329-rtc + + then: + clocks: + minItems: 3 + maxItems: 4 + items: + - description: AHB parent for internal SPI clock + - description: Bus clock for register access + - description: 24 MHz oscillator + - description: External 32768 Hz oscillator + + clock-names: + minItems: 3 + minItems: 4 + items: + - const: ahb + - const: bus + - const: hosc + - const: ext-osc32k + + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-r40-rtc + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc then: properties: @@ -117,7 +184,6 @@ required: - compatible - reg - interrupts - - clock-output-names additionalProperties: false diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h new file mode 100644 index 000000000000..c845493e4d37 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ +#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ From patchwork Tue Sep 28 08:03:29 2021 Content-Type: text/plain; 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Tue, 28 Sep 2021 04:03:43 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 3/9] clk: sunxi-ng: div: Add macro using CLK_HW_INIT_FW_NAME Date: Tue, 28 Sep 2021 03:03:29 -0500 Message-Id: <20210928080335.36706-4-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To use the external clock references from the device tree, instead of hardcoded global names, parents should be referenced with .fw_name. Add a variant of the SUNXI_CCU_M_WITH_GATE initializer which does this. Signed-off-by: Samuel Holland --- Changes since v1: - None. drivers/clk/sunxi-ng/ccu_div.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 6682fde6043c..4f8c78a4665b 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -166,6 +166,20 @@ struct ccu_div { SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) +#define SUNXI_CCU_M_FW_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, _flags) \ + struct ccu_div _struct = { \ + .enable = _gate, \ + .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_FW_NAME(_name, \ + _parent, \ + &ccu_div_ops, \ + _flags), \ + }, \ + } + static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Tue Sep 28 08:03:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78C28C4332F for ; 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Tue, 28 Sep 2021 04:03:45 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 4/9] clk: sunxi-ng: mux: Add macro using CLK_HW_INIT_PARENTS_DATA Date: Tue, 28 Sep 2021 03:03:30 -0500 Message-Id: <20210928080335.36706-5-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some muxes need the flexibility to specify a combination of internal parents (using .hw) and external parents (using .fw_name). Support this with a version of the SUNXI_CCU_MUX_WITH_GATE macro that uses CLK_HW_INIT_PARENTS_DATA to provide the parent information. Signed-off-by: Samuel Holland --- Changes since v1: - None. drivers/clk/sunxi-ng/ccu_mux.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index e31efc509b3d..f0e3094f29e4 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -72,6 +72,20 @@ struct ccu_mux { SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \ _reg, _shift, _width, 0, _flags) +#define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \ + _shift, _width, _gate, _flags) \ + struct ccu_mux _struct = { \ + .enable = _gate, \ + .mux = _SUNXI_CCU_MUX(_shift, _width), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + } \ + } + static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Tue Sep 28 08:03:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5403CC433EF for ; Tue, 28 Sep 2021 08:04:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38E0961213 for ; Tue, 28 Sep 2021 08:04:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239363AbhI1IGF (ORCPT ); Tue, 28 Sep 2021 04:06:05 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:36755 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239324AbhI1IFa (ORCPT ); Tue, 28 Sep 2021 04:05:30 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id 6EB672B01619; Tue, 28 Sep 2021 04:03:48 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Tue, 28 Sep 2021 04:03:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=QgH4NWp1cwKin oSU/DCR2ZQ5c69368eYkorZC4IC6nA=; b=l7yQfD4Vq8aTGBTn5WQZJl+NLUFpU zLbYv2tZ+C+y4Fq+6/qLQR50CPGZYNIAGDCLtYB37rfTf2HPfG5DJNE3RbkNIbKn 7IcWvH8KpXq7lejQ14Ka4tQI6oyDVj31tbcJVv+2p7WNR+lanAUTaRsIqljUExb/ g9g+030cCC9b68gfGbhjbbOqLAHyqAzarv7JFI67WjZkaklwGR3422vwgGxTP1fg OMNKILVARhSt2F3s80xVK1bHQiki9A3Jaw7+SD3gdqzjvvp5TNt7QMJnAbl6yeTs 80cpBVCuEtzUt3M6yBwe0i5fqvuf3/59HJBHYj1lvwOfwx14bQin1MK4g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=QgH4NWp1cwKinoSU/DCR2ZQ5c69368eYkorZC4IC6nA=; b=OkO4r9kw +Q+RSemvmgeGoD6gOI+jb0RRzFPHYyZXyYvUC2jX2J3DMFmaWwXMx1fzZCwBGMZY dD6wzX0VyWDb0exvt6e72G5gLlQ2kcDb+BnuELTR1q5VHwMUiiecRK8rZZXCOX03 0a8HGpLCWyu5VaMdtrVe5k1yFUniwtdMbQKVKm7IqHUJn8x4Z/Rxcbyr7NRSBqrB nN3OcTlpaqc4kKG48ythFF53NtGpgveS52y/2/zPpIur5+5EB+C26CMdRhKXF3b0 r26Hsb8cvYFchy2uDWBZVJVgCUHsInP09JKaDwPztaK+9oe0EOy0bbOJ+jyC7VDq QnWgZdmTsECOrg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudejledguddvfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheej vdfgjeehueeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 28 Sep 2021 04:03:47 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 5/9] clk: sunxi-ng: mux: Allow muxes to have keys Date: Tue, 28 Sep 2021 03:03:31 -0500 Message-Id: <20210928080335.36706-6-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The muxes in the RTC can only be updated when setting a key field to a specific value. Add a feature flag to denote muxes with this property. Since so far the key value is always the same, it does not need to be provided separately for each mux. Signed-off-by: Samuel Holland --- Changes since v1: - None. drivers/clk/sunxi-ng/ccu_common.h | 1 + drivers/clk/sunxi-ng/ccu_mux.c | 7 +++++++ drivers/clk/sunxi-ng/ccu_mux.h | 14 ++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index 98a1834b58bb..fbf16c6b896d 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -17,6 +17,7 @@ #define CCU_FEATURE_LOCK_REG BIT(5) #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) +#define CCU_FEATURE_KEY_FIELD BIT(8) /* MMC timing mode switch bit */ #define CCU_MMC_NEW_TIMING_MODE BIT(30) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index e8149f3c2324..da5ad4b87440 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -12,6 +12,8 @@ #include "ccu_gate.h" #include "ccu_mux.h" +#define CCU_MUX_KEY_VALUE 0x16aa0000 + static u16 ccu_mux_get_prediv(struct ccu_common *common, struct ccu_mux_internal *cm, int parent_index) @@ -188,6 +190,11 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); + + /* The key field always reads as zero. */ + if (common->features & CCU_FEATURE_KEY_FIELD) + reg |= CCU_MUX_KEY_VALUE; + reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); writel(reg | (index << cm->shift), common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index f0e3094f29e4..1758dcc82ca6 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -86,6 +86,20 @@ struct ccu_mux { } \ } +#define SUNXI_CCU_MUX_HW_WITH_KEY(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct ccu_mux _struct = { \ + .mux = _SUNXI_CCU_MUX(_shift, _width), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_KEY_FIELD, \ + .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + } \ + } + static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Tue Sep 28 08:03:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8200DC43217 for ; Tue, 28 Sep 2021 08:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B6BE61130 for ; Tue, 28 Sep 2021 08:04:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239505AbhI1IGC (ORCPT ); Tue, 28 Sep 2021 04:06:02 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:55223 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239330AbhI1IFa (ORCPT ); Tue, 28 Sep 2021 04:05:30 -0400 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailnew.west.internal (Postfix) with ESMTP id 9AF912B0161B; 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Tue, 28 Sep 2021 04:03:49 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 6/9] rtc: sun6i: Allow probing without an early clock provider Date: Tue, 28 Sep 2021 03:03:32 -0500 Message-Id: <20210928080335.36706-7-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some SoCs have an RTC supported by this RTC driver, but do not have an early clock provider declared here. Currently, this prevents the RTC driver from probing, because it expects a global struct to already be allocated. Fix probing the driver by copying the missing pieces from the clock provider setup function, replacing them with the devm variants. Signed-off-by: Samuel Holland --- Changes since v1: - New patch. (This patch is independent of the rest of the series.) drivers/rtc/rtc-sun6i.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index adec1b14a8de..711832c758ae 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -673,8 +673,17 @@ static int sun6i_rtc_probe(struct platform_device *pdev) struct sun6i_rtc_dev *chip = sun6i_rtc; int ret; - if (!chip) - return -ENODEV; + if (!chip) { + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + spin_lock_init(&chip->lock); + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + } platform_set_drvdata(pdev, chip); From patchwork Tue Sep 28 08:03:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 657CEC4332F for ; Tue, 28 Sep 2021 08:04:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 512AC6120D for ; Tue, 28 Sep 2021 08:04:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239478AbhI1IGG (ORCPT ); Tue, 28 Sep 2021 04:06:06 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:50711 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239341AbhI1IFc (ORCPT ); Tue, 28 Sep 2021 04:05:32 -0400 Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailnew.west.internal (Postfix) with ESMTP id CDE272B0161F; Tue, 28 Sep 2021 04:03:52 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Tue, 28 Sep 2021 04:03:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=SaufLTRKbCSob Q2OUN+vL4Q3M/tZ13OlIGAkrA6LvBQ=; b=TLIFyr9Uts+f5XfcpR1ZhKYY5wHgl f4OT59daNJxM4PBJf/oVI9vM8H2x2nIBLAr04VRqfxgvkxVbqCSg4zh/sSscYCH2 7ZMagFVEScP38fiuHylZnA5NoRPmVJU6jEAKVBPcK5Ndt6fje35M0/eg9+kBPwmx y2gdLZbvZTFrhsPYwKxRDYQwLwMgRIPuJVKv3RSJQ4J5jgHt7JimhJuo5xY00M+o kMRzU7u9Iyruuoiox0OYrF9s/IZtC1cBMSVzB41WDTuwp8SedyL3LZbOgembnXqI i+PiGOUXSWP4vR6wL0Ly8Je6rkkmNAH6MU6o2hgOUHYEIxURxTKXE2qoA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=SaufLTRKbCSobQ2OUN+vL4Q3M/tZ13OlIGAkrA6LvBQ=; b=VSSbnJCw /+2FyKl0D4UDz3+dbkwmF9THFo5J7Tx72mIgYn4eOfr6MvSvsqhr3guUG0su8/CH +wA3K0ZoGayRbc555P6PG/pxTZMjvgXTaALJ4Znt5Lj9elgl00lthCBbouD+6tgy qU7w1cr5z3yoYM/QrEqwlIhiFdwy++W+wEylsU7/2/HBOMPXaxMNuJgTzY8KQq7h b65v8WmwdFUE/TOMwhsB0XCxJmzZiFNh88cUl3RfDQDYVRUeyq2vXJVVWT15qmq3 ZHMM9/vY/FQBWkNP2WDK9Rke+7HZeEs85i+7jMCXihcBmjXo6d+zPqM7F8/IhFC6 VOJp7D9axM6ttw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudejledguddvfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheej vdfgjeehueeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 28 Sep 2021 04:03:51 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 7/9] clk: sunxi-ng: Add support for the sun6i RTC clocks Date: Tue, 28 Sep 2021 03:03:33 -0500 Message-Id: <20210928080335.36706-8-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power domain handles the 24 MHz DCXO (called "HOSC", "dcxo24M", or "osc24M") as well. The H6 also introduces a calibration circuit for IOSC. Later SoCs introduce further variations on the design: - H616 adds an additional mux for the 32 kHz fanout source. - R329 adds an additional mux for the RTC timekeeping clock, a clock for the SPI bus between power domains inside the RTC, and removes the IOSC calibration functionality. Take advantage of the CCU framework to handle this increased complexity. The CCU framework provides pre-made widgets for the mux/gate/divider combinations. And it allows plugging in different clocks for the same specifiers based on the compatible string. This driver is intended to be a drop-in replacement for the existing RTC clock driver. So some runtime adjustment of the clock parents is needed, both to handle hardware differences, and to support the old binding which omitted some of the input clocks. Signed-off-by: Samuel Holland --- Changes since v1: - Rebase on v2 of the module support series. - Load the CCU driver from the RTC driver, not as an OF provider. drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 373 +++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 16 ++ drivers/clk/sunxi-ng/ccu_gate.c | 3 + drivers/rtc/rtc-sun6i.c | 5 + include/linux/clk/sunxi-ng.h | 9 + 7 files changed, 413 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 727ff755eca4..fcbdabf4deae 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -59,6 +59,11 @@ config SUN6I_A31_CCU default MACH_SUN6I depends on MACH_SUN6I || COMPILE_TEST +config SUN6I_RTC_CCU + tristate "Support for the Allwinner H616/R329 RTC CCU" + default ARM64 && ARCH_SUNXI + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST + config SUN8I_A23_CCU tristate "Support for the Allwinner A23 CCU" default MACH_SUN8I diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 659d55150c32..4a326226e78d 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o +obj-$(CONFIG_SUN6I_RTC_CCU) += sun6i-rtc-ccu.o obj-$(CONFIG_SUN8I_A23_CCU) += sun8i-a23-ccu.o obj-$(CONFIG_SUN8I_A33_CCU) += sun8i-a33-ccu.o obj-$(CONFIG_SUN8I_A83T_CCU) += sun8i-a83t-ccu.o @@ -56,6 +57,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o sun6i-a31-ccu-y += ccu-sun6i-a31.o +sun6i-rtc-ccu-y += ccu-sun6i-rtc.o sun8i-a23-ccu-y += ccu-sun8i-a23.o sun8i-a33-ccu-y += ccu-sun8i-a33.o sun8i-a83t-ccu-y += ccu-sun8i-a83t.o diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c new file mode 100644 index 000000000000..7e67466c481d --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2021 Samuel Holland +// + +#include +#include +#include +#include + +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mux.h" + +#include "ccu-sun6i-rtc.h" + +#define IOSC_ACCURACY 300000000 /* 30% */ +#define IOSC_RATE 16000000 + +#define LOSC_RATE 32768 +#define LOSC_RATE_SHIFT 15 + +#define LOSC_CTRL_KEY 0x16aa0000 + +#define IOSC_32K_CLK_DIV_REG 0x8 +#define IOSC_32K_CLK_DIV GENMASK(4, 0) +#define IOSC_32K_PRE_DIV 32 + +#define IOSC_CLK_CALI_REG 0xc +#define IOSC_CLK_CALI_DIV_ONES 22 +#define IOSC_CLK_CALI_EN BIT(1) +#define IOSC_CLK_CALI_SRC_SEL BIT(0) + +#define DCXO_CTRL_REG 0x160 +#define DCXO_CTRL_CLK16M_RC_EN BIT(0) + +struct sun6i_rtc_match_data { + const struct sunxi_ccu_desc *desc; + void (*setup)(void); +}; + +static bool have_iosc_calib; + +static int ccu_iosc_enable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static void ccu_iosc_disable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static int ccu_iosc_is_enabled(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + + if (have_iosc_calib) { + u32 reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* + * Recover the IOSC frequency by shifting the ones place of + * (fixed-point divider * 32768) into bit zero. + */ + if (reg & IOSC_CLK_CALI_EN) + return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT); + } + + return IOSC_RATE; +} + +static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + return IOSC_ACCURACY; +} + +static const struct clk_ops ccu_iosc_ops = { + .enable = ccu_iosc_enable, + .disable = ccu_iosc_disable, + .is_enabled = ccu_iosc_is_enabled, + .recalc_rate = ccu_iosc_recalc_rate, + .recalc_accuracy = ccu_iosc_recalc_accuracy, +}; + +static struct ccu_common iosc_clk = { + .reg = DCXO_CTRL_REG, + .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, + CLK_GET_RATE_NOCACHE), +}; + +static int ccu_iosc_32k_enable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + unsigned long flags; + u32 reg; + + if (!have_iosc_calib) + return 0; + + spin_lock_irqsave(cm->lock, flags); + + reg = readl(cm->base + IOSC_CLK_CALI_REG); + writel(reg | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL, + cm->base + IOSC_CLK_CALI_REG); + + spin_unlock_irqrestore(cm->lock, flags); + + return 0; +} + +static void ccu_iosc_32k_disable(struct clk_hw *hw) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + unsigned long flags; + u32 reg; + + if (!have_iosc_calib) + return; + + spin_lock_irqsave(cm->lock, flags); + + reg = readl(cm->base + IOSC_CLK_CALI_REG); + writel(reg & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL), + cm->base + IOSC_CLK_CALI_REG); + + spin_unlock_irqrestore(cm->lock, flags); +} + +static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + u32 reg; + + if (have_iosc_calib) { + reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (reg & IOSC_CLK_CALI_SRC_SEL) + return LOSC_RATE; + } + + reg = readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV; + + return parent_rate / IOSC_32K_PRE_DIV / (reg + 1); +} + +static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + struct ccu_common *cm = hw_to_ccu_common(hw); + u32 reg; + + if (have_iosc_calib) { + reg = readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (reg & IOSC_CLK_CALI_SRC_SEL) + return 0; + } + + return parent_accuracy; +} + +static const struct clk_ops ccu_iosc_32k_ops = { + .enable = ccu_iosc_32k_enable, + .disable = ccu_iosc_32k_disable, + .recalc_rate = ccu_iosc_32k_recalc_rate, + .recalc_accuracy = ccu_iosc_32k_recalc_accuracy, +}; + +static struct ccu_common iosc_32k_clk = { + .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, + &ccu_iosc_32k_ops, 0), +}; + +/* .fw_name will be nulled out below if the clock-names property is missing. */ +static struct clk_parent_data ext_osc32k[] = { + { .fw_name = "ext-osc32k", .index = 0 } +}; +static SUNXI_CCU_GATE_DATA(ext_osc32k_gate_clk, "ext-osc32k-gate", + ext_osc32k, 0x0, BIT(4), 0); + +static const struct clk_hw *osc32k_parents[] = { &iosc_32k_clk.hw, + &ext_osc32k_gate_clk.common.hw }; +static SUNXI_CCU_MUX_HW_WITH_KEY(osc32k_clk, "osc32k", osc32k_parents, + 0x0, 0, 1, 0); + +/* This falls back to the global name for FW nodes without a hosc reference. */ +static struct clk_parent_data osc24M[] = { + { .fw_name = "hosc", .name = "osc24M" } +}; +static struct ccu_gate osc24M_32k_clk = { + .enable = BIT(16), + .common = { + .reg = 0x60, + .prediv = 750, + .features = CCU_FEATURE_ALL_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M, + &ccu_gate_ops, 0), + }, +}; + +static CLK_FIXED_FACTOR_HW(rtc_32k_fixed_clk, "rtc-32k", + &osc32k_clk.common.hw, 1, 1, 0); + +static const struct clk_hw *rtc_32k_parents[] = { &osc32k_clk.common.hw, + &osc24M_32k_clk.common.hw }; +static SUNXI_CCU_MUX_HW_WITH_KEY(rtc_32k_mux_clk, "rtc-32k", rtc_32k_parents, + 0x0, 1, 1, 0); + +static struct clk_parent_data osc32k_fanout_parents[] = { + { .hw = &osc32k_clk.common.hw }, + /* This parent is replaced below for some hardware variants. */ + { .fw_name = "pll-32k" }, + { .hw = &osc24M_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", + osc32k_fanout_parents, + 0x60, 1, 2, BIT(0), 0); + +static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", + 0x310, 0, 5, BIT(31), 0); + +static struct ccu_common *sun50i_h616_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &osc32k_fanout_clk.common, +}; + +static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &rtc_32k_mux_clk.common, + &osc32k_fanout_clk.common, + &rtc_spi_clk.common, +}; + +static struct clk_hw_onecell_data sun50i_h616_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = NULL, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_fixed_clk.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + +static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_mux_clk.common.hw, + [CLK_RTC_SPI] = &rtc_spi_clk.common.hw, + }, +}; + +static const struct sunxi_ccu_desc sun50i_h616_rtc_ccu_desc = { + .ccu_clks = sun50i_h616_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_rtc_ccu_clks), + + .hw_clks = &sun50i_h616_rtc_ccu_hw_clks, +}; + +static const struct sunxi_ccu_desc sun50i_r329_rtc_ccu_desc = { + .ccu_clks = sun50i_r329_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_r329_rtc_ccu_clks), + + .hw_clks = &sun50i_r329_rtc_ccu_hw_clks, +}; + +static void sun50i_h616_rtc_ccu_setup(void) +{ + have_iosc_calib = 1; + + /* Remove the second parent as external osc32k is not supported. */ + osc32k_parents[1] = osc32k_parents[0]; +} + +static void sun50i_r329_rtc_ccu_setup(void) +{ + have_iosc_calib = 0; + + osc32k_fanout_parents[1] = (struct clk_parent_data) { + .hw = &ext_osc32k_gate_clk.common.hw + }; +} + +static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = { + .desc = &sun50i_h616_rtc_ccu_desc, + .setup = sun50i_h616_rtc_ccu_setup, +}; + +static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = { + .desc = &sun50i_r329_rtc_ccu_desc, + .setup = sun50i_r329_rtc_ccu_setup, +}; + +static const struct of_device_id sun6i_rtc_ccu_match[] = { + { + .compatible = "allwinner,sun50i-h616-rtc", + .data = &sun50i_h616_rtc_ccu_data, + }, + { + .compatible = "allwinner,sun50i-r329-rtc", + .data = &sun50i_r329_rtc_ccu_data, + }, +}; + +int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) +{ + struct device_node *node = dev->of_node; + const struct sun6i_rtc_match_data *data; + const struct of_device_id *match; + int i; + + match = of_match_device(sun6i_rtc_ccu_match, dev); + if (!match) + return 0; + + data = match->data; + + /* ext-osc32k was the only input clock in the old binding. */ + if (!of_property_read_bool(node, "clock-names")) + ext_osc32k[0].fw_name = NULL; + + /* Rename the first 3 clocks to respect clock-output-names. */ + for (i = CLK_OSC32K; i <= CLK_IOSC; ++i) { + struct clk_init_data *init = (struct clk_init_data *) + data->desc->hw_clks->hws[i]->init; + + of_property_read_string_index(node, "clock-output-names", i, + &init->name); + } + + data->setup(); + + return devm_sunxi_ccu_probe(dev, reg, data->desc); +} + +MODULE_IMPORT_NS(SUNXI_CCU); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h new file mode 100644 index 000000000000..5c91dc1fb3eb --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _CCU_SUN6I_RTC_H +#define _CCU_SUN6I_RTC_H + +#include + +#define CLK_IOSC_32K 4 +#define CLK_EXT_OSC32K_GATE 5 +#define CLK_OSC24M_32K 6 +#define CLK_RTC_32K 7 +#define CLK_RTC_SPI 8 + +#define CLK_NUMBER (CLK_RTC_SPI + 1) + +#endif /* _CCU_SUN6I_RTC_H */ diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_gate.c index b77288f44118..a2115a21807d 100644 --- a/drivers/clk/sunxi-ng/ccu_gate.c +++ b/drivers/clk/sunxi-ng/ccu_gate.c @@ -24,6 +24,7 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate) spin_unlock_irqrestore(common->lock, flags); } +EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_disable, SUNXI_CCU); static void ccu_gate_disable(struct clk_hw *hw) { @@ -49,6 +50,7 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate) return 0; } +EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_enable, SUNXI_CCU); static int ccu_gate_enable(struct clk_hw *hw) { @@ -64,6 +66,7 @@ int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate) return readl(common->base + common->reg) & gate; } +EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_is_enabled, SUNXI_CCU); static int ccu_gate_is_enabled(struct clk_hw *hw) { diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 711832c758ae..079c7c8f3b54 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -683,6 +684,10 @@ static int sun6i_rtc_probe(struct platform_device *pdev) chip->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chip->base)) return PTR_ERR(chip->base); + + ret = sun6i_rtc_ccu_probe(&pdev->dev, chip->base); + if (ret) + return ret; } platform_set_drvdata(pdev, chip); diff --git a/include/linux/clk/sunxi-ng.h b/include/linux/clk/sunxi-ng.h index cf32123b39f5..0630298686ee 100644 --- a/include/linux/clk/sunxi-ng.h +++ b/include/linux/clk/sunxi-ng.h @@ -9,4 +9,13 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode); int sunxi_ccu_get_mmc_timing_mode(struct clk *clk); +#ifdef CONFIG_SUN6I_RTC_CCU +int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg); +#else +static inline int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) +{ + return 0; +} +#endif + #endif From patchwork Tue Sep 28 08:03:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A856C4707E for ; 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Tue, 28 Sep 2021 04:03:54 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 8/9] [DO NOT MERGE] clk: sunxi-ng: sun6i-rtc: Add support for H6 Date: Tue, 28 Sep 2021 03:03:34 -0500 Message-Id: <20210928080335.36706-9-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org H6 has IOSC calibration and an ext-osc32k input. H6 has the osc32k mux and the rtc-32k mux, but no fanout mux. Signed-off-by: Samuel Holland --- Changes since v1: - Rebase. - Add a new non-mux "osc32k-fanout" clock instead of changing the number of parents in osc32k_fanout_clk. drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 49 ++++++++++++++++++++++++++++ drivers/rtc/rtc-sun6i.c | 17 ---------- 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c index 7e67466c481d..f742f6569f6c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -234,9 +234,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", osc32k_fanout_parents, 0x60, 1, 2, BIT(0), 0); +static SUNXI_CCU_GATE_HW(osc32k_fanout_gate_clk, "osc32k-fanout", + &osc32k_clk.common.hw, 0x60, BIT(0), 0); + static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", 0x310, 0, 5, BIT(31), 0); +static struct ccu_common *sun50i_h6_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &rtc_32k_mux_clk.common, + &osc32k_fanout_gate_clk.common, +}; + static struct ccu_common *sun50i_h616_rtc_ccu_clks[] = { &iosc_clk, &iosc_32k_clk, @@ -256,6 +269,21 @@ static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { &rtc_spi_clk.common, }; +static struct clk_hw_onecell_data sun50i_h6_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_gate_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_mux_clk.common.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + static struct clk_hw_onecell_data sun50i_h616_rtc_ccu_hw_clks = { .num = CLK_NUMBER, .hws = { @@ -286,6 +314,13 @@ static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { }, }; +static const struct sunxi_ccu_desc sun50i_h6_rtc_ccu_desc = { + .ccu_clks = sun50i_h6_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_rtc_ccu_clks), + + .hw_clks = &sun50i_h6_rtc_ccu_hw_clks, +}; + static const struct sunxi_ccu_desc sun50i_h616_rtc_ccu_desc = { .ccu_clks = sun50i_h616_rtc_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h616_rtc_ccu_clks), @@ -300,6 +335,11 @@ static const struct sunxi_ccu_desc sun50i_r329_rtc_ccu_desc = { .hw_clks = &sun50i_r329_rtc_ccu_hw_clks, }; +static void sun50i_h6_rtc_ccu_setup(void) +{ + have_iosc_calib = 1; +} + static void sun50i_h616_rtc_ccu_setup(void) { have_iosc_calib = 1; @@ -317,6 +357,11 @@ static void sun50i_r329_rtc_ccu_setup(void) }; } +static const struct sun6i_rtc_match_data sun50i_h6_rtc_ccu_data = { + .desc = &sun50i_h6_rtc_ccu_desc, + .setup = sun50i_h6_rtc_ccu_setup, +}; + static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = { .desc = &sun50i_h616_rtc_ccu_desc, .setup = sun50i_h616_rtc_ccu_setup, @@ -328,6 +373,10 @@ static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = { }; static const struct of_device_id sun6i_rtc_ccu_match[] = { + { + .compatible = "allwinner,sun50i-h6-rtc", + .data = &sun50i_h6_rtc_ccu_data, + }, { .compatible = "allwinner,sun50i-h616-rtc", .data = &sun50i_h616_rtc_ccu_data, diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 079c7c8f3b54..727b34a6e44d 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -364,23 +364,6 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", sun8i_h3_rtc_clk_init); -static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { - .rc_osc_rate = 16000000, - .fixed_prescaler = 32, - .has_prescaler = 1, - .has_out_clk = 1, - .export_iosc = 1, - .has_losc_en = 1, - .has_auto_swt = 1, -}; - -static void __init sun50i_h6_rtc_clk_init(struct device_node *node) -{ - sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); -} -CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", - sun50i_h6_rtc_clk_init); - /* * The R40 user manual is self-conflicting on whether the prescaler is * fixed or configurable. The clock diagram shows it as fixed, but there From patchwork Tue Sep 28 08:03:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12522053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AF56C4167D for ; Tue, 28 Sep 2021 08:04:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8748660F9B for ; Tue, 28 Sep 2021 08:04:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239432AbhI1IGI (ORCPT ); Tue, 28 Sep 2021 04:06:08 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:59529 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239372AbhI1IFh (ORCPT ); Tue, 28 Sep 2021 04:05:37 -0400 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailnew.west.internal (Postfix) with ESMTP id 2E50F2B01620; Tue, 28 Sep 2021 04:03:57 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Tue, 28 Sep 2021 04:03:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=MZr1ROPsa7huk ZlSBuo6Lot+29g5/AyZ+XRVJeB1+z0=; b=uE/MuVjV8S+Y5a7yePJbasPwcE/uY 1T26aIR1rxCiWu5feWUc+7e76u6EGYlwPwEvSbR1upjFnq7QeNBxMEs/hirHpggS rVVO3xcvHfWoGOwbBA86XTRHoBAddX7n0Pwcg7iQ4LW9erTb16A5r6ae+zPGdp5m N+U1M99CFgpzOV3uE69IoFuACjIfRRKcTKJ8qMr98dr5xmxgjbgtWH0CJuIn3hsz pKRq2whWz1lV7OEhTHdZjYeQijiLI4lgYYf7x5DtF84ODTFPVbUH34P1bB0hXVEf jyG5TPMaTwNntnk2DFdKATPJqeuyE4L7YXobSg9Ids7mRLFMgh3Sv8QoQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=MZr1ROPsa7hukZlSBuo6Lot+29g5/AyZ+XRVJeB1+z0=; b=QDH/DdCA OyRWaJABYJaWLRlwsGkbGakKqlJDi+6QtosbTMOLOG/O70T4pCuN42eyM1dQRT2I WMupQSPEU2pvGCmOKh22J5uXZM/MAcdQesnCDFMLfDSMs1ix2C/y1iJ6mG8HrrGA ucyxuMrdfWgmvTLxbl0j6IgPXVUMzyop9jniJdnZuRhAPWS8pu0+elGyWn9c9/Qa qwP1g5EpxkuBSq18j5p68aPV1FoucSdvHeEUuuJG0by8phR62UfQNE0CaMWbMPpH Nq90qXo/q96nQGI+CKJPYRc+Lhu00odvJ5slb5VP4ILDZNw7egyVUWqcOYfSzwvL rLFiCVREhd2M4g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudejledguddvfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheej vdfgjeehueeinecuvehluhhsthgvrhfuihiivgepvdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 28 Sep 2021 04:03:56 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 9/9] [DO NOT MERGE] clk: sunxi-ng: sun6i-rtc: Add support for T5 Date: Tue, 28 Sep 2021 03:03:35 -0500 Message-Id: <20210928080335.36706-10-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210928080335.36706-1-samuel@sholland.org> References: <20210928080335.36706-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The T5 RTC is similar to the H616 RTC (no rtc-32k mux, pll-32k as the second fanout input), except that it adds the ext-osc32k input. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c index f742f6569f6c..88946c990b61 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -240,6 +240,15 @@ static SUNXI_CCU_GATE_HW(osc32k_fanout_gate_clk, "osc32k-fanout", static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", 0x310, 0, 5, BIT(31), 0); +static struct ccu_common *sun8i_t5_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &osc32k_fanout_clk.common, +}; + static struct ccu_common *sun50i_h6_rtc_ccu_clks[] = { &iosc_clk, &iosc_32k_clk, @@ -269,6 +278,21 @@ static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { &rtc_spi_clk.common, }; +static struct clk_hw_onecell_data sun8i_t5_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_fixed_clk.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + static struct clk_hw_onecell_data sun50i_h6_rtc_ccu_hw_clks = { .num = CLK_NUMBER, .hws = { @@ -314,6 +338,13 @@ static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { }, }; +static const struct sunxi_ccu_desc sun8i_t5_rtc_ccu_desc = { + .ccu_clks = sun8i_t5_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_t5_rtc_ccu_clks), + + .hw_clks = &sun8i_t5_rtc_ccu_hw_clks, +}; + static const struct sunxi_ccu_desc sun50i_h6_rtc_ccu_desc = { .ccu_clks = sun50i_h6_rtc_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_rtc_ccu_clks), @@ -335,6 +366,11 @@ static const struct sunxi_ccu_desc sun50i_r329_rtc_ccu_desc = { .hw_clks = &sun50i_r329_rtc_ccu_hw_clks, }; +static void sun8i_t5_rtc_ccu_setup(void) +{ + have_iosc_calib = 1; +} + static void sun50i_h6_rtc_ccu_setup(void) { have_iosc_calib = 1; @@ -357,6 +393,11 @@ static void sun50i_r329_rtc_ccu_setup(void) }; } +static const struct sun6i_rtc_match_data sun8i_t5_rtc_ccu_data = { + .desc = &sun8i_t5_rtc_ccu_desc, + .setup = sun8i_t5_rtc_ccu_setup, +}; + static const struct sun6i_rtc_match_data sun50i_h6_rtc_ccu_data = { .desc = &sun50i_h6_rtc_ccu_desc, .setup = sun50i_h6_rtc_ccu_setup, @@ -373,6 +414,10 @@ static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = { }; static const struct of_device_id sun6i_rtc_ccu_match[] = { + { + .compatible = "allwinner,sun8i-t5-rtc", + .data = &sun8i_t5_rtc_ccu_data, + }, { .compatible = "allwinner,sun50i-h6-rtc", .data = &sun50i_h6_rtc_ccu_data,