From patchwork Tue Sep 28 16:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12523181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 124E0C433F5 for ; Tue, 28 Sep 2021 16:04:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EAD866135E for ; Tue, 28 Sep 2021 16:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241824AbhI1QGL (ORCPT ); Tue, 28 Sep 2021 12:06:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:47478 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241821AbhI1QGJ (ORCPT ); Tue, 28 Sep 2021 12:06:09 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 27AD96128B; Tue, 28 Sep 2021 16:04:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632845069; bh=P4ZkEtDSPnIoXB1tLW1afhZpMp6qUuz4Ha6J4mMMF+Y=; h=From:To:Cc:Subject:Date:From; b=JEMBpoTvyDv5hbAmUzjdFRvle5ut7iUoFzOHkhk9cLW4vNmZvBUwYQZIhFFFIxPoZ DrcGaz6X8a31DTkv4uSfQYfq2qlgkPXiwAMAQeBPGQVvlhw+6gdLEFI+ktJwRhO77F 9j7ghfylIAJlJVcJ3YXNAw+hk4NllNHhAF2ZRR3Mv8VRIUly//K/tofo8tWAgRpnaw /9VTJYVaSKNq2ZzpHuP5qPTjDqTojSTS8hFjFQYCF1Z5POmR0tpQguZxNsrcw17/JS /ikU92qwTfrim3IZa0WGPu4gASsm0xbxf2pgeom6gBJl/b25ADUTHWNC9ZRp8vsn9G n6bXosMPiHzaQ== From: Dinh Nguyen To: michal.simek@xilinx.com Cc: dinguyen@kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rric@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [PATCHv3 1/3] EDAC/synopsys: use the quirk for version instead of ddr version Date: Tue, 28 Sep 2021 11:04:21 -0500 Message-Id: <20210928160423.271187-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Version 2.40a supports DDR_ECC_INTR_SUPPORT for a quirk, so use that quirk to determine a call to setup_address_map(). Signed-off-by: Dinh Nguyen Reviewed-by: Michal Simek --- v3: new patch --- drivers/edac/synopsys_edac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 7e7146b22c16..bf237fccb444 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1352,8 +1352,7 @@ static int mc_probe(struct platform_device *pdev) } } - if (of_device_is_compatible(pdev->dev.of_node, - "xlnx,zynqmp-ddrc-2.40a")) + if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) setup_address_map(priv); #endif From patchwork Tue Sep 28 16:04:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12523179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C44C433EF for ; Tue, 28 Sep 2021 16:04:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FFC661354 for ; Tue, 28 Sep 2021 16:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241810AbhI1QGL (ORCPT ); Tue, 28 Sep 2021 12:06:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:47508 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241825AbhI1QGJ (ORCPT ); Tue, 28 Sep 2021 12:06:09 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 405076128E; Tue, 28 Sep 2021 16:04:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632845070; bh=01wz6erCakbXSf2MOUj5I3H7r0o1qQPsOzBsFvpd0uE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EUS18fCmOq0in3hvpKrWA84T6wNO8t+f/UE0xjgCEvVLjrKHlWgErtSDuy2KfxaDA NW1orpik6JsIDvaVl98XKp9f9h1xIIBOWb306jthQ4CApK2w9oP0EX2KocJ/N/jblf e1PHvA5xK1L1N56FP5yPD00kGe/Uit8cz81u+Bs2H85F7SeLQwBhC/3FYV20cgzA+k NrnzUZGDXcMNNIq2yhJSwexYGgDImo6UuSrqKejKEYwWwCr89SNbPkiFBkab73NJut XFX5gTAaFdXvnoUuaJcLRZUwytAhcwK4i88NeHs7K7DAqzg2iQUbBkaZ3Okk+dL5a+ 0O8pWobAkHeGA== From: Dinh Nguyen To: michal.simek@xilinx.com Cc: dinguyen@kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rric@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [PATCHv3 2/3] EDAC/synopsys: add support for version 3 of the Synopsys EDAC DDR Date: Tue, 28 Sep 2021 11:04:22 -0500 Message-Id: <20210928160423.271187-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210928160423.271187-1-dinguyen@kernel.org> References: <20210928160423.271187-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Adds support for version 3.80a of the Synopsys DDR controller with EDAC. This version of the controller has the following differences: - UE/CE are auto cleared - Interrupts are supported by default Signed-off-by: Dinh Nguyen Reviewed-by: Michal Simek --- v3: Address comments from Michal Simek use bit macro removed extra "cleared" word from comment section about v3.0 v2: remove "This patch" from commit message --- drivers/edac/synopsys_edac.c | 49 ++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index bf237fccb444..66ee37ea0acc 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -101,6 +101,7 @@ /* DDR ECC Quirks */ #define DDR_ECC_INTR_SUPPORT BIT(0) #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) +#define DDR_ECC_INTR_SELF_CLEAR BIT(2) /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */ /* ECC Configuration Registers */ @@ -171,6 +172,10 @@ #define DDR_QOS_IRQ_EN_OFST 0x20208 #define DDR_QOS_IRQ_DB_OFST 0x2020C +/* DDR QOS Interrupt register definitions */ +#define DDR_UE_MASK BIT(9) +#define DDR_CE_MASK BIT(8) + /* ECC Corrected Error Register Mask and Shifts*/ #define ECC_CEADDR0_RW_MASK 0x3FFFF #define ECC_CEADDR0_RNK_MASK BIT(24) @@ -533,10 +538,16 @@ static irqreturn_t intr_handler(int irq, void *dev_id) priv = mci->pvt_info; p_data = priv->p_data; - regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); - regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); - if (!(regval & ECC_CE_UE_INTR_MASK)) - return IRQ_NONE; + /* + * v3.0 of the controller has the ce/ue bits cleared automatically, + * so this condition does not apply. + */ + if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { + regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); + regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); + if (!(regval & ECC_CE_UE_INTR_MASK)) + return IRQ_NONE; + } status = p_data->get_error_info(priv); if (status) @@ -548,7 +559,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id) edac_dbg(3, "Total error count CE %d UE %d\n", priv->ce_cnt, priv->ue_cnt); - writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); + /* v3.0 of the controller does not have this register */ + if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) + writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); return IRQ_HANDLED; } @@ -834,8 +847,13 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) static void enable_intr(struct synps_edac_priv *priv) { /* Enable UE/CE Interrupts */ - writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, - priv->baseaddr + DDR_QOS_IRQ_EN_OFST); + if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) + writel(DDR_UE_MASK | DDR_CE_MASK, + priv->baseaddr + ECC_CLR_OFST); + else + writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, + priv->baseaddr + DDR_QOS_IRQ_EN_OFST); + } static void disable_intr(struct synps_edac_priv *priv) @@ -890,6 +908,19 @@ static const struct synps_platform_data zynqmp_edac_def = { ), }; +static const struct synps_platform_data synopsys_edac_def = { + .get_error_info = zynqmp_get_error_info, + .get_mtype = zynqmp_get_mtype, + .get_dtype = zynqmp_get_dtype, + .get_ecc_state = zynqmp_get_ecc_state, + .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR +#ifdef CONFIG_EDAC_DEBUG + | DDR_ECC_DATA_POISON_SUPPORT +#endif + ), +}; + + static const struct of_device_id synps_edac_match[] = { { .compatible = "xlnx,zynq-ddrc-a05", @@ -899,6 +930,10 @@ static const struct of_device_id synps_edac_match[] = { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = (void *)&zynqmp_edac_def }, + { + .compatible = "snps,ddrc-3.80a", + .data = (void *)&synopsys_edac_def + }, { /* end of table */ } From patchwork Tue Sep 28 16:04:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12523183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C37AFC4332F for ; Tue, 28 Sep 2021 16:04:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A73286135A for ; Tue, 28 Sep 2021 16:04:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241818AbhI1QGL (ORCPT ); Tue, 28 Sep 2021 12:06:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:47532 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241832AbhI1QGK (ORCPT ); Tue, 28 Sep 2021 12:06:10 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6F08661357; Tue, 28 Sep 2021 16:04:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632845071; bh=Fq/JqCT+osi1O4JBR74Hu4wp20lUJtI7S1DtsM/0L1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a+x9v2lo/9dHvyvqQT88lVO1mNqd4esG6DbliMXAYLlo6waE7w2fZnd8balFyWRJ+ lvFqdco7E0buebBtGf5NIa/+puge62/k1KYZV8zFMjX7cR97T68iyQkPTiZ/1uXK2s 1PWc6dIl8LoOjLhhhTaK5pjRdVfiTvs4sV65j6yBhgXqM95u+sKxrMTZdCo3iKT5x7 5lMGdvpIUtH+z1KdyFE3BcD9+fs0ZKHU3aEoQFCSCMcyWL6SJ69ZS63ylHXR5BvYM0 kTEL9vk342Q9o7VKwQBfy4YA0NZMzpqitzMyg0mOopMJhLmePuMWWQDA1fZUuiwUth 2do87/vz2mKPA== From: Dinh Nguyen To: michal.simek@xilinx.com Cc: dinguyen@kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rric@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [PATCHv3 3/3] EDAC/synopsys: v3.80a of the synopsys edac contoller is also on the N5X Date: Tue, 28 Sep 2021 11:04:23 -0500 Message-Id: <20210928160423.271187-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210928160423.271187-1-dinguyen@kernel.org> References: <20210928160423.271187-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Intel's N5X platform is also using the Synopsys EDAC controller. Signed-off-by: Dinh Nguyen Acked-by: Michal Simek --- v3: s/ARCH_N5X/ARCH_INTEL_SOCFPGA v2: no changes --- drivers/edac/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 2fc4c3f91fd5..58ab63642e72 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -484,7 +484,7 @@ config EDAC_ARMADA_XP config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" - depends on ARCH_ZYNQ || ARCH_ZYNQMP + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA help Support for error detection and correction on the Synopsys DDR memory controller.