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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id p14sm1181548ejn.65.2021.09.30.02.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 02:52:31 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: pinctrl: convert rockchip, pinctrl.txt to YAML Date: Thu, 30 Sep 2021 11:52:23 +0200 Message-Id: <20210930095225.9718-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210930_025234_275714_273A1863 X-CRM114-Status: GOOD ( 21.19 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Convert rockchip,pinctrl.txt to YAML Signed-off-by: Johan Jonker --- Changed V2: Add '|' to maintain the paragraphs. Change gpio patternProperties. Move description to items. Remove type array. Restyle --- .../bindings/pinctrl/rockchip,pinctrl.txt | 114 ------------ .../bindings/pinctrl/rockchip,pinctrl.yaml | 176 ++++++++++++++++++ 2 files changed, 176 insertions(+), 114 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 84c411129..000000000 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: should be - "rockchip,px30-pinctrl": for Rockchip PX30 - "rockchip,rv1108-pinctrl": for Rockchip RV1108 - "rockchip,rk2928-pinctrl": for Rockchip RK2928 - "rockchip,rk3066a-pinctrl": for Rockchip RK3066a - "rockchip,rk3066b-pinctrl": for Rockchip RK3066b - "rockchip,rk3128-pinctrl": for Rockchip RK3128 - "rockchip,rk3188-pinctrl": for Rockchip RK3188 - "rockchip,rk3228-pinctrl": for Rockchip RK3228 - "rockchip,rk3288-pinctrl": for Rockchip RK3288 - "rockchip,rk3308-pinctrl": for Rockchip RK3308 - "rockchip,rk3328-pinctrl": for Rockchip RK3328 - "rockchip,rk3368-pinctrl": for Rockchip RK3368 - "rockchip,rk3399-pinctrl": for Rockchip RK3399 - "rockchip,rk3568-pinctrl": for Rockchip RK3568 - - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. On the rk3368 this should - point to the PMUGRF syscon. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: -See rockchip,gpio-bank.yaml - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = . - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml new file mode 100644 index 000000000..01a62245b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pinmux Controller + +maintainers: + - Heiko Stuebner + +description: | + The Rockchip Pinmux Controller enables the IC to share one PAD + to several functional blocks. The sharing is done by multiplexing + the PAD input/output signals. For each PAD there are several muxing + options with option 0 being used as a GPIO. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The Rockchip pin configuration node is a node of a group of pins which can be + used for a specific device or function. This node represents both mux and + config of the pins in that group. The 'pins' selects the function mode + (also named pin mode) this pin can work on and the 'config' configures + various pad settings such as pull-up, etc. + + The pins are grouped into up to 9 individual pin banks which need to be + defined as gpio sub-nodes of the pinmux controller. + +properties: + compatible: + enum: + - rockchip,px30-pinctrl + - rockchip,rk2928-pinctrl + - rockchip,rk3066a-pinctrl + - rockchip,rk3066b-pinctrl + - rockchip,rk3128-pinctrl + - rockchip,rk3188-pinctrl + - rockchip,rk3228-pinctrl + - rockchip,rk3288-pinctrl + - rockchip,rk3308-pinctrl + - rockchip,rk3328-pinctrl + - rockchip,rk3368-pinctrl + - rockchip,rk3399-pinctrl + - rockchip,rk3568-pinctrl + - rockchip,rv1108-pinctrl + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF registers. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the PMU registers, + as some SoCs carry parts of the iomux controller registers there. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + + ranges: true + +patternProperties: + "gpio@[0-9a-f]+$": + type: object + + $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#" + + unevaluatedProperties: false + + "pcfg-[a-z0-9-]+$": + type: object + properties: + bias-disable: true + + bias-pull-down: true + + bias-pull-pin-default: true + + bias-pull-up: true + + drive-strength: + minimum: 0 + maximum: 20 + + input-enable: true + + input-schmitt-enable: true + + output-high: true + + output-low: true + + additionalProperties: false + +additionalProperties: + type: object + additionalProperties: + type: object + properties: + rockchip,pins: + minItems: 1 + items: + items: + - minimum: 0 + maximum: 8 + description: + Pin bank. + - minimum: 0 + maximum: 31 + description: + Pin bank index. + - minimum: 0 + maximum: 6 + description: + Mux 0 means gpio and mux 1 to N means + the specific device function. + - description: + The phandle of a node contains the generic pinconfig options + to use as described in pinctrl-bindings.txt. + +examples: + - | + #include + #include + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + }; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + clocks = <&mux_uart2>; + pinctrl-0 = <&uart2_xfer>; + pinctrl-names = "default"; + reg-io-width = <1>; + reg-shift = <2>; + }; From patchwork Thu Sep 30 09:52:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12527815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C4F3C433EF for ; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id p14sm1181548ejn.65.2021.09.30.02.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 02:52:32 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] ARM: dts: rockchip: change gpio nodenames Date: Thu, 30 Sep 2021 11:52:24 +0200 Message-Id: <20210930095225.9718-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930095225.9718-1-jbx6244@gmail.com> References: <20210930095225.9718-1-jbx6244@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210930_025234_712078_6D058F2F X-CRM114-Status: GOOD ( 11.46 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker Reviewed-by: Linus Walleij --- arch/arm/boot/dts/rk3036.dtsi | 6 +++--- arch/arm/boot/dts/rk3066a.dtsi | 12 ++++++------ arch/arm/boot/dts/rk3188.dtsi | 8 ++++---- arch/arm/boot/dts/rk322x.dtsi | 8 ++++---- arch/arm/boot/dts/rk3288.dtsi | 18 +++++++++--------- arch/arm/boot/dts/rv1108.dtsi | 8 ++++---- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ffa9bc7ed..9d2d44381 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -575,7 +575,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2007c000 { + gpio0: gpio@2007c000 { compatible = "rockchip,gpio-bank"; reg = <0x2007c000 0x100>; interrupts = ; @@ -588,7 +588,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@20080000 { + gpio1: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; @@ -601,7 +601,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@20084000 { + gpio2: gpio@20084000 { compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ae4055428..6688a1a3b 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -273,7 +273,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@20034000 { + gpio0: gpio@20034000 { compatible = "rockchip,gpio-bank"; reg = <0x20034000 0x100>; interrupts = ; @@ -286,7 +286,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@2003c000 { + gpio1: gpio@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; @@ -299,7 +299,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@2003e000 { + gpio2: gpio@2003e000 { compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; @@ -312,7 +312,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@20080000 { + gpio3: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; @@ -325,7 +325,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio4@20084000 { + gpio4: gpio@20084000 { compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; @@ -338,7 +338,7 @@ #interrupt-cells = <2>; }; - gpio6: gpio6@2000a000 { + gpio6: gpio@2000a000 { compatible = "rockchip,gpio-bank"; reg = <0x2000a000 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2c606494b..3e5786e07 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -223,7 +223,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2000a000 { + gpio0: gpio@2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = ; @@ -236,7 +236,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@2003c000 { + gpio1: gpio@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; @@ -249,7 +249,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@2003e000 { + gpio2: gpio@2003e000 { compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; @@ -262,7 +262,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@20080000 { + gpio3: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 75af99c76..3e36cec36 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -946,7 +946,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@11110000 { + gpio0: gpio@11110000 { compatible = "rockchip,gpio-bank"; reg = <0x11110000 0x100>; interrupts = ; @@ -959,7 +959,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@11120000 { + gpio1: gpio@11120000 { compatible = "rockchip,gpio-bank"; reg = <0x11120000 0x100>; interrupts = ; @@ -972,7 +972,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@11130000 { + gpio2: gpio@11130000 { compatible = "rockchip,gpio-bank"; reg = <0x11130000 0x100>; interrupts = ; @@ -985,7 +985,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@11140000 { + gpio3: gpio@11140000 { compatible = "rockchip,gpio-bank"; reg = <0x11140000 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 4dcdcf17c..096f5bb22 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1422,7 +1422,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff750000 { + gpio0: gpio@ff750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff750000 0x0 0x100>; interrupts = ; @@ -1435,7 +1435,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff780000 { + gpio1: gpio@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; interrupts = ; @@ -1448,7 +1448,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff790000 { + gpio2: gpio@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; interrupts = ; @@ -1461,7 +1461,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff7a0000 { + gpio3: gpio@ff7a0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7a0000 0x0 0x100>; interrupts = ; @@ -1474,7 +1474,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio4@ff7b0000 { + gpio4: gpio@ff7b0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7b0000 0x0 0x100>; interrupts = ; @@ -1487,7 +1487,7 @@ #interrupt-cells = <2>; }; - gpio5: gpio5@ff7c0000 { + gpio5: gpio@ff7c0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7c0000 0x0 0x100>; interrupts = ; @@ -1500,7 +1500,7 @@ #interrupt-cells = <2>; }; - gpio6: gpio6@ff7d0000 { + gpio6: gpio@ff7d0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7d0000 0x0 0x100>; interrupts = ; @@ -1513,7 +1513,7 @@ #interrupt-cells = <2>; }; - gpio7: gpio7@ff7e0000 { + gpio7: gpio@ff7e0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7e0000 0x0 0x100>; interrupts = ; @@ -1526,7 +1526,7 @@ #interrupt-cells = <2>; }; - gpio8: gpio8@ff7f0000 { + gpio8: gpio@ff7f0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7f0000 0x0 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 24d56849a..db7166ed8 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -600,7 +600,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@20030000 { + gpio0: gpio@20030000 { compatible = "rockchip,gpio-bank"; reg = <0x20030000 0x100>; interrupts = ; @@ -613,7 +613,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@10310000 { + gpio1: gpio@10310000 { compatible = "rockchip,gpio-bank"; reg = <0x10310000 0x100>; interrupts = ; @@ -626,7 +626,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@10320000 { + gpio2: gpio@10320000 { compatible = "rockchip,gpio-bank"; reg = <0x10320000 0x100>; interrupts = ; @@ -639,7 +639,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@10330000 { + gpio3: gpio@10330000 { compatible = "rockchip,gpio-bank"; reg = <0x10330000 0x100>; interrupts = ; From patchwork Thu Sep 30 09:52:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12527819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B867C433F5 for ; Thu, 30 Sep 2021 09:54:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E3DA61882 for ; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id p14sm1181548ejn.65.2021.09.30.02.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 02:52:33 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: rockchip: change gpio nodenames Date: Thu, 30 Sep 2021 11:52:25 +0200 Message-Id: <20210930095225.9718-3-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930095225.9718-1-jbx6244@gmail.com> References: <20210930095225.9718-1-jbx6244@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210930_025235_715507_CCFED066 X-CRM114-Status: GOOD ( 11.46 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/rockchip/px30.dtsi | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 10 +++++----- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 +++++----- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 64f643145..17a64c3f0 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1297,7 +1297,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff040000 { + gpio0: gpio@ff040000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff040000 0x0 0x100>; interrupts = ; @@ -1309,7 +1309,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff250000 { + gpio1: gpio@ff250000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff250000 0x0 0x100>; interrupts = ; @@ -1321,7 +1321,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff260000 { + gpio2: gpio@ff260000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = ; @@ -1333,7 +1333,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff270000 { + gpio3: gpio@ff270000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff270000 0x0 0x100>; interrupts = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index ce6f4a28d..cec6d179b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -790,7 +790,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff220000 { + gpio0: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = ; @@ -801,7 +801,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff230000 { + gpio1: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = ; @@ -812,7 +812,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff240000 { + gpio2: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = ; @@ -823,7 +823,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff250000 { + gpio3: gpio@ff250000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff250000 0x0 0x100>; interrupts = ; @@ -834,7 +834,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio4@ff260000 { + gpio4: gpio@ff260000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 5b2020590..6edb1a537 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1014,7 +1014,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff210000 { + gpio0: gpio@ff210000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff210000 0x0 0x100>; interrupts = ; @@ -1027,7 +1027,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff220000 { + gpio1: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = ; @@ -1040,7 +1040,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff230000 { + gpio2: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = ; @@ -1053,7 +1053,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff240000 { + gpio3: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 4217897cd..ef6847014 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -797,7 +797,7 @@ #size-cells = <0x2>; ranges; - gpio0: gpio0@ff750000 { + gpio0: gpio@ff750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff750000 0x0 0x100>; clocks = <&cru PCLK_GPIO0>; @@ -810,7 +810,7 @@ #interrupt-cells = <0x2>; }; - gpio1: gpio1@ff780000 { + gpio1: gpio@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO1>; @@ -823,7 +823,7 @@ #interrupt-cells = <0x2>; }; - gpio2: gpio2@ff790000 { + gpio2: gpio@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; @@ -836,7 +836,7 @@ #interrupt-cells = <0x2>; }; - gpio3: gpio3@ff7a0000 { + gpio3: gpio@ff7a0000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff7a0000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 44def886b..577c02047 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1978,7 +1978,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff720000 { + gpio0: gpio@ff720000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; @@ -1991,7 +1991,7 @@ #interrupt-cells = <0x2>; }; - gpio1: gpio1@ff730000 { + gpio1: gpio@ff730000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; @@ -2004,7 +2004,7 @@ #interrupt-cells = <0x2>; }; - gpio2: gpio2@ff780000 { + gpio2: gpio@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; @@ -2017,7 +2017,7 @@ #interrupt-cells = <0x2>; }; - gpio3: gpio3@ff788000 { + gpio3: gpio@ff788000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; @@ -2030,7 +2030,7 @@ #interrupt-cells = <0x2>; }; - gpio4: gpio4@ff790000 { + gpio4: gpio@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>;