From patchwork Mon Oct 4 01:27:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B171C433FE for ; Mon, 4 Oct 2021 01:27:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D8EB6121F for ; Mon, 4 Oct 2021 01:27:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232124AbhJDB3d (ORCPT ); Sun, 3 Oct 2021 21:29:33 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:37615 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232123AbhJDB3c (ORCPT ); Sun, 3 Oct 2021 21:29:32 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id 93F452B0131A; Sun, 3 Oct 2021 21:27:43 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Sun, 03 Oct 2021 21:27:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=K3ztzcGIJRQA2 i14m+NN5p4mb3bayApw/5zcCVEE87c=; b=E2icTyS3WcsTltpWkzopB35ArJL7h 3sqrYi0/6CYeyIayp35p4jnrfyuXO798gPLP8bR5jvEihwPj8CoIS0Ar79yWv8c7 ynoa+4SXtdC2kwftH7n/FEDeea4PIuYInKWn4GjKxlk0wyF6BZ+IulDz49l9KX7m EvlUfBX5EV5BLlesvlLDwo/ja80dm1L1rpY1z2zYFBRTTOiCfKGHIdNH2Uoej8lN GaCxCuDD06OpBnoYDoFBNvARHvMtf2c2uNhZ9mPi96x42Wzk9KEWUyhX6mjdSOD3 FtHKZ4p1MsQykeNl6nQS+CJ9/D3l9+1O8TLczdGY86M7+dYy/hHhzguxw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=K3ztzcGIJRQA2i14m+NN5p4mb3bayApw/5zcCVEE87c=; b=Xxbh9ZUT u76ocYZZ8vRKR/oNxSV8v6gB96eld1/qE+N0A8s9Gu59mb2Dr4EzRNvqNxgmD7t+ YX0ZI847eeUgy6aq37wGTff8o3ssF3woFu/I6zUS5BjhJnVvNrOlokt8IQnhPl7p TXu5QtOJxoXMO6uxLrV99CS/VVDZgZyjK8q9al72zbfBH/wA4IteNYjsawn7LjOB SFlhvchFa+DUkrCuH3ReUTRhndQ1W2BzJVp0I6mrONW5saNvyx5nJYeFBpsQAtlv nimay0TtQB4ZEb/6q0j9tGMO4/gpDjrinUXqjLnI5Q8Cl28x05ejtewNlMWnVvz7 56MHQtbWTdLOBQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudeluddggeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 3 Oct 2021 21:27:42 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 1/6] dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq Date: Sun, 3 Oct 2021 20:27:34 -0500 Message-Id: <20211004012739.39053-2-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The MBUS node needs to reference the CLK_DRAM clock, as the MBUS hardware implements memory dynamic frequency scaling using this clock. Export this clock for SoCs which will be getting a devfreq driver. Signed-off-by: Samuel Holland Acked-by: Rob Herring Reviewed-by: Chanwoo Choi --- drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 2 -- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 2 -- include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +- 4 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h index 54d1f96f4b68..a8c11c0b4e06 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -51,8 +51,6 @@ #define CLK_USB_OHCI1_12M 92 -#define CLK_DRAM 94 - /* All the DRAM gates are exported */ /* And the DSI and GPU module clock is exported */ diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index d8c38447e11b..e13f3c4b57d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -42,8 +42,6 @@ /* The first bunch of module clocks are exported */ -#define CLK_DRAM 96 - /* All the DRAM gates are exported */ /* Some more module clocks are exported */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index 318eb15c414c..175892189e9d 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -113,7 +113,7 @@ #define CLK_USB_OHCI0 91 #define CLK_USB_OHCI1 93 - +#define CLK_DRAM 94 #define CLK_DRAM_VE 95 #define CLK_DRAM_CSI 96 #define CLK_DRAM_DEINTERLACE 97 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index 30d2d15373a2..5d4ada2c22e6 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -126,7 +126,7 @@ #define CLK_USB_OHCI1 93 #define CLK_USB_OHCI2 94 #define CLK_USB_OHCI3 95 - +#define CLK_DRAM 96 #define CLK_DRAM_VE 97 #define CLK_DRAM_CSI 98 #define CLK_DRAM_DEINTERLACE 99 From patchwork Mon Oct 4 01:27:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92B92C433F5 for ; Mon, 4 Oct 2021 01:27:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A17461206 for ; Mon, 4 Oct 2021 01:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232123AbhJDB3g (ORCPT ); Sun, 3 Oct 2021 21:29:36 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:48611 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232128AbhJDB3f (ORCPT ); Sun, 3 Oct 2021 21:29:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id 28B702B01318; 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Sun, 3 Oct 2021 21:27:44 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 2/6] dt-bindings: arm: sunxi: Expand MBUS binding Date: Sun, 3 Oct 2021 20:27:35 -0500 Message-Id: <20211004012739.39053-3-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The MBUS provides more than address translation and bandwidth control. It also provides a PMU to measure bandwidth usage by certain masters, and it provides notification via IRQ when they are active or idle. The MBUS is also tightly integrated with the DRAM controller to provide a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the MBUS binding needs to represent the hardware resources needed for MDFS, which include the clocks and MMIO range of the adjacent DRAM controller. Add the additional resources for the H3 and A64 compatibles, and a new example showing how they are used. Signed-off-by: Samuel Holland Reviewed-by: Chanwoo Choi --- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 75 ++++++++++++++++++- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index e713a6fe4cf7..c1fb404d2fb3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -33,10 +33,33 @@ properties: - allwinner,sun50i-a64-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + items: + - const: "mbus" + - const: "dram" clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + items: + - const: "mbus" + - const: "dram" + - const: "bus" + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -53,13 +76,42 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + +then: + properties: + reg: + minItems: 2 + + clocks: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + clocks: + maxItems: 1 + additionalProperties: false examples: - | - #include + #include + #include - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -69,4 +121,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ... From patchwork Mon Oct 4 01:27:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EACEC433EF for ; Mon, 4 Oct 2021 01:27:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB2256120F for ; Mon, 4 Oct 2021 01:27:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232225AbhJDB3m (ORCPT ); Sun, 3 Oct 2021 21:29:42 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:59493 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232181AbhJDB3i (ORCPT ); Sun, 3 Oct 2021 21:29:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id 74D8F2B0131A; Sun, 3 Oct 2021 21:27:48 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sun, 03 Oct 2021 21:27:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=OSyUKqUS0Bf/W N+jBk7XnzZgBpUsMJ5MFDdoJJnN3Gk=; b=HTf95sgGkUAMGmsoOM6ciHbmn9D8U mkpBo4wMtIJOjqB4zmorpQcRfknjlOIPNw+zUAIMVja1fwaZQ/BdygDxl38nFY57 DVIFO7rdJKTZ68kmuLy6A7FN8+pNSh3EDZjKgNXycPXzT1A65AWGL4VfzUm0bpJD FZ4hhbaPC9sj2b+IQ2ANEisQPKKg7HEXFFSu91teQXgIPCBXlbpalIHuhh5pqO0I OCcvqumnH+GQyL0bUfLhixviQ8YTiZ3rCDycaS3N+OtYmLVIZIPHXbwyoih/tgXQ 92bqrcXPTzyc9oPrvdNdKxMtWCFTYLBUspNt7kCW+ht64mb70cNQ7Rd6g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=OSyUKqUS0Bf/WN+jBk7XnzZgBpUsMJ5MFDdoJJnN3Gk=; b=AheGZcDf sxZtrC3aLh8wqNVpM374jWnlaM0Q4WqOX5uPYP1bcfkr62+o3rcDyNo4I39lxT/e 7Geh5UvAvSWYbyZKQNorvfO1v5On2Kib0bKr1MStZdQDRDY9L+fEmjamg1PRGE+Q yh70PXrrihNkARGNMl5CnwrQ/qHL52k9mkzcQulpDL3SCQFTvZptloGsyhApfK5Y xbqOLdiMQ2z7OGnUD53WGfgd5fGQpI/y9vga0KRCgAHkBR7B0JTboJuTyf8nL3DA Pi4DzMowQALmGJPrljXN2FHPWbGRnjq/+yBZFwQU9zR0b0PVLo6lZxln6FK/NQoE G9ufoCqHbhAY6Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudeluddggeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 3 Oct 2021 21:27:47 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 3/6] dt-bindings: arm: sunxi: Add H5 MBUS compatible Date: Sun, 3 Oct 2021 20:27:36 -0500 Message-Id: <20211004012739.39053-4-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The H5 SoC has a MBUS very similar to the H3 SoC, but it has a smaller MDFS divider range (1-4 instead of 1-16). Add a separate compatible for this variant. Signed-off-by: Samuel Holland Acked-by: Rob Herring --- .../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index c1fb404d2fb3..c070f99e0bb7 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -31,6 +31,7 @@ properties: - allwinner,sun5i-a13-mbus - allwinner,sun8i-h3-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus reg: minItems: 1 @@ -83,6 +84,7 @@ if: enum: - allwinner,sun8i-h3-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus then: properties: From patchwork Mon Oct 4 01:27:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50E9EC433FE for ; Mon, 4 Oct 2021 01:27:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34D0E611C5 for ; Mon, 4 Oct 2021 01:27:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232193AbhJDB3n (ORCPT ); Sun, 3 Oct 2021 21:29:43 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:51803 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232209AbhJDB3k (ORCPT ); Sun, 3 Oct 2021 21:29:40 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id 148192B01318; Sun, 3 Oct 2021 21:27:51 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Sun, 03 Oct 2021 21:27:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=CcvFh4HuzkBSe qWpoXTdQ8k6kPzZDUz8gpq+d2gNRvM=; b=OgtdLOrYTb1jvdd+BaxODyJD7qmP/ Nb6mZBPqpumpvRGcSzI+et6IThys821DduwnNUkmnohlwOod7YaIuQMinj9JzWx8 sJCpqU3+3AmO3DkDrW5YdCwYgYLLJogj6lD1iQwKjMeM0FFeR75XrTEdago3zxql tNH4t6sbXpN3UQ6Nbsm9SvjlNunXtn6zo491aK1joXO8cJN06xzRrWtrxfn96MSD jdEU2s6M6nr9M7wwFu5qSPUSnwxiLkmUX8Bbm51HJXmstX1iIzH4zHa/rrPgFy+q h18eaP1Q2hNWE7KH6CNhsL1/GBiwJYdQnS3qXYrNvrT2hcOAa1ZvIqQNA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=CcvFh4HuzkBSeqWpoXTdQ8k6kPzZDUz8gpq+d2gNRvM=; b=fqTMEBLe jr/4ZMW6ZbmNsZwftDoSwcqAdF/YHRop+EzCeICSta9H6H29FeMTOXvSuTgQuk8H tjluykm/6+WBEFlVsjaf4kbHMH3Pmz7HBNbArHjJMfQeV6+jkgJFfIYi61ruf3Z+ EQM12zW++k3NvvJNz61pDFt/71AfCdgBUbsJ1tjyaTliSzmzd6P366+zTAIfy+PE 8NxxdpHdTII1XCPIu/khS+0O+XL9oBuJgDR13cpT5vmgKj1/OtKCxIViyUcLulQv s0HUg/80ob9IEyzQOIgm4PS08BOQxczcBMDo2xSDM/tQ/wQwv2NgWds+uYU9pISJ t/wi+Itqpiy9cQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudeluddggeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 3 Oct 2021 21:27:49 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 4/6] ARM: dts: sunxi: h3/h5: Update MBUS node Date: Sun, 3 Oct 2021 20:27:37 -0500 Message-Id: <20211004012739.39053-5-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Since the H3 and H5 have different clock divider limits, they need separate compatibles. Signed-off-by: Samuel Holland Reviewed-by: Chanwoo Choi --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 ++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 4e89701df91f..43acb98cf390 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -282,6 +282,10 @@ &display_clocks { compatible = "allwinner,sun8i-h3-de2-clk"; }; +&mbus { + compatible = "allwinner,sun8i-h3-mbus"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c7428df9469e..3a683e190dab 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -568,9 +568,14 @@ external_mdio: mdio@2 { }; mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-h3-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu CLK_MBUS>; + /* compatible is in per SoC .dtsi file */ + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 578a63dedf46..35d5d238e313 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -233,6 +233,10 @@ &display_clocks { compatible = "allwinner,sun50i-h5-de2-clk"; }; +&mbus { + compatible = "allwinner,sun50i-h5-mbus"; +}; + &mmc0 { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; From patchwork Mon Oct 4 01:27:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A5ACC433F5 for ; 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Sun, 3 Oct 2021 21:27:52 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 5/6] arm64: dts: allwinner: a64: Update MBUS node Date: Sun, 3 Oct 2021 20:27:38 -0500 Message-Id: <20211004012739.39053-6-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Signed-off-by: Samuel Holland Reviewed-by: Chanwoo Choi --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 6ddb717f2f98..609a59c6c778 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1129,8 +1129,14 @@ pwm: pwm@1c21400 { mbus: dram-controller@1c62000 { compatible = "allwinner,sun50i-a64-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 112>; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; From patchwork Mon Oct 4 01:27:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12533159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB4A4C4332F for ; Mon, 4 Oct 2021 01:28:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7C63611C5 for ; Mon, 4 Oct 2021 01:28:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232194AbhJDB3u (ORCPT ); Sun, 3 Oct 2021 21:29:50 -0400 Received: from wnew3-smtp.messagingengine.com ([64.147.123.17]:38437 "EHLO wnew3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231935AbhJDB3p (ORCPT ); Sun, 3 Oct 2021 21:29:45 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id ABC8F2B01318; Sun, 3 Oct 2021 21:27:56 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Sun, 03 Oct 2021 21:27:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=1/5827tWbe7lP 9uENZnIZ/9VijMvgu8XCkKxgypswN8=; b=pmYGGpylIc6nnEtAg7YfuV+DXLpX6 aa9Rm/Y/8b72J1YzWyoXhKboPsKSCACzbZV5B5y6wwAgaZQjOXq549GHuTM6gJrJ WIcuyY73o/0T7hoLMN90cux2CJDz8sPhHobNyEAlk7AErwjyiTkGexbbf1z7B8A5 0KWQFBVYn/pnJmj5efld+YvKFuGqQDNqJnrweKBf5qB659gUdldsJrnGFVavdFb8 RKF4wNWFwx0x1Cmm74ElmSzb183JJ/DYWy5VNKBGUNtB6nqCwpv+ycJ32wA3oSZe YS/NK9DhsdoQwuqcevzmUh8pSzIOiYl0HJTYgx+MkUETA32mkNFap1+Yg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=1/5827tWbe7lP9uENZnIZ/9VijMvgu8XCkKxgypswN8=; b=Ge/bDGqU 6NBxMygGLA8kXo+zNeXk6hEAdWPhVk9UexDBhedrJz6wiL7YR0FdhcqW9jgao0B1 yv7WG6kzPjhDRPntoxuE0GXSMfPHT7qh4+xwp4iBt+U6loUGzZwboVcZHlVpoMyF pcf8smfUcIRLl1/JJdhjDSWtcBSGZ6aVnc3QvG7k5AHMLjwLrqEMOKwBbBP75FTJ RTcVkS3VpA3cu5E4WqYbSjhcAQ2RoNJVyeLoZjO8U2V2QkjrLhhd7xdELk8sGVHz FhyfYguruMNf33FbPs0d9ewbIMlsltIDz4ir2W+C2q9PV60T+/df17Eao9DM7Zpx bExVp9WaXP15Qw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudeluddggeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 3 Oct 2021 21:27:54 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v2 6/6] PM / devfreq: Add a driver for the sun8i/sun50i MBUS Date: Sun, 3 Oct 2021 20:27:39 -0500 Message-Id: <20211004012739.39053-7-samuel@sholland.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211004012739.39053-1-samuel@sholland.org> References: <20211004012739.39053-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This driver works by adjusting the divider on the DRAM controller's module clock. Thus there is no fixed set of OPPs, only "full speed" down to "quarter speed" (or whatever the maximum divider is on that variant). It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which takes care of updating registers during the critical section while DRAM is inaccessible. This driver should support several sunxi SoCs, starting with the A33, which have a DesignWare DDR3 controller with merged PHY register space and the matching MBUS register layout (so not A63 or later). However, the driver has only been tested on the A64/H5, so those are the only compatibles enabled for now. Signed-off-by: Samuel Holland Acked-by: Chanwoo Choi --- drivers/devfreq/Kconfig | 8 + drivers/devfreq/Makefile | 1 + drivers/devfreq/sun8i-a33-mbus.c | 511 +++++++++++++++++++++++++++++++ 3 files changed, 520 insertions(+) create mode 100644 drivers/devfreq/sun8i-a33-mbus.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index e87d01c0b76a..b94eb04761f6 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -132,6 +132,14 @@ config ARM_RK3399_DMC_DEVFREQ It sets the frequency for the memory controller and reads the usage counts from hardware. +config ARM_SUN8I_A33_MBUS_DEVFREQ + tristate "sun8i/sun50i MBUS DEVFREQ Driver" + depends on ARCH_SUNXI || COMPILE_TEST + select DEVFREQ_GOV_SIMPLE_ONDEMAND + help + This adds the DEVFREQ driver for the MBUS controller in some + Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index a16333ea7034..0b6be92a25d9 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o +obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o # DEVFREQ Event Drivers diff --git a/drivers/devfreq/sun8i-a33-mbus.c b/drivers/devfreq/sun8i-a33-mbus.c new file mode 100644 index 000000000000..13d32213139f --- /dev/null +++ b/drivers/devfreq/sun8i-a33-mbus.c @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (C) 2020-2021 Samuel Holland +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MBUS_CR 0x0000 +#define MBUS_CR_GET_DRAM_TYPE(x) (((x) >> 16) & 0x7) +#define MBUS_CR_DRAM_TYPE_DDR2 2 +#define MBUS_CR_DRAM_TYPE_DDR3 3 +#define MBUS_CR_DRAM_TYPE_DDR4 4 +#define MBUS_CR_DRAM_TYPE_LPDDR2 6 +#define MBUS_CR_DRAM_TYPE_LPDDR3 7 + +#define MBUS_TMR 0x000c +#define MBUS_TMR_PERIOD(x) ((x) - 1) + +#define MBUS_PMU_CFG 0x009c +#define MBUS_PMU_CFG_PERIOD(x) (((x) - 1) << 16) +#define MBUS_PMU_CFG_UNIT (0x3 << 1) +#define MBUS_PMU_CFG_UNIT_B (0x0 << 1) +#define MBUS_PMU_CFG_UNIT_KB (0x1 << 1) +#define MBUS_PMU_CFG_UNIT_MB (0x2 << 1) +#define MBUS_PMU_CFG_ENABLE (0x1 << 0) + +#define MBUS_PMU_BWCR(n) (0x00a0 + (0x04 * (n))) + +#define MBUS_TOTAL_BWCR MBUS_PMU_BWCR(5) +#define MBUS_TOTAL_BWCR_H616 MBUS_PMU_BWCR(13) + +#define MBUS_MDFSCR 0x0100 +#define MBUS_MDFSCR_BUFFER_TIMING (0x1 << 15) +#define MBUS_MDFSCR_PAD_HOLD (0x1 << 13) +#define MBUS_MDFSCR_BYPASS (0x1 << 4) +#define MBUS_MDFSCR_MODE (0x1 << 1) +#define MBUS_MDFSCR_MODE_DFS (0x0 << 1) +#define MBUS_MDFSCR_MODE_CFS (0x1 << 1) +#define MBUS_MDFSCR_START (0x1 << 0) + +#define MBUS_MDFSMRMR 0x0108 + +#define DRAM_PWRCTL 0x0004 +#define DRAM_PWRCTL_SELFREF_EN (0x1 << 0) + +#define DRAM_RFSHTMG 0x0090 +#define DRAM_RFSHTMG_TREFI(x) ((x) << 16) +#define DRAM_RFSHTMG_TRFC(x) ((x) << 0) + +#define DRAM_VTFCR 0x00b8 +#define DRAM_VTFCR_VTF_ENABLE (0x3 << 8) + +#define DRAM_ODTMAP 0x0120 + +#define DRAM_DX_MAX 4 + +#define DRAM_DXnGCR0(n) (0x0344 + 0x80 * (n)) +#define DRAM_DXnGCR0_DXODT (0x3 << 4) +#define DRAM_DXnGCR0_DXODT_DYNAMIC (0x0 << 4) +#define DRAM_DXnGCR0_DXODT_ENABLED (0x1 << 4) +#define DRAM_DXnGCR0_DXODT_DISABLED (0x2 << 4) +#define DRAM_DXnGCR0_DXEN (0x1 << 0) + +struct sun8i_a33_mbus_variant { + u32 min_dram_divider; + u32 max_dram_divider; + u32 odt_freq_mhz; +}; + +struct sun8i_a33_mbus { + const struct sun8i_a33_mbus_variant *variant; + void __iomem *reg_dram; + void __iomem *reg_mbus; + struct clk *clk_bus; + struct clk *clk_dram; + struct clk *clk_mbus; + struct devfreq *devfreq_dram; + struct devfreq_simple_ondemand_data gov_data; + struct devfreq_dev_profile profile; + u32 data_width; + u32 nominal_bw; + u32 odtmap; + u32 tREFI_ns; + u32 tRFC_ns; + unsigned long freq_table[]; +}; + +/* + * The unit for this value is (MBUS clock cycles / MBUS_TMR_PERIOD). When + * MBUS_TMR_PERIOD is programmed to match the MBUS clock frequency in MHz, as + * it is during DRAM init and during probe, the resulting unit is microseconds. + */ +static int pmu_period = 50000; +module_param(pmu_period, int, 0644); +MODULE_PARM_DESC(pmu_period, "Bandwidth measurement period (microseconds)"); + +static u32 sun8i_a33_mbus_get_peak_bw(struct sun8i_a33_mbus *priv) +{ + /* Returns the peak transfer (in KiB) during any single PMU period. */ + return readl_relaxed(priv->reg_mbus + MBUS_TOTAL_BWCR); +} + +static void sun8i_a33_mbus_restart_pmu_counters(struct sun8i_a33_mbus *priv) +{ + u32 pmu_cfg = MBUS_PMU_CFG_PERIOD(pmu_period) | MBUS_PMU_CFG_UNIT_KB; + + /* All PMU counters are cleared on a disable->enable transition. */ + writel_relaxed(pmu_cfg, + priv->reg_mbus + MBUS_PMU_CFG); + writel_relaxed(pmu_cfg | MBUS_PMU_CFG_ENABLE, + priv->reg_mbus + MBUS_PMU_CFG); + +} + +static void sun8i_a33_mbus_update_nominal_bw(struct sun8i_a33_mbus *priv, + u32 ddr_freq_mhz) +{ + /* + * Nominal bandwidth (KiB per PMU period): + * + * DDR transfers microseconds KiB + * ------------- * ------------ * -------- + * microsecond PMU period transfer + */ + priv->nominal_bw = ddr_freq_mhz * pmu_period * priv->data_width / 1024; +} + +static int sun8i_a33_mbus_set_dram_freq(struct sun8i_a33_mbus *priv, + unsigned long freq) +{ + u32 ddr_freq_mhz = freq / USEC_PER_SEC; /* DDR */ + u32 dram_freq_mhz = ddr_freq_mhz / 2; /* SDR */ + u32 mctl_freq_mhz = dram_freq_mhz / 2; /* HDR */ + u32 dxodt, mdfscr, pwrctl, vtfcr; + u32 i, tREFI_32ck, tRFC_ck; + int ret; + + /* The rate change is not effective until the MDFS process runs. */ + ret = clk_set_rate(priv->clk_dram, freq); + if (ret) + return ret; + + /* Disable automatic self-refesh and VTF before starting MDFS. */ + pwrctl = readl_relaxed(priv->reg_dram + DRAM_PWRCTL) & + ~DRAM_PWRCTL_SELFREF_EN; + writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL); + vtfcr = readl_relaxed(priv->reg_dram + DRAM_VTFCR); + writel_relaxed(vtfcr & ~DRAM_VTFCR_VTF_ENABLE, + priv->reg_dram + DRAM_VTFCR); + + /* Set up MDFS and enable double buffering for timing registers. */ + mdfscr = MBUS_MDFSCR_MODE_DFS | + MBUS_MDFSCR_BYPASS | + MBUS_MDFSCR_PAD_HOLD | + MBUS_MDFSCR_BUFFER_TIMING; + writel(mdfscr, priv->reg_mbus + MBUS_MDFSCR); + + /* Update the buffered copy of RFSHTMG. */ + tREFI_32ck = priv->tREFI_ns * mctl_freq_mhz / 1000 / 32; + tRFC_ck = DIV_ROUND_UP(priv->tRFC_ns * mctl_freq_mhz, 1000); + writel(DRAM_RFSHTMG_TREFI(tREFI_32ck) | DRAM_RFSHTMG_TRFC(tRFC_ck), + priv->reg_dram + DRAM_RFSHTMG); + + /* Enable ODT if needed, or disable it to save power. */ + if (priv->odtmap && dram_freq_mhz > priv->variant->odt_freq_mhz) { + dxodt = DRAM_DXnGCR0_DXODT_DYNAMIC; + writel(priv->odtmap, priv->reg_dram + DRAM_ODTMAP); + } else { + dxodt = DRAM_DXnGCR0_DXODT_DISABLED; + writel(0, priv->reg_dram + DRAM_ODTMAP); + } + for (i = 0; i < DRAM_DX_MAX; ++i) { + void __iomem *reg = priv->reg_dram + DRAM_DXnGCR0(i); + + writel((readl(reg) & ~DRAM_DXnGCR0_DXODT) | dxodt, reg); + } + + dev_dbg(priv->devfreq_dram->dev.parent, + "Setting DRAM to %u MHz, tREFI=%u, tRFC=%u, ODT=%s\n", + dram_freq_mhz, tREFI_32ck, tRFC_ck, + dxodt == DRAM_DXnGCR0_DXODT_DYNAMIC ? "dynamic" : "disabled"); + + /* Trigger hardware MDFS. */ + writel(mdfscr | MBUS_MDFSCR_START, priv->reg_mbus + MBUS_MDFSCR); + ret = readl_poll_timeout_atomic(priv->reg_mbus + MBUS_MDFSCR, mdfscr, + !(mdfscr & MBUS_MDFSCR_START), 10, 1000); + if (ret) + return ret; + + /* Disable double buffering. */ + writel(0, priv->reg_mbus + MBUS_MDFSCR); + + /* Restore VTF configuration. */ + writel_relaxed(vtfcr, priv->reg_dram + DRAM_VTFCR); + + /* Enable automatic self-refresh at the lowest frequency only. */ + if (freq == priv->freq_table[0]) + pwrctl |= DRAM_PWRCTL_SELFREF_EN; + writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL); + + sun8i_a33_mbus_restart_pmu_counters(priv); + sun8i_a33_mbus_update_nominal_bw(priv, ddr_freq_mhz); + + return 0; +} + +static int sun8i_a33_mbus_set_dram_target(struct device *dev, + unsigned long *freq, u32 flags) +{ + struct sun8i_a33_mbus *priv = dev_get_drvdata(dev); + struct devfreq *devfreq = priv->devfreq_dram; + struct dev_pm_opp *opp; + int ret; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + dev_pm_opp_put(opp); + + if (*freq == devfreq->previous_freq) + return 0; + + ret = sun8i_a33_mbus_set_dram_freq(priv, *freq); + if (ret) { + dev_warn(dev, "failed to set DRAM frequency: %d\n", ret); + *freq = devfreq->previous_freq; + } + + return ret; +} + +static int sun8i_a33_mbus_get_dram_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct sun8i_a33_mbus *priv = dev_get_drvdata(dev); + + stat->busy_time = sun8i_a33_mbus_get_peak_bw(priv); + stat->total_time = priv->nominal_bw; + stat->current_frequency = priv->devfreq_dram->previous_freq; + + sun8i_a33_mbus_restart_pmu_counters(priv); + + dev_dbg(dev, "Using %lu/%lu (%lu%%) at %lu MHz\n", + stat->busy_time, stat->total_time, + DIV_ROUND_CLOSEST(stat->busy_time * 100, stat->total_time), + stat->current_frequency / USEC_PER_SEC); + + return 0; +} + +static int sun8i_a33_mbus_hw_init(struct device *dev, + struct sun8i_a33_mbus *priv, + unsigned long ddr_freq) +{ + u32 i, mbus_cr, mbus_freq_mhz; + + /* Choose tREFI and tRFC to match the configured DRAM type. */ + mbus_cr = readl_relaxed(priv->reg_mbus + MBUS_CR); + switch (MBUS_CR_GET_DRAM_TYPE(mbus_cr)) { + case MBUS_CR_DRAM_TYPE_DDR2: + case MBUS_CR_DRAM_TYPE_DDR3: + case MBUS_CR_DRAM_TYPE_DDR4: + priv->tREFI_ns = 7800; + priv->tRFC_ns = 350; + break; + case MBUS_CR_DRAM_TYPE_LPDDR2: + case MBUS_CR_DRAM_TYPE_LPDDR3: + priv->tREFI_ns = 3900; + priv->tRFC_ns = 210; + break; + default: + return -EINVAL; + } + + /* Save ODTMAP so it can be restored when raising the frequency. */ + priv->odtmap = readl_relaxed(priv->reg_dram + DRAM_ODTMAP); + + /* Compute the DRAM data bus width by counting enabled DATx8 blocks. */ + for (i = 0; i < DRAM_DX_MAX; ++i) { + void __iomem *reg = priv->reg_dram + DRAM_DXnGCR0(i); + + if (!(readl_relaxed(reg) & DRAM_DXnGCR0_DXEN)) + break; + } + priv->data_width = i; + + dev_dbg(dev, "Detected %u-bit %sDDRx with%s ODT\n", + priv->data_width * 8, + MBUS_CR_GET_DRAM_TYPE(mbus_cr) > 4 ? "LP" : "", + priv->odtmap ? "" : "out"); + + /* Program MBUS_TMR such that the PMU period unit is microseconds. */ + mbus_freq_mhz = clk_get_rate(priv->clk_mbus) / USEC_PER_SEC; + writel_relaxed(MBUS_TMR_PERIOD(mbus_freq_mhz), + priv->reg_mbus + MBUS_TMR); + + /* "Master Ready Mask Register" bits must be set or MDFS will block. */ + writel_relaxed(0xffffffff, priv->reg_mbus + MBUS_MDFSMRMR); + + sun8i_a33_mbus_restart_pmu_counters(priv); + sun8i_a33_mbus_update_nominal_bw(priv, ddr_freq / USEC_PER_SEC); + + return 0; +} + +static int __maybe_unused sun8i_a33_mbus_suspend(struct device *dev) +{ + struct sun8i_a33_mbus *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk_bus); + + return 0; +} + +static int __maybe_unused sun8i_a33_mbus_resume(struct device *dev) +{ + struct sun8i_a33_mbus *priv = dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk_bus); +} + +static int sun8i_a33_mbus_probe(struct platform_device *pdev) +{ + const struct sun8i_a33_mbus_variant *variant; + struct device *dev = &pdev->dev; + struct sun8i_a33_mbus *priv; + unsigned long base_freq; + unsigned int max_state; + const char *err; + int i, ret; + + variant = device_get_match_data(dev); + if (!variant) + return -EINVAL; + + max_state = variant->max_dram_divider - variant->min_dram_divider + 1; + + priv = devm_kzalloc(dev, struct_size(priv, freq_table, max_state), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + priv->variant = variant; + + priv->reg_dram = devm_platform_ioremap_resource_byname(pdev, "dram"); + if (IS_ERR(priv->reg_dram)) + return PTR_ERR(priv->reg_dram); + + priv->reg_mbus = devm_platform_ioremap_resource_byname(pdev, "mbus"); + if (IS_ERR(priv->reg_mbus)) + return PTR_ERR(priv->reg_mbus); + + priv->clk_bus = devm_clk_get(dev, "bus"); + if (IS_ERR(priv->clk_bus)) + return dev_err_probe(dev, PTR_ERR(priv->clk_bus), + "failed to get bus clock\n"); + + priv->clk_dram = devm_clk_get(dev, "dram"); + if (IS_ERR(priv->clk_dram)) + return dev_err_probe(dev, PTR_ERR(priv->clk_dram), + "failed to get dram clock\n"); + + priv->clk_mbus = devm_clk_get(dev, "mbus"); + if (IS_ERR(priv->clk_mbus)) + return dev_err_probe(dev, PTR_ERR(priv->clk_mbus), + "failed to get mbus clock\n"); + + ret = clk_prepare_enable(priv->clk_bus); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable bus clock\n"); + + /* Lock the DRAM clock rate to keep priv->nominal_bw in sync. */ + ret = clk_rate_exclusive_get(priv->clk_dram); + if (ret) { + err = "failed to lock dram clock rate\n"; + goto err_disable_bus; + } + + /* Lock the MBUS clock rate to keep MBUS_TMR_PERIOD in sync. */ + ret = clk_rate_exclusive_get(priv->clk_mbus); + if (ret) { + err = "failed to lock mbus clock rate\n"; + goto err_unlock_dram; + } + + priv->gov_data.upthreshold = 10; + priv->gov_data.downdifferential = 5; + + priv->profile.initial_freq = clk_get_rate(priv->clk_dram); + priv->profile.polling_ms = 1000; + priv->profile.target = sun8i_a33_mbus_set_dram_target; + priv->profile.get_dev_status = sun8i_a33_mbus_get_dram_status; + priv->profile.freq_table = priv->freq_table; + priv->profile.max_state = max_state; + + ret = devm_pm_opp_set_clkname(dev, "dram"); + if (ret) { + err = "failed to add OPP table\n"; + goto err_unlock_mbus; + } + + base_freq = clk_get_rate(clk_get_parent(priv->clk_dram)); + for (i = 0; i < max_state; ++i) { + unsigned int div = variant->max_dram_divider - i; + + priv->freq_table[i] = base_freq / div; + + ret = dev_pm_opp_add(dev, priv->freq_table[i], 0); + if (ret) { + err = "failed to add OPPs\n"; + goto err_remove_opps; + } + } + + ret = sun8i_a33_mbus_hw_init(dev, priv, priv->profile.initial_freq); + if (ret) { + err = "failed to init hardware\n"; + goto err_remove_opps; + } + + priv->devfreq_dram = devfreq_add_device(dev, &priv->profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &priv->gov_data); + if (IS_ERR(priv->devfreq_dram)) { + ret = PTR_ERR(priv->devfreq_dram); + err = "failed to add devfreq device\n"; + goto err_remove_opps; + } + + /* + * This must be set manually after registering the devfreq device, + * because there is no way to select a dynamic OPP as the suspend OPP. + */ + priv->devfreq_dram->suspend_freq = priv->freq_table[0]; + + return 0; + +err_remove_opps: + dev_pm_opp_remove_all_dynamic(dev); +err_unlock_mbus: + clk_rate_exclusive_put(priv->clk_mbus); +err_unlock_dram: + clk_rate_exclusive_put(priv->clk_dram); +err_disable_bus: + clk_disable_unprepare(priv->clk_bus); + + return dev_err_probe(dev, ret, err); +} + +static int sun8i_a33_mbus_remove(struct platform_device *pdev) +{ + struct sun8i_a33_mbus *priv = platform_get_drvdata(pdev); + unsigned long initial_freq = priv->profile.initial_freq; + struct device *dev = &pdev->dev; + int ret; + + devfreq_remove_device(priv->devfreq_dram); + + ret = sun8i_a33_mbus_set_dram_freq(priv, initial_freq); + if (ret) + dev_warn(dev, "failed to restore DRAM frequency: %d\n", ret); + + dev_pm_opp_remove_all_dynamic(dev); + clk_rate_exclusive_put(priv->clk_mbus); + clk_rate_exclusive_put(priv->clk_dram); + clk_disable_unprepare(priv->clk_bus); + + return 0; +} + +static const struct sun8i_a33_mbus_variant sun50i_a64_mbus = { + .min_dram_divider = 1, + .max_dram_divider = 4, + .odt_freq_mhz = 400, +}; + +static const struct of_device_id sun8i_a33_mbus_of_match[] = { + { .compatible = "allwinner,sun50i-a64-mbus", .data = &sun50i_a64_mbus }, + { .compatible = "allwinner,sun50i-h5-mbus", .data = &sun50i_a64_mbus }, + { }, +}; +MODULE_DEVICE_TABLE(of, sun8i_a33_mbus_of_match); + +static SIMPLE_DEV_PM_OPS(sun8i_a33_mbus_pm_ops, + sun8i_a33_mbus_suspend, sun8i_a33_mbus_resume); + +static struct platform_driver sun8i_a33_mbus_driver = { + .probe = sun8i_a33_mbus_probe, + .remove = sun8i_a33_mbus_remove, + .driver = { + .name = "sun8i-a33-mbus", + .of_match_table = sun8i_a33_mbus_of_match, + .pm = pm_ptr(&sun8i_a33_mbus_pm_ops), + }, +}; +module_platform_driver(sun8i_a33_mbus_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Allwinner sun8i/sun50i MBUS DEVFREQ Driver"); +MODULE_LICENSE("GPL v2");