From patchwork Mon Oct 4 17:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534481 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40A59C433EF for ; Mon, 4 Oct 2021 18:01:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 291C861213 for ; Mon, 4 Oct 2021 18:01:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236175AbhJDSDJ (ORCPT ); Mon, 4 Oct 2021 14:03:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236103AbhJDSDI (ORCPT ); Mon, 4 Oct 2021 14:03:08 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F5FAC061745; Mon, 4 Oct 2021 11:01:19 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id na16-20020a17090b4c1000b0019f5bb661f9so542618pjb.0; Mon, 04 Oct 2021 11:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B7sq5HEJs5lGnG+J8tujUids2AjtGM7weFegW7/rlp0=; b=DCLTSaQ07PyQGYWXH1+2Xsfdvw5DGV/I8XtRyOJbPaLb7kUI5hE9bZs5tBKfKfnEZv yJWA9rYnr0brHhmOMVeV+trr2fiBrUYwjSZbYSZwDmP9r/JS76OU6s/3AdycKZWfYTFw CIclJY0tQH0UeDsZcm6RtmrZGNXAT160EC6VgsC9hOtIq0iSkaWcZ0KkM1D96wVVTdxM U+yKA9jvbDs9v12WOHtt4EpvmMzklJn+8vLlgMBPU0VuViSjzLx2CwTYViJ73cL/+5xP vGqSeNgUdhH7az1nnmJYLp6QV6XxCG8nLT0xkZmBoClJDUKZ/T4ZfTcgZV5MYU4BQyQC CewA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B7sq5HEJs5lGnG+J8tujUids2AjtGM7weFegW7/rlp0=; b=gGDmz3spj+dZDma/u/VZ/a1y8edYSGABWRtOuyLRFzB3JEIZGvAvPN4maaHs3xwP2T ttY1vOcOUr8H83zk+Ab/80Yic4h9RqKGsGUMAPUyuXyat5HvqX8dbp/eKhGS/EAgCb1k phumd+dvDdRsvQ+EaAaYnpFi56xM5wDd2KcYTgltVLuG4W+PGMHVzJJtvQ0JSqiXg5Jo jTHVIFUYkKU/Cxoa1GWU+BcjWIla36KGCUMpL0B4PpeCuyWw6iu/bQNn/TbvMuq0Oveb ieNr0V6JTAShRJcEBCMGwPyfLeM5nGq5GohVDB8A0cY4797fCaB03aeZDTrG/3k6o+eO w3tA== X-Gm-Message-State: AOAM5309NLlPnLB1bbB8nYF4NtmMZmvn6o812E1dGAcTjAwwu6w45Wp6 5uVErnw+50OZ4xhZuPwr2r0= X-Google-Smtp-Source: ABdhPJxqQ1dbB0F5R2hGORk15/5zZpFg9rCi0DkVZQ7y0tE2wiTwWP4DlAOal+8YQvciNlfn7Vn2pw== X-Received: by 2002:a17:902:a503:b029:12b:2429:385e with SMTP id s3-20020a170902a503b029012b2429385emr966754plq.64.1633370478701; Mon, 04 Oct 2021 11:01:18 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:e8f0:c2a7:3579:5fe8:31d9]) by smtp.gmail.com with ESMTPSA id z2sm3641004pfe.210.2021.10.04.11.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 11:01:18 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de, ruscur@russell.cc, oohall@gmail.com Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH 1/6] PCI/AER: Enable COR/UNCOR error reporting in set_device_error_reporting() Date: Mon, 4 Oct 2021 23:29:27 +0530 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The (PCIe r5.0, sec 7.6.4.3, Table 7-101) and (PCIe r5.0, sec 7.8.4.6, Table 7-104) states that the default values for the Uncorrectable Error Mask and Correctable Error Mask should be 0b. But the current code does not set the default value of these registers when the PCIe bus loads the AER service driver. Enable reporting of all correctable and uncorrectable errors during aer_probe() Signed-off-by: Naveen Naidu --- drivers/pci/pcie/aer.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 9784fdcf3006..88c4ca6098fb 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1212,6 +1212,7 @@ static int set_device_error_reporting(struct pci_dev *dev, void *data) { bool enable = *((bool *)data); int type = pci_pcie_type(dev); + int aer = dev->aer_cap; if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_RC_EC) || @@ -1223,8 +1224,18 @@ static int set_device_error_reporting(struct pci_dev *dev, void *data) pci_disable_pcie_error_reporting(dev); } - if (enable) + if (enable) { + + /* Enable reporting of all uncorrectable errors */ + /* Uncorrectable Error Mask - turned on bits disable errors */ + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 0); + + /* Enable reporting of all correctable errors */ + /* Correctable Error Mask - turned on bits disable errors */ + pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, 0); + pcie_set_ecrc_checking(dev); + } return 0; } From patchwork Mon Oct 4 17:59:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534483 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D5A7C433F5 for ; Mon, 4 Oct 2021 18:01:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47A7E61213 for ; Mon, 4 Oct 2021 18:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235285AbhJDSDr (ORCPT ); Mon, 4 Oct 2021 14:03:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236419AbhJDSDn (ORCPT ); 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Mon, 04 Oct 2021 11:01:52 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 2/6] MIPS: OCTEON: Remove redundant clearing of AER status registers Date: Mon, 4 Oct 2021 23:29:28 +0530 Message-Id: <81597ce8ee30ad01da86fe1edf0fab76aa9b9710.1633369560.git.naveennaidu479@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time. Currently when CONFIG_PCIEAER=y, the Uncorrectable Error status, Correctable Error status and Root status registers are cleared during the PCI Bus enumeration path by pci_aer_init() via pci_init_capabilities() It is now no longer necessary for Octeon code to clear AER status registers since it's done by PCI core. Signed-off-by: Naveen Naidu --- arch/mips/pci/pci-octeon.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index fc29b85cfa92..8e8b282226cc 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -124,11 +124,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (pos) { - /* Clear Uncorrectable Error Status */ - pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, - &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, - dconfig); /* Enable reporting of all uncorrectable errors */ /* Uncorrectable Error Mask - turned on bits disable errors */ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); @@ -138,9 +133,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * correctable, not if the error is reported. */ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ - /* Clear Correctable Error Status */ - pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); /* Enable reporting of all correctable errors */ /* Correctable Error Mask - turned on bits disable errors */ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); @@ -159,9 +151,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) PCI_ERR_ROOT_CMD_COR_EN | PCI_ERR_ROOT_CMD_NONFATAL_EN | PCI_ERR_ROOT_CMD_FATAL_EN); - /* Clear the Root status register */ - pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); - pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); } return 0; From patchwork Mon Oct 4 17:59:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534485 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A80CC433EF for ; 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Mon, 04 Oct 2021 11:02:05 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:e8f0:c2a7:3579:5fe8:31d9]) by smtp.gmail.com with ESMTPSA id z2sm3641004pfe.210.2021.10.04.11.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 11:02:05 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 3/6] MIPS: OCTEON: Remove redundant enable of PCIe normal error reporting Date: Mon, 4 Oct 2021 23:29:29 +0530 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time. Currently when CONFIG_PCIEAER=y, the PCIe normal error reporting is enabled by pci_enable_pcie_error_reporting() in the aer_probe() path. It is now no longer necessary for Octeon code to enable PCIe normal error since it's done when PCIe bus loads the AER service driver. Signed-off-by: Naveen Naidu --- arch/mips/pci/pci-octeon.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 8e8b282226cc..2c251018075c 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -114,13 +114,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); } - /* Enable the PCIe normal error reporting */ - config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ - config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ - pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); - /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (pos) { From patchwork Mon Oct 4 17:59:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534487 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4266C433EF for ; Mon, 4 Oct 2021 18:02:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BC9360FBF for ; Mon, 4 Oct 2021 18:02:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236341AbhJDSEU (ORCPT ); Mon, 4 Oct 2021 14:04:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236449AbhJDSEO (ORCPT ); Mon, 4 Oct 2021 14:04:14 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0DBAC061753; Mon, 4 Oct 2021 11:02:21 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id m26so1963340pff.3; Mon, 04 Oct 2021 11:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KXqbMrl5ji7P3WLEqvYvyx/g2tHqF5Pvsy98EpcbEmA=; b=dK+/OiASR7/FhhaAZ1YS1MI0vNDY5l52Cxz3No+1sg7HRJnIdcgAq2YwESOyPBn6U2 ylQrlDPi0zET4PEkuZZaCD2aMFfQFJd5zq6AkC0uFi2S2rmimoy07cpRoQDo08+j3TlM mm82LwXdWRtUirmQLHAQH5mBG4+PmSS85QwdWqcPmhfkFCN/BNttISWbcw9IBCdZK339 /ZZSwBhc414AE9lM7y7WmavuWwWVzavo+q3xY267R/GbDxwoAsITSos7CCXOGaq/BVj6 IPbA+CMtTg7ClhaFo/okYXOLZ8iemQ8vLlIPKr3K54As7GRT2CBtzx3b8o6HhtlMgguf rAgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KXqbMrl5ji7P3WLEqvYvyx/g2tHqF5Pvsy98EpcbEmA=; b=VUBuCbAQ5/qDQxa6SD4YIR/YWIvHomJCREOOYn/Bbsp4hUij4pSFcCGmclwIN5DPJA wdeT/3vaMKFU/rb4S0rhROPMqzWoT7Hek0ySMXeYjnAJV4o2gOi+M9qrUQjwgpD2Si/H yS0XUAuJAfcs7iafl67uxtlD8p/ukKT6j9wfjD8WvlcKlIgHbQTIZiP028EyGP+iQuZA 8HJP4AwnliqWHg1dmgCgmoqOoiBVV90Ku2pEMs6wT+o3ocIe2bjsGaHKMGlUynkshHTD oCCEdd+Omh30bRFtGtTvN3QNXtx/iLalGfhlDiLpR1QwaxxHcIzwrRKsBn5xt47+AC34 JGlQ== X-Gm-Message-State: AOAM530dKry3KdePLLA7+UI+M9l8o++9uOISnt8TK2DTshxxdGpl5AGn xxmeSk8MyHmSA5gcih2OH3c= X-Google-Smtp-Source: ABdhPJzbBvEjkhQa/NIXLQN94nJSDDapaLKAaUE41cWvqwkMormTval0zeWCNCkCWwbjm9h9m6LR6Q== X-Received: by 2002:a65:44c4:: with SMTP id g4mr12117582pgs.254.1633370541031; Mon, 04 Oct 2021 11:02:21 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:e8f0:c2a7:3579:5fe8:31d9]) by smtp.gmail.com with ESMTPSA id z2sm3641004pfe.210.2021.10.04.11.02.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 11:02:20 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 4/6] MIPS: OCTEON: Remove redundant enable of COR/UNCOR error Date: Mon, 4 Oct 2021 23:29:30 +0530 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time. Currently when CONFIG_PCIEAER=y, correctable/uncorrectable errors are enabled by set_device_error_reporting() in the aer_probe() path. It is now no longer necessary for Octeon code to enable PCIe COR/UNCOR errors since it's done when PCIe bus loads the AER service driver. Signed-off-by: Naveen Naidu --- arch/mips/pci/pci-octeon.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 2c251018075c..a82cf48f00ab 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -117,18 +117,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev) /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (pos) { - /* Enable reporting of all uncorrectable errors */ - /* Uncorrectable Error Mask - turned on bits disable errors */ - pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); /* * Leave severity at HW default. This only controls if * errors are reported as uncorrectable or * correctable, not if the error is reported. */ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ - /* Enable reporting of all correctable errors */ - /* Correctable Error Mask - turned on bits disable errors */ - pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); + /* Advanced Error Capabilities */ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); /* ECRC Generation Enable */ From patchwork Mon Oct 4 17:59:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534489 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F054C433FE for ; Mon, 4 Oct 2021 18:02:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB886611F0 for ; Mon, 4 Oct 2021 18:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236847AbhJDSE3 (ORCPT ); Mon, 4 Oct 2021 14:04:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236615AbhJDSE2 (ORCPT ); Mon, 4 Oct 2021 14:04:28 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F384C06174E; Mon, 4 Oct 2021 11:02:39 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id y5so463861pll.3; Mon, 04 Oct 2021 11:02:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=25oPhBAQkpYHQtBYswx+vS6+yZtQwuBWM057qnMpNgo=; b=a+i/D2I2zafjFRyVlx3zfqTHD/dvxl0+TVAzlmofD0s5Qm7DQxny3W3HPYBfFYfg7U DPQwS1MXFkOlOEpIdsFNgW8RFIwa5dUjs31vNl+2J46pcKEmEZJJO6cHIAAfEXRsgpHg 7SwyOHal9fLukzQPAoo44doJJpZoZSEa8MLs0kOFAtuH+etLAEp3iHhVG3baosWkdLjq 4mMw8HON7jV2S6toLxJWlPp/fmwhz5Yh+8izA9POP5P7hU1PGWxFjBJiB4w2TPhM/Vi4 m5L3pOMuyKVbbnUWI2LL6mA8/H5aPbRdQ5dJQSCCj5/1kq4gAWl/sn6rxKpJORaP1S+d Jkaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=25oPhBAQkpYHQtBYswx+vS6+yZtQwuBWM057qnMpNgo=; b=ZBSLPDoW6SNomPi+37ehcFf7Nrxc1U3e/wrUG6zuukuWmP6nrDkKQvKLBeGRv7kRF+ UzNJtbb72ZCtPjtYB/cu9RDZrx1feYBr5pmkCAMx0YPom/QgW/ni4DbGrFd/ADjg+ZwC M2l01yWeqo+aBIbA8xbHFkiDM3sH0JlGxgYA1Ji2XAO2DSHlWJXptY2OxH5SUihiHRAe +vFxyMPO36iEWev4crTXIsZ1mKBYGPdfOanW6FKrgBmPNh3j3usWO6oI071SzJHtBshY OokES6y9QGdrx1unEIK2CJXkgPffe54SKkrt+ruSEs41rLaMCACtSzVD9tfxev7w2kUL WQug== X-Gm-Message-State: AOAM531/9qP6ouYkW1kplSMFGZNrWIgx7015sRafqGGBdwiWJUOPL57d FBculNW9QSHqnQ5OljwNHo0= X-Google-Smtp-Source: ABdhPJxv6QIzFS3p/UlJANVCJKP+PWKnIFZqL4BNZk5cQPC6u6+nGacnfaojYfhuU38H2X9HnRDehA== X-Received: by 2002:a17:90a:428e:: with SMTP id p14mr38364317pjg.92.1633370558785; Mon, 04 Oct 2021 11:02:38 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:e8f0:c2a7:3579:5fe8:31d9]) by smtp.gmail.com with ESMTPSA id z2sm3641004pfe.210.2021.10.04.11.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 11:02:38 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 5/6] MIPS: OCTEON: Remove redundant ECRC Generation Enable Date: Mon, 4 Oct 2021 23:29:31 +0530 Message-Id: <6d0856b6953765463aac43fbd641d26f19dc7e11.1633369560.git.naveennaidu479@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time. Currently when CONFIG_PCIEAER=y, ECRC generation is enabled by pcie_set_ecrc_checking() in the aer_probe() path. It is now no longer necessary for Octeon code to enable ECRC since it's done when PCIe bus loads the AER service driver. Signed-off-by: Naveen Naidu --- arch/mips/pci/pci-octeon.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index a82cf48f00ab..b973fc464c21 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -124,15 +124,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) */ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ - /* Advanced Error Capabilities */ - pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); - /* ECRC Generation Enable */ - if (config & PCI_ERR_CAP_ECRC_GENC) - config |= PCI_ERR_CAP_ECRC_GENE; - /* ECRC Check Enable */ - if (config & PCI_ERR_CAP_ECRC_CHKC) - config |= PCI_ERR_CAP_ECRC_CHKE; - pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ /* Report all errors to the root complex */ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, From patchwork Mon Oct 4 17:59:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Naidu X-Patchwork-Id: 12534491 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7F7CC433EF for ; Mon, 4 Oct 2021 18:02:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A73CB61130 for ; Mon, 4 Oct 2021 18:02:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233839AbhJDSEj (ORCPT ); Mon, 4 Oct 2021 14:04:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236808AbhJDSEi (ORCPT ); Mon, 4 Oct 2021 14:04:38 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AA2BC061746; Mon, 4 Oct 2021 11:02:49 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id l6so447889plh.9; Mon, 04 Oct 2021 11:02:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PKklRx9y5Qor/aGWnNnuo+lS2V9yeaUbLzR0QD7Qli0=; b=EjT1r3PfOqOTV9SjziQCZVpG3EQgBHx0RG8Xv1lR0WpTgXkde6DDI2XQGrKGdHGuOu sF8twN+l6PEyjaQgO2BIbkDAnZOxsyGpLSQx0bkTBfWz4phFythCJUO4BZRv3/Z/8zKr 1//l0509wxgBJzdQE3exb9ktxgeL1GX8XjLoF24duAVx1O1TZSBk2RSLHje65Qnxn8tD choOqeAKFsYBiq3gwXktjQK6A0LUWmGLIwhm3ekrXBemHgpW2KSXMwBP7rUFeKDPmjfS WWxTDvX8wjrXjFPuwm3Fey5YCsR27a1Yb26TkgNatJpgQGXQF46aJ9xIPDup4JAZPfGu OtpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PKklRx9y5Qor/aGWnNnuo+lS2V9yeaUbLzR0QD7Qli0=; b=HUqCVuFIcd5uuOUKHaHLHcZbNTB1pk1qtXrlefC+qC8gWglQpY5Z0shn5SBaz7AVui 4P33HKZflSue4k97zueShSA8+nOpru69GiJ5t6o7dPrRju6+mVffyEWDjyfDi+q38Zp4 DKQsJpF/9fh5fx6C0oRSiCP67noRrk2DCALV4Ktejja48xalsX/P06+KenEMl3cnzXkY 8FghdiaVEuFq66vN6Z6iFb2oLyutVXLLe786ng+8CHnWcsPr/USDULjNptpwinNxtwYL jt5R3au2IbIYNv9C/Rm46h6b9dv63K4w4MIEh8+jvo9leIM4Qipp+xgj7ZNFQyn8lUbb PPWA== X-Gm-Message-State: AOAM530eJGyu7RaX4jQHMV8O75apboG1gCzXG4SaL8faCU+01GhfAFK4 RRIM5x7O9jWehe9Zv2iAdfbU+XYbBg2NIH4O X-Google-Smtp-Source: ABdhPJyBIls+LLr17tvrEzq80SP4CQurse34IktWPG8aqV9f13TkQAW/TRNDg2X5+MjZ3loaaHOhLw== X-Received: by 2002:a17:90a:8912:: with SMTP id u18mr31155201pjn.69.1633370568999; Mon, 04 Oct 2021 11:02:48 -0700 (PDT) Received: from localhost.localdomain ([2406:7400:63:e8f0:c2a7:3579:5fe8:31d9]) by smtp.gmail.com with ESMTPSA id z2sm3641004pfe.210.2021.10.04.11.02.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 11:02:48 -0700 (PDT) From: Naveen Naidu To: bhelgaas@google.com, tsbogend@alpha.franken.de Cc: Naveen Naidu , linux-kernel-mentees@lists.linuxfoundation.org, skhan@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 6/6] MIPS: OCTEON: Remove redundant enable of RP error reporting Date: Mon, 4 Oct 2021 23:29:32 +0530 Message-Id: <66ad4e435d11d191ca71b491a15e1487e07fc204.1633369560.git.naveennaidu479@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time. Currently when CONFIG_PCIEAER=y, root port's error reporting is enabled by aer_enable_rootport() in the aer_probe() path. It is now no longer necessary for Octeon code to enable RP's error reporting since it's done when PCIe bus loads the AER service driver. Signed-off-by: Naveen Naidu --- arch/mips/pci/pci-octeon.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index b973fc464c21..239eec8ac942 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -114,24 +114,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); } - /* Find the Advanced Error Reporting capability */ - pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); - if (pos) { - /* - * Leave severity at HW default. This only controls if - * errors are reported as uncorrectable or - * correctable, not if the error is reported. - */ - /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ - - /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ - /* Report all errors to the root complex */ - pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, - PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - } - return 0; }