From patchwork Tue Oct 5 15:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17E28C4707E for ; Tue, 5 Oct 2021 16:09:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EBC1E6137C for ; Tue, 5 Oct 2021 16:09:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236419AbhJEQLR (ORCPT ); Tue, 5 Oct 2021 12:11:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234405AbhJEQLP (ORCPT ); Tue, 5 Oct 2021 12:11:15 -0400 X-Greylist: delayed 576 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 05 Oct 2021 09:09:24 PDT Received: from mail.marcansoft.com (marcansoft.com [IPv6:2a01:298:fe:f::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD2CAC06174E; Tue, 5 Oct 2021 09:09:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 650CB41EA7; Tue, 5 Oct 2021 15:59:46 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: arm: apple: Add apple,pmgr binding Date: Wed, 6 Oct 2021 00:59:17 +0900 Message-Id: <20211005155923.173399-2-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The PMGR block in Apple Silicon SoCs is responsible for SoC power management. There are two PMGRs in T8103, with different register layouts but compatible registers. In order to support this as well as future SoC generations with backwards-compatible registers, we declare these blocks as syscons and bind to individual registers in child nodes. Each register controls one SoC device. The respective apple compatibles are defined in case device-specific quirks are necessary in the future, but currently these nodes are expected to be bound by the generic syscon driver. Signed-off-by: Hector Martin Reviewed-by: Mark Kettenis . --- .../bindings/arm/apple/apple,pmgr.yaml | 74 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml new file mode 100644 index 000000000000..0304164e4140 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Power Manager (PMGR) + +maintainers: + - Hector Martin + +description: | + Apple SoCs include a PMGR block responsible for power management, + which can control various clocks, resets, power states, and + performance features. This node represents the PMGR as a syscon, + with sub-nodes representing individual features. + + Apple SoCs may have a secondary "mini-PMGR"; it is represented + separately in the device tree, but works the same way. + +select: + properties: + compatible: + contains: + enum: + - apple,t8103-pmgr + - apple,t8103-minipmgr + - apple,pmgr + + required: + - compatible + +properties: + $nodename: + pattern: "^power-management@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr + - apple,t8103-minipmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: true + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2 0x3b700000 0x0 0x14000>; + }; + + power-management@23b700000 { + compatible = "apple,t8103-minipmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2 0x3d280000 0x0 0xc000>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index abdcbcfef73d..d25598842d15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1719,6 +1719,7 @@ B: https://github.com/AsahiLinux/linux/issues C: irc://irc.oftc.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml +F: Documentation/devicetree/bindings/arm/apple/* F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ From patchwork Tue Oct 5 15:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC0FC4167B for ; Tue, 5 Oct 2021 16:09:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4791615E6 for ; Tue, 5 Oct 2021 16:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235543AbhJEQLQ (ORCPT ); Tue, 5 Oct 2021 12:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235588AbhJEQLP (ORCPT ); Tue, 5 Oct 2021 12:11:15 -0400 X-Greylist: delayed 576 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 05 Oct 2021 09:09:24 PDT Received: from mail.marcansoft.com (marcansoft.com [IPv6:2a01:298:fe:f::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD1BBC061749; Tue, 5 Oct 2021 09:09:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 617A2420CF; Tue, 5 Oct 2021 15:59:51 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: power: Add apple,pmgr-pwrstate binding Date: Wed, 6 Oct 2021 00:59:18 +0900 Message-Id: <20211005155923.173399-3-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This syscon child node represents a single SoC device controlled by the PMGR block. This layout allows us to declare all device power state controls (power/clock gating and reset) in the device tree, including dependencies, instead of hardcoding it into the driver. The register layout is uniform. Each pmgr-pwrstate node provides genpd and reset features, to be consumed by downstream device nodes. Future SoCs are expected to use backwards compatible registers, and the "apple,pmgr-pwrstate" represents any such interfaces (possibly with additional features gated by the more specific compatible), allowing them to be bound without driver updates. If a backwards incompatible change is introduced in future SoCs, it will require a new compatible, such as "apple,pmgr-pwrstate-v2". Signed-off-by: Hector Martin Reviewed-by: Mark Kettenis --- .../bindings/power/apple,pmgr-pwrstate.yaml | 117 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml new file mode 100644 index 000000000000..a14bf5f30ff0 --- /dev/null +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC PMGR Power States + +maintainers: + - Hector Martin + +allOf: + - $ref: "power-domain.yaml#" + +description: | + Apple SoCs include a PMGR block responsible for power management, + which can control various clocks, resets, power states, and + performance features. This binding describes the device power + state registers, which control power states and resets. + + Each instance of a power controller within the PMGR syscon node + represents a generic power domain provider, as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. + The provider controls a single SoC block. The power hierarchy is + represented via power-domains relationships between these nodes. + + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml + for the top-level PMGR node documentation. + + IP cores belonging to a power domain should contain a + "power-domains" property that is a phandle for the + power domain node representing the domain. + +properties: + $nodename: + pattern: "^power-controller@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr-pwrstate + - const: apple,pmgr-pwrstate + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + + "#reset-cells": + const: 0 + + power-domains: + description: + Reference to parent power domains. A domain may have multiple parents, + and all will be powered up when it is powered. + + apple,domain-name: + description: | + Specifies the name of the SoC device being controlled. This is used to + name the power/reset domains. + $ref: /schemas/types.yaml#/definitions/string + + apple,always-on: + description: | + Forces this power domain to always be powered up. + type: boolean + +required: + - compatible + - reg + - "#power-domain-cells" + - "#reset-cells" + - "apple,domain-name" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "sio"; + apple,always-on; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart0"; + power-domains = <&ps_uart_p>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d25598842d15..5fe53d9a2956 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1722,6 +1722,7 @@ F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/arm/apple/* F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/power/apple* F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c F: include/dt-bindings/interrupt-controller/apple-aic.h From patchwork Tue Oct 5 15:59:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A203C4167E for ; Tue, 5 Oct 2021 16:09:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9076617E3 for ; Tue, 5 Oct 2021 16:09:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235077AbhJEQLQ (ORCPT ); Tue, 5 Oct 2021 12:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235875AbhJEQLP (ORCPT ); Tue, 5 Oct 2021 12:11:15 -0400 Received: from mail.marcansoft.com (marcansoft.com [IPv6:2a01:298:fe:f::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB40CC061753; Tue, 5 Oct 2021 09:09:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 5C0CF3FA5E; Tue, 5 Oct 2021 15:59:56 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 3/7] soc: apple: Add driver for Apple PMGR power state controls Date: Wed, 6 Oct 2021 00:59:19 +0900 Message-Id: <20211005155923.173399-4-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Implements genpd and reset providers for downstream devices. Each instance of the driver binds to a single register and represents a single SoC power domain. The driver does not currently implement all features (auto-pm, clockgate-only state), but we declare the respective registers for documentation purposes. These features will be added as they become useful for downstream devices. This also creates the apple/soc tree and Kconfig submenu. Signed-off-by: Hector Martin Acked-by: Linus Walleij --- MAINTAINERS | 1 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/apple/Kconfig | 21 ++ drivers/soc/apple/Makefile | 2 + drivers/soc/apple/apple-pmgr-pwrstate.c | 281 ++++++++++++++++++++++++ 6 files changed, 307 insertions(+) create mode 100644 drivers/soc/apple/Kconfig create mode 100644 drivers/soc/apple/Makefile create mode 100644 drivers/soc/apple/apple-pmgr-pwrstate.c diff --git a/MAINTAINERS b/MAINTAINERS index 5fe53d9a2956..def5e05da2bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1725,6 +1725,7 @@ F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: Documentation/devicetree/bindings/power/apple* F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c +F: drivers/soc/apple/* F: include/dt-bindings/interrupt-controller/apple-aic.h F: include/dt-bindings/pinctrl/apple.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e8a30c4c5aec..a8562678c437 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -3,6 +3,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" source "drivers/soc/amlogic/Kconfig" +source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index a05e9fbcd3e0..adb30c2d4fea 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ +obj-$(CONFIG_ARCH_APPLE) += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig new file mode 100644 index 000000000000..271092b6aee7 --- /dev/null +++ b/drivers/soc/apple/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_APPLE || COMPILE_TEST + +menu "Apple SoC drivers" + +config APPLE_PMGR_PWRSTATE + tristate "Apple SoC PMGR power state control" + select REGMAP + select MFD_SYSCON + select PM_GENERIC_DOMAINS + select RESET_CONTROLLER + default ARCH_APPLE + help + The PMGR block in Apple SoCs provides high-level power state + controls for SoC devices. This driver manages them through the + generic power domain framework, and also provides reset support. + +endmenu + +endif diff --git a/drivers/soc/apple/Makefile b/drivers/soc/apple/Makefile new file mode 100644 index 000000000000..c114e84667e4 --- /dev/null +++ b/drivers/soc/apple/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_APPLE_PMGR_PWRSTATE) += apple-pmgr-pwrstate.o diff --git a/drivers/soc/apple/apple-pmgr-pwrstate.c b/drivers/soc/apple/apple-pmgr-pwrstate.c new file mode 100644 index 000000000000..a0338dbb29b8 --- /dev/null +++ b/drivers/soc/apple/apple-pmgr-pwrstate.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple SoC PMGR device power state driver + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define APPLE_PMGR_RESET BIT(31) +#define APPLE_PMGR_AUTO_ENABLE BIT(28) +#define APPLE_PMGR_PS_AUTO GENMASK(27, 24) +#define APPLE_PMGR_PARENT_OFF BIT(11) +#define APPLE_PMGR_DEV_DISABLE BIT(10) +#define APPLE_PMGR_WAS_CLKGATED BIT(9) +#define APPLE_PMGR_WAS_PWRGATED BIT(8) +#define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4) +#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) + +#define APPLE_PMGR_PS_ACTIVE 0xf +#define APPLE_PMGR_PS_CLKGATE 0x4 +#define APPLE_PMGR_PS_PWRGATE 0x0 + +#define APPLE_PMGR_PS_SET_TIMEOUT 100 +#define APPLE_PMGR_RESET_TIME 1 + +struct apple_pmgr_ps { + struct device *dev; + struct generic_pm_domain genpd; + struct reset_controller_dev rcdev; + struct regmap *regmap; + u32 offset; +}; + +#define genpd_to_apple_pmgr_ps(_genpd) container_of(_genpd, struct apple_pmgr_ps, genpd) +#define rcdev_to_apple_pmgr_ps(_rcdev) container_of(_rcdev, struct apple_pmgr_ps, rcdev) + +static int apple_pmgr_ps_set(struct generic_pm_domain *genpd, u32 pstate) +{ + int ret; + struct apple_pmgr_ps *ps = genpd_to_apple_pmgr_ps(genpd); + u32 reg; + + regmap_read(ps->regmap, ps->offset, ®); + + /* Resets are synchronous, and only work if the device is powered and clocked. */ + if (reg & APPLE_PMGR_RESET && pstate != APPLE_PMGR_PS_ACTIVE) + dev_err(ps->dev, "PS 0x%x: powering off with RESET active\n", ps->offset); + + reg &= ~(APPLE_PMGR_AUTO_ENABLE | APPLE_PMGR_WAS_CLKGATED | APPLE_PMGR_WAS_PWRGATED | + APPLE_PMGR_PS_TARGET); + reg |= FIELD_PREP(APPLE_PMGR_PS_TARGET, pstate); + + dev_dbg(ps->dev, "PS 0x%x: pwrstate = 0x%x: 0x%x\n", ps->offset, pstate, reg); + + regmap_write(ps->regmap, ps->offset, reg); + + ret = regmap_read_poll_timeout_atomic( + ps->regmap, ps->offset, reg, + (FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == pstate), 1, + APPLE_PMGR_PS_SET_TIMEOUT); + if (ret < 0) + dev_err(ps->dev, "PS 0x%x: Failed to reach power state 0x%x (now: 0x%x)\n", + ps->offset, pstate, reg); + return ret; +} + +static bool apple_pmgr_ps_is_active(struct apple_pmgr_ps *ps) +{ + u32 reg; + + regmap_read(ps->regmap, ps->offset, ®); + return FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == APPLE_PMGR_PS_ACTIVE; +} + +static int apple_pmgr_ps_power_on(struct generic_pm_domain *genpd) +{ + return apple_pmgr_ps_set(genpd, APPLE_PMGR_PS_ACTIVE); +} + +static int apple_pmgr_ps_power_off(struct generic_pm_domain *genpd) +{ + return apple_pmgr_ps_set(genpd, APPLE_PMGR_PS_PWRGATE); +} + +static int apple_pmgr_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + + mutex_lock(&ps->genpd.mlock); + + if (ps->genpd.status == GENPD_STATE_OFF) + dev_err(ps->dev, "PS 0x%x: asserting RESET while powered down\n", ps->offset); + + dev_dbg(ps->dev, "PS 0x%x: assert reset\n", ps->offset); + /* Quiesce device before asserting reset */ + regmap_set_bits(ps->regmap, ps->offset, APPLE_PMGR_DEV_DISABLE); + regmap_set_bits(ps->regmap, ps->offset, APPLE_PMGR_RESET); + + mutex_unlock(&ps->genpd.mlock); + + return 0; +} + +static int apple_pmgr_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + + mutex_lock(&ps->genpd.mlock); + + dev_dbg(ps->dev, "PS 0x%x: deassert reset\n", ps->offset); + regmap_clear_bits(ps->regmap, ps->offset, APPLE_PMGR_RESET); + regmap_clear_bits(ps->regmap, ps->offset, APPLE_PMGR_DEV_DISABLE); + + if (ps->genpd.status == GENPD_STATE_OFF) + dev_err(ps->dev, "PS 0x%x: RESET was deasserted while powered down\n", ps->offset); + + mutex_unlock(&ps->genpd.mlock); + + return 0; +} + +static int apple_pmgr_reset_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + int ret; + + ret = apple_pmgr_reset_assert(rcdev, id); + if (ret) + return ret; + + usleep_range(APPLE_PMGR_RESET_TIME, 2 * APPLE_PMGR_RESET_TIME); + + return apple_pmgr_reset_deassert(rcdev, id); +} + +static int apple_pmgr_reset_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + u32 reg; + + regmap_read(ps->regmap, ps->offset, ®); + + return !!(reg & APPLE_PMGR_RESET); +} + +const struct reset_control_ops apple_pmgr_reset_ops = { + .assert = apple_pmgr_reset_assert, + .deassert = apple_pmgr_reset_deassert, + .reset = apple_pmgr_reset_reset, + .status = apple_pmgr_reset_status, +}; + +static int apple_pmgr_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return 0; +} + +static int apple_pmgr_ps_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct apple_pmgr_ps *ps; + struct regmap *regmap; + struct of_phandle_iterator it; + int ret; + const char *name; + + regmap = syscon_node_to_regmap(node->parent); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ps = devm_kzalloc(dev, sizeof(*ps), GFP_KERNEL); + if (!ps) + return -ENOMEM; + + ps->dev = dev; + ps->regmap = regmap; + + ret = of_property_read_string(node, "apple,domain-name", &name); + if (ret < 0) { + dev_err(dev, "missing apple,domain-name property\n"); + return ret; + } + + ret = of_property_read_u32(node, "reg", &ps->offset); + if (ret < 0) { + dev_err(dev, "missing reg property\n"); + return ret; + } + + if (of_property_read_bool(node, "apple,always-on")) + ps->genpd.flags |= GENPD_FLAG_ALWAYS_ON; + + ps->genpd.name = name; + ps->genpd.power_on = apple_pmgr_ps_power_on; + ps->genpd.power_off = apple_pmgr_ps_power_off; + + ret = pm_genpd_init(&ps->genpd, NULL, !apple_pmgr_ps_is_active(ps)); + if (ret < 0) { + dev_err(dev, "pm_genpd_init failed\n"); + return ret; + } + + ret = of_genpd_add_provider_simple(node, &ps->genpd); + if (ret < 0) { + dev_err(dev, "of_genpd_add_provider_simple failed\n"); + return ret; + } + + of_for_each_phandle(&it, ret, node, "power-domains", "#power-domain-cells", -1) { + struct of_phandle_args parent, child; + + parent.np = it.node; + parent.args_count = of_phandle_iterator_args(&it, parent.args, MAX_PHANDLE_ARGS); + child.np = node; + child.args_count = 0; + ret = of_genpd_add_subdomain(&parent, &child); + + if (ret == -EPROBE_DEFER) { + of_node_put(parent.np); + goto err_remove; + } else if (ret < 0) { + dev_err(dev, "failed to add to parent domain: %d (%s -> %s)\n", + ret, it.node->name, node->name); + of_node_put(parent.np); + goto err_remove; + } + } + + pm_genpd_remove_device(dev); + + ps->rcdev.owner = THIS_MODULE; + ps->rcdev.nr_resets = 1; + ps->rcdev.ops = &apple_pmgr_reset_ops; + ps->rcdev.of_node = dev->of_node; + ps->rcdev.of_reset_n_cells = 0; + ps->rcdev.of_xlate = apple_pmgr_reset_xlate; + + ret = devm_reset_controller_register(dev, &ps->rcdev); + if (ret < 0) + goto err_remove; + + return 0; +err_remove: + of_genpd_del_provider(node); + pm_genpd_remove(&ps->genpd); + return ret; +} + +static const struct of_device_id apple_pmgr_ps_of_match[] = { + { .compatible = "apple,t8103-pmgr-pwrstate" }, + { .compatible = "apple,pmgr-pwrstate" }, + {} +}; + +MODULE_DEVICE_TABLE(of, apple_pmgr_ps_of_match); + +static struct platform_driver apple_pmgr_ps_driver = { + .probe = apple_pmgr_ps_probe, + .driver = { + .name = "apple-pmgr-pwrstate", + .of_match_table = apple_pmgr_ps_of_match, + }, +}; + +MODULE_AUTHOR("Hector Martin "); +MODULE_DESCRIPTION("PMGR power state driver for Apple SoCs"); +MODULE_LICENSE("GPL v2"); + +module_platform_driver(apple_pmgr_ps_driver); From patchwork Tue Oct 5 15:59:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20ABDC433EF for ; Tue, 5 Oct 2021 16:09:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0827261372 for ; Tue, 5 Oct 2021 16:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236435AbhJEQLT (ORCPT ); Tue, 5 Oct 2021 12:11:19 -0400 Received: from marcansoft.com ([212.63.210.85]:46724 "EHLO mail.marcansoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236390AbhJEQLR (ORCPT ); Tue, 5 Oct 2021 12:11:17 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 8EB4C41F4A; Tue, 5 Oct 2021 16:00:01 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 4/7] arm64: dts: apple: t8103: Rename clk24 to clkref Date: Wed, 6 Oct 2021 00:59:20 +0900 Message-Id: <20211005155923.173399-5-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org We now know that this frequency comes from the external reference oscillator and is used for various SoC blocks, and isn't just a random 24MHz clock, so let's call it something more appropriate. Signed-off-by: Hector Martin Reviewed-by: Mark Kettenis --- arch/arm64/boot/dts/apple/t8103.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index a1e22a2ea2e5..9f60f9e48ea0 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -95,11 +95,11 @@ timer { ; }; - clk24: clock-24m { + clkref: clock-ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; - clock-output-names = "clk24"; + clock-output-names = "clkref"; }; soc { @@ -120,7 +120,7 @@ serial0: serial@235200000 { * TODO: figure out the clocking properly, there may * be a third selectable clock. */ - clocks = <&clk24>, <&clk24>; + clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; From patchwork Tue Oct 5 15:59:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF138C43219 for ; Tue, 5 Oct 2021 16:09:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA7AC61371 for ; Tue, 5 Oct 2021 16:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236448AbhJEQLV (ORCPT ); Tue, 5 Oct 2021 12:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235875AbhJEQLR (ORCPT ); Tue, 5 Oct 2021 12:11:17 -0400 Received: from mail.marcansoft.com (marcansoft.com [IPv6:2a01:298:fe:f::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62656C06174E; Tue, 5 Oct 2021 09:09:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 8E61A4246F; Tue, 5 Oct 2021 16:00:06 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 5/7] arm64: dts: apple: t8103: Add the UART PMGR tree Date: Wed, 6 Oct 2021 00:59:21 +0900 Message-Id: <20211005155923.173399-6-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Note that the UART driver does not currently support runtime-pm, so this effectively always keeps the UART0 device on. However, this does clockgate all the other UARTs, as those are not currently instantiated. Signed-off-by: Hector Martin Reviewed-by: Mark Kettenis --- arch/arm64/boot/dts/apple/t8103.dtsi | 116 +++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 9f60f9e48ea0..63056ddc7ef7 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -122,6 +122,7 @@ serial0: serial@235200000 { */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -131,5 +132,120 @@ aic: interrupt-controller@23b100000 { interrupt-controller; reg = <0x2 0x3b100000 0x0 0x8000>; }; + + pmgr: power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio_busif: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "sio_busif"; + }; + + ps_sio: power-controller@1c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "sio"; + power-domains = <&ps_sio_busif>; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@278 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@280 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@288 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@290 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x290>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@298 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x298>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@2a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_uart7: power-controller@2a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart7"; + power-domains = <&ps_uart_p>; + }; + + ps_uart8: power-controller@2b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart8"; + power-domains = <&ps_uart_p>; + }; + }; }; }; From patchwork Tue Oct 5 15:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6A47C4332F for ; Tue, 5 Oct 2021 16:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90C3561354 for ; Tue, 5 Oct 2021 16:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236428AbhJEQLS (ORCPT ); Tue, 5 Oct 2021 12:11:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236399AbhJEQLR (ORCPT ); Tue, 5 Oct 2021 12:11:17 -0400 Received: from mail.marcansoft.com (marcansoft.com [IPv6:2a01:298:fe:f::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55D09C061749; Tue, 5 Oct 2021 09:09:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 8840642481; Tue, 5 Oct 2021 16:00:11 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 6/7] tty: serial: samsung_tty: Support runtime PM Date: Wed, 6 Oct 2021 00:59:22 +0900 Message-Id: <20211005155923.173399-7-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This allows idle UART devices to be suspended using the standard runtime-PM framework. The logic is modeled after stm32-usart. Signed-off-by: Hector Martin --- drivers/tty/serial/samsung_tty.c | 88 ++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 34 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index e2f49863e9c2..d68e3341adc6 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -40,6 +40,7 @@ #include #include #include +#include #include /* UART name and device definitions */ @@ -1381,31 +1382,49 @@ static void exynos_usi_init(struct uart_port *port) /* power power management control */ -static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, - unsigned int old) +static int __maybe_unused s3c24xx_serial_runtime_suspend(struct device *dev) { + struct uart_port *port = dev_get_drvdata(dev); struct s3c24xx_uart_port *ourport = to_ourport(port); int timeout = 10000; - ourport->pm_level = level; + while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) + udelay(100); - switch (level) { - case 3: - while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) - udelay(100); + if (!IS_ERR(ourport->baudclk)) + clk_disable_unprepare(ourport->baudclk); - if (!IS_ERR(ourport->baudclk)) - clk_disable_unprepare(ourport->baudclk); + clk_disable_unprepare(ourport->clk); + return 0; +}; - clk_disable_unprepare(ourport->clk); - break; +static int __maybe_unused s3c24xx_serial_runtime_resume(struct device *dev) +{ + struct uart_port *port = dev_get_drvdata(dev); + struct s3c24xx_uart_port *ourport = to_ourport(port); - case 0: - clk_prepare_enable(ourport->clk); + clk_prepare_enable(ourport->clk); - if (!IS_ERR(ourport->baudclk)) - clk_prepare_enable(ourport->baudclk); + if (!IS_ERR(ourport->baudclk)) + clk_prepare_enable(ourport->baudclk); + return 0; +}; + +static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, + unsigned int old) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + + ourport->pm_level = level; + switch (level) { + case UART_PM_STATE_OFF: + pm_runtime_mark_last_busy(port->dev); + pm_runtime_put_sync(port->dev); + break; + + case UART_PM_STATE_ON: + pm_runtime_get_sync(port->dev); exynos_usi_init(port); break; default: @@ -2282,18 +2301,15 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) } } + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + dev_dbg(&pdev->dev, "%s: adding port\n", __func__); uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); platform_set_drvdata(pdev, &ourport->port); - /* - * Deactivate the clock enabled in s3c24xx_serial_init_port here, - * so that a potential re-enablement through the pm-callback overlaps - * and keeps the clock enabled in this case. - */ - clk_disable_unprepare(ourport->clk); - if (!IS_ERR(ourport->baudclk)) - clk_disable_unprepare(ourport->baudclk); + pm_runtime_put_sync(&pdev->dev); ret = s3c24xx_serial_cpufreq_register(ourport); if (ret < 0) @@ -2309,8 +2325,14 @@ static int s3c24xx_serial_remove(struct platform_device *dev) struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); if (port) { + pm_runtime_get_sync(&dev->dev); + s3c24xx_serial_cpufreq_deregister(to_ourport(port)); uart_remove_one_port(&s3c24xx_uart_drv, port); + + pm_runtime_disable(&dev->dev); + pm_runtime_set_suspended(&dev->dev); + pm_runtime_put_noidle(&dev->dev); } uart_unregister_driver(&s3c24xx_uart_drv); @@ -2319,8 +2341,8 @@ static int s3c24xx_serial_remove(struct platform_device *dev) } /* UART power management code */ -#ifdef CONFIG_PM_SLEEP -static int s3c24xx_serial_suspend(struct device *dev) + +static int __maybe_unused s3c24xx_serial_suspend(struct device *dev) { struct uart_port *port = s3c24xx_dev_to_port(dev); @@ -2330,7 +2352,7 @@ static int s3c24xx_serial_suspend(struct device *dev) return 0; } -static int s3c24xx_serial_resume(struct device *dev) +static int __maybe_unused s3c24xx_serial_resume(struct device *dev) { struct uart_port *port = s3c24xx_dev_to_port(dev); struct s3c24xx_uart_port *ourport = to_ourport(port); @@ -2350,7 +2372,7 @@ static int s3c24xx_serial_resume(struct device *dev) return 0; } -static int s3c24xx_serial_resume_noirq(struct device *dev) +static int __maybe_unused s3c24xx_serial_resume_noirq(struct device *dev) { struct uart_port *port = s3c24xx_dev_to_port(dev); struct s3c24xx_uart_port *ourport = to_ourport(port); @@ -2420,16 +2442,14 @@ static int s3c24xx_serial_resume_noirq(struct device *dev) } static const struct dev_pm_ops s3c24xx_serial_pm_ops = { +#ifdef CONFIG_PM_SLEEP .suspend = s3c24xx_serial_suspend, .resume = s3c24xx_serial_resume, .resume_noirq = s3c24xx_serial_resume_noirq, +#endif + SET_RUNTIME_PM_OPS(s3c24xx_serial_runtime_suspend, + s3c24xx_serial_runtime_resume, NULL) }; -#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) - -#else /* !CONFIG_PM_SLEEP */ - -#define SERIAL_SAMSUNG_PM_OPS NULL -#endif /* CONFIG_PM_SLEEP */ /* Console code */ @@ -2924,7 +2944,7 @@ static struct platform_driver samsung_serial_driver = { .id_table = s3c24xx_serial_driver_ids, .driver = { .name = "samsung-uart", - .pm = SERIAL_SAMSUNG_PM_OPS, + .pm = &s3c24xx_serial_pm_ops, .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), }, }; From patchwork Tue Oct 5 15:59:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12537161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D96A1C433F5 for ; Tue, 5 Oct 2021 16:09:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9F0F6137C for ; Tue, 5 Oct 2021 16:09:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236358AbhJEQLP (ORCPT ); Tue, 5 Oct 2021 12:11:15 -0400 Received: from marcansoft.com ([212.63.210.85]:46700 "EHLO mail.marcansoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235197AbhJEQLP (ORCPT ); Tue, 5 Oct 2021 12:11:15 -0400 X-Greylist: delayed 575 seconds by postgrey-1.27 at vger.kernel.org; Tue, 05 Oct 2021 12:11:14 EDT Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 9D01C4248E; Tue, 5 Oct 2021 16:00:16 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Marc Zyngier , Rob Herring , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: apple: t8103: Add UART2 Date: Wed, 6 Oct 2021 00:59:23 +0900 Message-Id: <20211005155923.173399-8-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211005155923.173399-1-marcan@marcan.st> References: <20211005155923.173399-1-marcan@marcan.st> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This UART is connected to the debug port of the WLAN module. It is mostly useless, but makes for a good test case for runtime-pm without having to unbind the console from the main system UART. Signed-off-by: Hector Martin Reviewed-by: Mark Kettenis --- arch/arm64/boot/dts/apple/t8103-j274.dts | 5 +++++ arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index e0f6775b9878..16c5eb7f53b1 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -17,6 +17,7 @@ / { aliases { serial0 = &serial0; + serial2 = &serial2; }; chosen { @@ -43,3 +44,7 @@ memory@800000000 { &serial0 { status = "okay"; }; + +&serial2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 63056ddc7ef7..844ed7bd0451 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -126,6 +126,18 @@ serial0: serial@235200000 { status = "disabled"; }; + serial2: serial@235208000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35208000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart2>; + status = "disabled"; + }; + aic: interrupt-controller@23b100000 { compatible = "apple,t8103-aic", "apple,aic"; #interrupt-cells = <3>;