From patchwork Fri Oct 8 03:45:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 12544137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98740C433FE for ; Fri, 8 Oct 2021 03:46:00 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 4724B6120C; Fri, 8 Oct 2021 03:46:00 +0000 (UTC) Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 181D5610E7; Fri, 8 Oct 2021 03:46:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 181D5610E7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-f177.google.com with SMTP id q19so6559105pfl.4; Thu, 07 Oct 2021 20:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7DEKEwn1sYlj7MiLzk6fLL0vy4MseGtQcchsFCXbjxQ=; b=HuS8xXU9n3RP9Z8wRKHlz2xxxem//6yMnrYPm59Skz7x+qdISQYod8sdKRSgl3DjHx BRAyGuFd4NcXzd+nX0rXIncqskgHbHac5lQJRjydO+IyXoYMyP4/eWdIfRTSFxccvRmM WWeexgXuPwFmZeUvuyaReODqGp0Fnuv5FMwVByCZ01h4QnmOYlH1du1iApH6Rhvfyn7C cYpG4q+Yo55ImbnBVCWSrN2CRu2bY5a5TAxQIHq952bEsmniyJ1wl1n9R8L54nKZacEy rQfMSdc1GRePJtY/vPJ5Zms6T2ucyu0Em7Y4d08sRUs8rtmdKPY6WLYxllcEC85PgmQX WnNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7DEKEwn1sYlj7MiLzk6fLL0vy4MseGtQcchsFCXbjxQ=; b=adLKV2/KSfIfi5LQX6tcChZrpxhX7SZ54hFG1XB9FHuYbZO96FXL+QEBWcdGiSaiMQ DEu/NFqWsHYrGQb4J+16nzPfTejtftDLcqRC2r/if/ab5Pq6KGWP1UWfLdJv1FEgraz0 lImtQT4xsG7k+jVW13hUiPUkdqHaeZZ1xeffmEhbL7Ou3WcqDbqYkKtTxm56kxDKK7XY PubrI2rLJ6GG8LCU4TznR8s8FTCUdtHImH0+pgS65aVim+ESSTH5Lik7XcLaRG5jWY3v NbY9m5qsjiC83sHWkikmRgkP5zwg0uKWhs0MsCibAtDpJOT3F3wPMjpVvrk0kLOg73pZ kJkQ== X-Gm-Message-State: AOAM532PKi8X3QxWeprssQ5nQA+0DlqI4RMWmofxJE/WARF3BDZCCQNI 3gHCFmaSO8c3rgQc7NDxNQHu02U4AsQ= X-Google-Smtp-Source: ABdhPJyYZCr7OAVfyNM+Z8n7lEgEBUMJyQtz8tYm+zp2CgOO2iEtifROiJAfELasAfD60h1FegN+SQ== X-Received: by 2002:a63:d2:: with SMTP id 201mr2730054pga.400.1633664759558; Thu, 07 Oct 2021 20:45:59 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s3sm9253776pjr.1.2021.10.07.20.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 20:45:59 -0700 (PDT) From: Chunyan Zhang List-Id: To: soc@kernel.org, Arnd Bergmann , Mark Rutland , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH v2 1/2] dt-bindings: arm: Add bindings for Unisoc's UMS512 Date: Fri, 8 Oct 2021 11:45:32 +0800 Message-Id: <20211008034533.343167-2-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008034533.343167-1-zhang.lyra@gmail.com> References: <20211008034533.343167-1-zhang.lyra@gmail.com> MIME-Version: 1.0 From: Chunyan Zhang Added bindings for Unisoc's ums512-1h10 board and ums512 SoC. Signed-off-by: Chunyan Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sprd/sprd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml index 7b6ae3070396..2c12e571394b 100644 --- a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -30,6 +30,11 @@ properties: - sprd,sp9863a-1h10 - const: sprd,sc9863a + - items: + - enum: + - sprd,ums512-1h10 + - const: sprd,ums512 + additionalProperties: true ... From patchwork Fri Oct 8 03:45:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 12544139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54CB0C433EF for ; Fri, 8 Oct 2021 03:46:05 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 368C56103C; Fri, 8 Oct 2021 03:46:05 +0000 (UTC) Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A9A360FD7; Fri, 8 Oct 2021 03:46:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0A9A360FD7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-f53.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so6790209pjb.3; Thu, 07 Oct 2021 20:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/lgnpuRbfj1pckDEvg1BLjdxv7Br/AmzscEEMD2BLf0=; b=YiqBuidvPuCOthdgQrfUpkAqhXe0CXgtuNK6zdRqxqeF6aSiJYSwgudu7Xe5KqbL0d q6XexlWsHmJDx1xdNDyBJ7pjHRoNTLgL0mudjHDdUO9alICKtaF7L0k/dtESUVed2dMk XgvK1RJMXiHe2WLWr5fk9UQqlhtKJ5oEiGK0FuPcPvuJxmQJxQKj2LPdeTw4IOZQkjSt v9qzPJuufokbXQPwXDUudugDyi0Koc+c0kOVOQWFutYibjQ2a/xqiTpG3TX7zNMv6pAj aZTTJwT9Pej5LkLxAbMCSHZtI0ewVCZS892XamzUoi7MydWCz09rSTmcYuy22+XRyALz CwZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/lgnpuRbfj1pckDEvg1BLjdxv7Br/AmzscEEMD2BLf0=; b=cHa0hdKH1NNb9N3FP+Z2x11RcQ1/vz7CXAAzj16DFv7LJOcd24UORp2SIIOBuaIkhN bEc+mjf3cC3kQ9csF6R40vJi0qzmSgev9XIKT8Btr6/rIG6bZu68ARQICU6iVIyHCe2G Lli7HNBRRcWJQRep/CBwcbToQNZOWRHQArfK92oyLvP/xeEr7s1NsJAG7QrBX7IukyEW pvF0OWfymU9CCJpkDxj4HcVaRAhyoiMvRy9yWaUEPq0bvpq/n0ZR/MOZIsC+JVcTAwxe t1i30rE7k6EazEw0DVvDOXzsHgEg5XGbaLCcSkDiwOV1lwICanxs5jz5shby9KHaePKu D7dg== X-Gm-Message-State: AOAM533r1600R7ntX8mfYZ/7f2o8BupgIVipL+Hezfqglo5mfqiTslNb SJF1n+FsUIXX6vKcdU9QZWxxLfANoEw= X-Google-Smtp-Source: ABdhPJxjo0+2eay02cMfkwLu4kef9hzJmJFh9XA2pCtQ22stO8cITi3m8hApvk1glvMy/E8x9tvnIw== X-Received: by 2002:a17:90a:352:: with SMTP id 18mr9175969pjf.116.1633664764099; Thu, 07 Oct 2021 20:46:04 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s3sm9253776pjr.1.2021.10.07.20.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 20:46:03 -0700 (PDT) From: Chunyan Zhang List-Id: To: soc@kernel.org, Arnd Bergmann , Mark Rutland , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH v2 2/2] arm64: dts: Add support for Unisoc's UMS512 Date: Fri, 8 Oct 2021 11:45:33 +0800 Message-Id: <20211008034533.343167-3-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211008034533.343167-1-zhang.lyra@gmail.com> References: <20211008034533.343167-1-zhang.lyra@gmail.com> MIME-Version: 1.0 From: Chunyan Zhang Add basic DT to support Unisoc's UMS512, with this patch, the board ums512-1h10 can run into console. Signed-off-by: Chunyan Zhang Reported-by: kernel test robot --- arch/arm64/boot/dts/sprd/Makefile | 3 +- arch/arm64/boot/dts/sprd/sc2730.dtsi | 263 +++++++ arch/arm64/boot/dts/sprd/ums512-1h10.dts | 69 ++ arch/arm64/boot/dts/sprd/ums512.dtsi | 919 +++++++++++++++++++++++ 4 files changed, 1253 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/sprd/sc2730.dtsi create mode 100644 arch/arm64/boot/dts/sprd/ums512-1h10.dts create mode 100644 arch/arm64/boot/dts/sprd/ums512.dtsi diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile index f4f1f5148cc2..97522fb0bf66 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ sp9860g-1h10.dtb \ - sp9863a-1h10.dtb + sp9863a-1h10.dtb \ + ums512-1h10.dtb diff --git a/arch/arm64/boot/dts/sprd/sc2730.dtsi b/arch/arm64/boot/dts/sprd/sc2730.dtsi new file mode 100644 index 000000000000..88fa8eadd3fb --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sc2730.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc SC2730 PMIC dts file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +&adi_bus { + sc2730_pmic: pmic@0 { + compatible = "sprd,sc2730"; + reg = <0>; + spi-max-frequency = <26000000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + regulators@1800 { + compatible = "sprd,sc2730-regulator"; + reg = <0x1800>; + + vddcpu: DCDC_CPU { + regulator-name = "vddcpu"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddgpu: DCDC_GPU { + regulator-name = "vddgpu"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddcore: DCDC_CORE { + regulator-name = "vddcore"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddmodem: DCDC_MODEM { + regulator-name = "vddmodem"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddmem: DCDC_MEM { + regulator-name = "vddmem"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1593750>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddmemq: DCDC_MEMQ { + regulator-name = "vddmemq"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddgen0: DCDC_GEN0 { + regulator-name = "vddgen0"; + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <2410625>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddgen1: DCDC_GEN1 { + regulator-name = "vddgen1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1643750>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddsram: DCDC_SRAM { + regulator-name = "vddsram"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <1596875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + avdd18: LDO_AVDD18 { + regulator-name = "avdd18"; + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1805000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddrf18: LDO_VDDRF18 { + regulator-name = "vddrf18"; + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1805000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddcamio: LDO_VDDCAMIO { + regulator-name = "vddcamio"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1830000>; + regulator-ramp-delay = <25000>; + }; + + vddwcn: LDO_VDDWCN { + regulator-name = "vddwcn"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1845000>; + regulator-ramp-delay = <25000>; + }; + + vddcamd1: LDO_VDDCAMD1 { + regulator-name = "vddcamd1"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1365000>; + regulator-ramp-delay = <25000>; + }; + + vddcamd0: LDO_VDDCAMD0 { + regulator-name = "vddcamd0"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1365000>; + regulator-ramp-delay = <25000>; + }; + + vddrf1v25: LDO_VDDRF1V25 { + regulator-name = "vddrf1v25"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1365000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + avdd12: LDO_AVDD12 { + regulator-name = "avdd12"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1365000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddcama0: LDO_VDDCAMA0 { + regulator-name = "vddcama0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddcama1: LDO_VDDCAMA1 { + regulator-name = "vddcama1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddcammot: LDO_VDDCAMMOT { + regulator-name = "vddcammot"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddsim2: LDO_VDDSIM2 { + regulator-name = "vddsim2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddemmccore: LDO_VDDEMMCCORE { + regulator-name = "vddemmccore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddsdcore: LDO_VDDSDCORE { + regulator-name = "vddsdcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddsdio: LDO_VDDSDIO { + regulator-name = "vddsdio"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vdd28: LDO_VDD28 { + regulator-name = "vdd28"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddwifipa: LDO_VDDWIFIPA { + regulator-name = "vddwifipa"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vdd18_dcxo: LDO_VDD18_DCXO { + regulator-name = "vdd18_dcxo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + vddusb33: LDO_VDDUSB33 { + regulator-name = "vddusb33"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddldo0: LDO_VDDLDO0 { + regulator-name = "vddldo0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddldo1: LDO_VDDLDO1 { + regulator-name = "vddldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddldo2: LDO_VDDLDO2 { + regulator-name = "vddldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + + vddkpled: LDO_VDDKPLED { + regulator-name = "vddkpled"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-ramp-delay = <25000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/ums512-1h10.dts b/arch/arm64/boot/dts/sprd/ums512-1h10.dts new file mode 100644 index 000000000000..8722c3999ade --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512-1h10.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512-1h10 boards DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +/dts-v1/; + +#include +#include "ums512.dtsi" +#include "sc2730.dtsi" + +/ { + model = "Unisoc UMS512-1H10 Board"; + + compatible = "sprd,ums512-1h10", "sprd,ums512"; + + sprd,sc-id = <512 1 0x20000>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* SD card */ +&sdio0 { + status = "okay"; + bus-width = <4>; + no-sdio; + no-mmc; + sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>; + sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>; + sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>; + sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>; + vmmc-supply = <&vddsdcore>; + vqmmc-supply = <&vddsdio>; + sd-uhs-sdr104; + sd-uhs-sdr50; +}; + +/* EMMC storage */ +&sdio3 { + status = "okay"; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + cap-mmc-hw-reset; +}; diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi new file mode 100644 index 000000000000..028e17f8198e --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -0,0 +1,919 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512 SoC DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + CORE_PD: core-pd { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure PPI */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@12000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + reg = <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + interrupts = ; + }; + + ap_ahb_regs: syscon@20100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20100000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20100000 0x4000>; + + apahb_gate: clock-controller@0 { + compatible = "sprd,ums512-apahb-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pub_apb_regs: syscon@31050000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x31050000 0 0x9000>; + }; + + top_dvfs_apb_regs: syscon@322a0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x322a0000 0 0x8000>; + }; + + ap_intc0_regs: syscon@32310000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32310000 0 0x1000>; + }; + + ap_intc1_regs: syscon@32320000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32320000 0 0x1000>; + }; + + ap_intc2_regs: syscon@32330000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32330000 0 0x1000>; + }; + + ap_intc3_regs: syscon@32340000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32340000 0 0x1000>; + }; + + ap_intc4_regs: syscon@32350000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32350000 0 0x1000>; + }; + + ap_intc5_regs: syscon@32360000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32360000 0 0x1000>; + }; + + anlg_phy_g0_regs: syscon@32390000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32390000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x32390000 0x3000>; + + dpll0: clock-controller@0 { + compatible = "sprd,ums512-g0-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@323b0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323b0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323b0000 0x3000>; + + mpll1: clock-controller@0 { + compatible = "sprd,ums512-g2-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g3_regs: syscon@323c0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323c0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323c0000 0x3000>; + + pll1: clock-controller@0 { + compatible = "sprd,ums512-g3-pll"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_gc_regs: syscon@323e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323e0000 0x3000>; + + pll2: clock-controller@0 { + compatible = "sprd,ums512-gc-pll"; + reg = <0x0 0x100>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g10_regs: syscon@323f0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323f0000 0 0x3000>; + }; + + aon_apb_regs: syscon@327d0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327d0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327d0000 0x3000>; + + aonapb_gate: clock-controller@0 { + compatible = "sprd,ums512-aon-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pmu_apb_regs: syscon@327e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327e0000 0x3000>; + + pmu_gate: clock-controller@0 { + compatible = "sprd,ums512-pmu-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + audcp_apb_regs: syscon@3350d000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x3350d000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x3350d000 0x1000>; + + audcpapb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpapb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + audcp_ahb_regs: syscon@335e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x335e0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x335e0000 0x1000>; + + audcpahb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpahb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + gpu_apb_regs: syscon@60100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60100000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60100000 0x3000>; + + gpu_clk: clock-controller@0 { + compatible = "sprd,ums512-gpu-clk"; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + gpu_dvfs_apb_regs: syscon@60110000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60110000 0 0x3000>; + }; + + mm_ahb_regs: syscon@62200000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x62200000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x62200000 0x3000>; + + mm_gate: clock-controller@0 { + compatible = "sprd,ums512-mm-gate-clk"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71000000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71000000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71000000 0x3000>; + + apapb_gate: clock-controller@0 { + compatible = "sprd,ums512-apapb-gate"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_clk: clock-controller@20200000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0 0x20200000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@32080000 { + compatible = "sprd,ums512-aonapb-clk"; + reg = <0 0x32080000 0 0x1000>; + clocks = <&ext_26m>, <&ext_32k>, + <&ext_4m>, <&rco_100m>; + clock-names = "ext-26m", "ext-32k", + "ext-4m", "rco-100m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@62100000 { + compatible = "sprd,ums512-mm-clk"; + reg = <0 0x62100000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + /* SoC Funnel */ + funnel@3c002000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3c002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_soc_out_port: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_soc_in_port: endpoint { + remote-endpoint = + <&funnel_corinth_out_port>; + }; + }; + }; + }; + + /* SoC ETF */ + soc_etb: etb@3c003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3c003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&funnel_soc_out_port>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core3/4/5/7 */ + funnel@3e001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_lit_out_port: endpoint { + remote-endpoint = + <&corinth_etf_lit_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + /* AP-CPU ETF for little cores */ + etf@3e002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_lit_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_lit_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_lit_in: endpoint { + remote-endpoint = + <&funnel_corinth_lit_out_port>; + }; + }; + }; + }; + + /* AP-CPU ETF for big cores */ + etf@3e003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_big_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_big_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_big_in: endpoint { + remote-endpoint = + <&funnel_corinth_big_out_port>; + }; + }; + }; + }; + + /* Funnel to SoC */ + funnel@3e004000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e004000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_out_port: endpoint { + remote-endpoint = + <&funnel_soc_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_corinth_from_lit_in_port: endpoint { + remote-endpoint = <&corinth_etf_lit_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_corinth_from_big_in_port: endpoint { + remote-endpoint = <&corinth_etf_big_out>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core0/1/2/6 */ + funnel@3e005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e005000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_big_out_port: endpoint { + remote-endpoint = <&corinth_etf_big_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + }; + }; + + etm0: etm@3f040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f040000 0 0x1000>; + cpu = <&CPU0>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&funnel_core_in_port0>; + }; + }; + }; + }; + + etm1: etm@3f140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f140000 0 0x1000>; + cpu = <&CPU1>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&funnel_core_in_port1>; + }; + }; + }; + }; + + etm2: etm@3f240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f240000 0 0x1000>; + cpu = <&CPU2>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&funnel_core_in_port2>; + }; + }; + }; + }; + + etm3: etm@3f340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f340000 0 0x1000>; + cpu = <&CPU3>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&funnel_core_in_port3>; + }; + }; + }; + }; + + etm4: etm@3f440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f440000 0 0x1000>; + cpu = <&CPU4>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&funnel_core_in_port4>; + }; + }; + }; + }; + + etm5: etm@3f540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f540000 0 0x1000>; + cpu = <&CPU5>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&funnel_core_in_port5>; + }; + }; + }; + }; + + etm6: etm@3f640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f640000 0 0x1000>; + cpu = <&CPU6>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&funnel_core_in_port6>; + }; + }; + }; + }; + + etm7: etm@3f740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f740000 0 0x1000>; + cpu = <&CPU7>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&funnel_core_in_port7>; + }; + }; + }; + }; + + + apb@70000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x70000000 0x10000000>; + + uart0: serial@0 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@100000 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x100000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + }; + + ap-apb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdio0: sdio@71100000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x71100000 0 0x1000>; + interrupts = ; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_SDIO0_2X>, + <&apapb_gate CLK_SDIO0_EB>; + assigned-clocks = <&ap_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + + sdio3: sdio@71400000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x71400000 0 0x1000>; + interrupts = ; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apapb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + }; + + aon { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adi_bus: spi@32100000 { + compatible = "sprd,ums512-adi"; + reg = <0 0x32100000 0 0x100000>; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>, + <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>, + <35 0x19b8>, <39 0x19ac>; + }; + }; + }; + + ext_26m: ext-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_32k: ext-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: ext-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: rco-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; +};