From patchwork Thu Dec 13 09:34:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10728289 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BED31759 for ; Thu, 13 Dec 2018 09:35:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B50A28767 for ; Thu, 13 Dec 2018 09:35:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F2AC2BD20; Thu, 13 Dec 2018 09:35:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BB4912BD17 for ; Thu, 13 Dec 2018 09:35:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727236AbeLMJfU (ORCPT ); Thu, 13 Dec 2018 04:35:20 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8169 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727972AbeLMJfT (ORCPT ); Thu, 13 Dec 2018 04:35:19 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:35:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:17 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 13 Dec 2018 01:35:17 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:17 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:17 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 13 Dec 2018 01:35:17 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH V2 12/21] cpufreq: tegra124: do not handle the CPU rail Date: Thu, 13 Dec 2018 17:34:29 +0800 Message-ID: <20181213093438.29621-13-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693713; bh=cFkhAstfSy6edE2nU4IXZTM12YCmE+CLGBX/yRk0+KM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=SVjYnz3a0Y2QCK2LAde4VURux6fQl+94wCgpe+11rWohRRTOPRqFk6aAseOLHnfqT 9Rwm4lEGpSMrmK8prj6pgEm1S7zfeqLNrrLsPLf3rif9v6YYGGOCtluH+hh7i4AxT+ +GS9c2P+BRKusrmhaW3D1blR54ImuzNqFmYOytQeV5hSTRUkKKr6UNPRj2W4L3KRw6 xd1BHetWN5g/hhxhbdsj2S1FBE8NlAEkxeOm3wfogbn9I/4kHTgveK5BmJ5iyhPujv siBWQBnXy05Oa8KG3RlYR8ab0WDt/DIQd/VUMOryBuwHRMIuH0zQYa7PVVXPP5nkKN vF6xL4eJx46Dw== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra124 cpufreq driver has no information to handle the Vdd-CPU rail. So this driver shouldn't handle for the CPU clock switching from DFLL to other PLL clocks. It was designed to work on DFLL clock only, which handle the frequency/voltage scaling in the background. This patch removes the driver dependency of the CPU rail, as well as not allow it to be built as a module and remove the removal function. So it can keep working on DFLL clock. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Viresh Kumar --- *V2: - update the commit message since we change the driver not able to be built as a module and remove the removal function in V2 --- drivers/cpufreq/Kconfig.arm | 4 +-- drivers/cpufreq/tegra124-cpufreq.c | 41 ++---------------------------- 2 files changed, 4 insertions(+), 41 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 4e1131ef85ae..1d83b6e81222 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -261,8 +261,8 @@ config ARM_TEGRA20_CPUFREQ This adds the CPUFreq driver support for Tegra20 SOCs. config ARM_TEGRA124_CPUFREQ - tristate "Tegra124 CPUFreq support" - depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR + bool "Tegra124 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help This adds the CPUFreq driver support for Tegra124 SOCs. diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 43530254201a..a1bfde0a7950 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -22,11 +22,9 @@ #include #include #include -#include #include struct tegra124_cpufreq_priv { - struct regulator *vdd_cpu_reg; struct clk *cpu_clk; struct clk *pllp_clk; struct clk *pllx_clk; @@ -60,14 +58,6 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv) return ret; } -static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv) -{ - clk_set_parent(priv->cpu_clk, priv->pllp_clk); - clk_disable_unprepare(priv->dfll_clk); - regulator_sync_voltage(priv->vdd_cpu_reg); - clk_set_parent(priv->cpu_clk, priv->pllx_clk); -} - static int tegra124_cpufreq_probe(struct platform_device *pdev) { struct tegra124_cpufreq_priv *priv; @@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENODEV; - priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu"); - if (IS_ERR(priv->vdd_cpu_reg)) { - ret = PTR_ERR(priv->vdd_cpu_reg); - goto out_put_np; - } - priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); if (IS_ERR(priv->cpu_clk)) { ret = PTR_ERR(priv->cpu_clk); - goto out_put_vdd_cpu_reg; + goto out_put_np; } priv->dfll_clk = of_clk_get_by_name(np, "dfll"); @@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) platform_device_register_full(&cpufreq_dt_devinfo); if (IS_ERR(priv->cpufreq_dt_pdev)) { ret = PTR_ERR(priv->cpufreq_dt_pdev); - goto out_switch_to_pllx; + goto out_put_pllp_clk; } platform_set_drvdata(pdev, priv); return 0; -out_switch_to_pllx: - tegra124_cpu_switch_to_pllx(priv); out_put_pllp_clk: clk_put(priv->pllp_clk); out_put_pllx_clk: @@ -146,34 +128,15 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) clk_put(priv->dfll_clk); out_put_cpu_clk: clk_put(priv->cpu_clk); -out_put_vdd_cpu_reg: - regulator_put(priv->vdd_cpu_reg); out_put_np: of_node_put(np); return ret; } -static int tegra124_cpufreq_remove(struct platform_device *pdev) -{ - struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev); - - platform_device_unregister(priv->cpufreq_dt_pdev); - tegra124_cpu_switch_to_pllx(priv); - - clk_put(priv->pllp_clk); - clk_put(priv->pllx_clk); - clk_put(priv->dfll_clk); - clk_put(priv->cpu_clk); - regulator_put(priv->vdd_cpu_reg); - - return 0; -} - static struct platform_driver tegra124_cpufreq_platdrv = { .driver.name = "cpufreq-tegra124", .probe = tegra124_cpufreq_probe, - .remove = tegra124_cpufreq_remove, }; static int __init tegra_cpufreq_init(void) From patchwork Thu Dec 13 09:34:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10728293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 897DA1759 for ; Thu, 13 Dec 2018 09:35:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B5982B986 for ; Thu, 13 Dec 2018 09:35:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F6D62BD20; Thu, 13 Dec 2018 09:35:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26DA72B986 for ; Thu, 13 Dec 2018 09:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727995AbeLMJfV (ORCPT ); Thu, 13 Dec 2018 04:35:21 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1383 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727972AbeLMJfV (ORCPT ); Thu, 13 Dec 2018 04:35:21 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:35:16 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:20 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:35:20 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:20 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:20 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 13 Dec 2018 01:35:20 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH V2 13/21] cpufreq: tegra124: extend to support Tegra210 Date: Thu, 13 Dec 2018 17:34:30 +0800 Message-ID: <20181213093438.29621-14-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693716; bh=4yzhfUkePTBvZGp9INmReRUoVFQVTTytNBnf/LLfowQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=hRKWNmrrWT+gr/6lLhtXB8A82uhi+VirfU+qSUm33H3/CSlYjF4XPJPqBnJuk3KV7 JmkzjguJ5rLOVMHVpPMcVvejQdXHvkM1ig8LNHrohxudeZLWkkkaXVE+Oo6srEGDGR hdnm3Q85PLQRw79ZBDDFe+Xthri1JYpQK4oWQo/zeqJFs5QUInYHHnru6B1gynIJTt EbOyHaPcQ/IleueCpZAvkWm0VV+mSsYanOeiQ98/Ma1ntj7ExSKgryVO5XR5GcGiCz ljmWRkQupjrv3dzIbC82KABMMp6NoBgNoVdrRYoQxdamO1zKJgCXZhCI3fMsJtfNCy V5Pj51EEjf05Q== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra210 uses the same methodology as Tegra124 for CPUFreq controlling that based on DFLL clock. So extending this driver to support Tegra210. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Viresh Kumar Acked-by: Jon Hunter --- *V2: - add two ack tags --- drivers/cpufreq/tegra124-cpufreq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index a1bfde0a7950..ba3795e13ac6 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -144,7 +144,8 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; - if (!of_machine_is_compatible("nvidia,tegra124")) + if (!(of_machine_is_compatible("nvidia,tegra124") || + of_machine_is_compatible("nvidia,tegra210"))) return -ENODEV; /* From patchwork Thu Dec 13 09:34:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10728297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6222C14E2 for ; Thu, 13 Dec 2018 09:35:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5301928767 for ; Thu, 13 Dec 2018 09:35:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 473A02BD17; Thu, 13 Dec 2018 09:35:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED78128767 for ; Thu, 13 Dec 2018 09:35:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727928AbeLMJfY (ORCPT ); Thu, 13 Dec 2018 04:35:24 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1391 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbeLMJfX (ORCPT ); Thu, 13 Dec 2018 04:35:23 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:35:19 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:23 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 13 Dec 2018 01:35:23 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:22 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:22 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 13 Dec 2018 01:35:22 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH V2 14/21] cpufreq: dt-platdev: add Tegra210 to blacklist Date: Thu, 13 Dec 2018 17:34:31 +0800 Message-ID: <20181213093438.29621-15-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693719; bh=myKaNq/lxtBIg3zsUcICsHKnQS978HytGp7bzL1guLU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=XD1LWO97h/2F2SBPY+hdUU8nMwjg4T8mLYrKN4/OWdCS1ZSBsMVT6MBiRENEwVuyh lzFpSf2CX38VKHDpcQyAb5pzK7a6rdiRlN8RCIwks+DhVgTFjrodccJhFGqpKGzogy 9y8Jk1tNFPlz7zOLUPOKf6161hlhUHCKo/P9qQBebi9GinIQAKKMTraRp714kMMCjd Cz/o1qICAzRerDdG66lW54lC5FauCb1hD3Xx03dq7qerNePyTaIllPKQikqJrrVmMB WRZy5DQWW3IzkrWhekz5QJ1juksh0OEBGjEzGw1/iCxhoEPM44Z/754T2sVFqLx7U1 fkNurWqGI8/sQ== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra210 uses "tegra124-cpufreq" platform driver to register device data for "cpufreq-dt" driver. So add it in the blacklist for "cpufreq-dt-platdev" driver to drop that. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Viresh Kumar --- *V2: - new added in V2 --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index b1c5468dca16..47729a22c159 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -119,6 +119,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8176", }, { .compatible = "nvidia,tegra124", }, + { .compatible = "nvidia,tegra210", }, { .compatible = "qcom,apq8096", }, { .compatible = "qcom,msm8996", },