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Tue, 12 Oct 2021 06:39:41 -0700 (PDT) From: Neil Armstrong To: tomba@kernel.org Cc: linux-omap@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, Tomi Valkeinen , Neil Armstrong Subject: [PATCH] drm/omap: increase DSS5 max tv pclk to 192MHz Date: Tue, 12 Oct 2021 15:39:39 +0200 Message-Id: <20211012133939.2145462-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1828; i=narmstrong@baylibre.com; h=from:subject; bh=/IYAeOjznmFZKQtbyiNltXzbWx1SQSeSVXzsgL7Y0g0=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBhZY/kQXqtsmH1M5LcYhE+C3h0vv0cLeo6PfSgeey5 U5lfFqSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYWWP5AAKCRB33NvayMhJ0ULjD/ 9i46pV2OVbqvg0OYjwURSFxSkXeze5h2UGKeEFVc8PrCVBu29GY5r5cm/37QzZTkev7b9nwKYuKj7s LP9/sE6WZF0UDRjOmAyquo6Rh01Hh+bfFcaLF0U5mklpnmy59qPw+m11uYcAvxbsh72r6sPCyWLSks Wuaa65aenK06yHvx6Gq/YYWOML/1xcK/HSpnfMzjkHOwvkJpBdT8LE+i/UsBgoOG0p4PveG36yA4N0 sA2o1wqDOA4dIMvXj6NoG/dRwzzgUx1xnYlJIfBw+TCdSMja66I08mMzDwFHru9WvkJH5npk722cZ1 Dkiy7wr0YLOmBCI9j5twVpH1bGmKqPbKZ165fFOJkDSqiJDe7uaR6rVoCTnnCniCPAmRPi9e+dsBtC 9YWC9bAcUA9rJD/S3sHRrfQT41Y98XeK2ZdqPiHfX00MT8tWMgeiQfGnXQh50Qe0WhoJx36jv8K/O5 uzUu3fyUkHdDj0sorCg2cKS9SmnEmqBu3yc6lZaNPAy5zmemQUp894FmrPrgMCOrEdRVfBDSnlsVz4 1oFCBEG1lnNG/KFNqDrOnabaf+PSb849gbkWbIQj2mHKpJeRlaHyZJ8JlPENRZv/gJ8uYHeO5+bGLk yfJYPVIhghlOh57VX1ZwS+xsQbzv9rw8Goptklar80SmDswP3AxHOqcjqjIw== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tomi Valkeinen DSS5's maximum tv pclk rate (i.e. HDMI) is set to 186MHz, which comes from the TRM (DPLL_HDMI_CLK1 frequency must be lower than 186 MHz). To support DRA76's wide screen HDMI feature, we need to increase this maximum rate. Testing shows that the PLL seems to work fine even with ~240MHz clocks, and even the HDMI output at that clock is stable enough for monitors to show a picture. This holds true for all DRA7 and AM5 SoCs (and probably also for OMAP5). However, the highest we can go without big refactoring to the clocking code is 192MHz, as that is the DSS func clock we get from the PRCM. So, increase the max HDMI pixel clock to 192MHz for now, to allow some more 2k+ modes to work. This patch never had a clear confirmation from HW people, but this change stayed on production trees for multiple years without any report on an eventual breakage. Signed-off-by: Tomi Valkeinen Signed-off-by: Neil Armstrong --- drivers/gpu/drm/omapdrm/dss/dispc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Tomi, I slighly changed the commit message to point the fact this patch has been used in production fort years without any sign of breakage. Neil base-commit: e4e737bb5c170df6135a127739a9e6148ee3da82 diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 5619420cc2cc..3c4a4991e45a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -4458,7 +4458,7 @@ static const struct dispc_features omap54xx_dispc_feats = { .mgr_width_max = 4096, .mgr_height_max = 4096, .max_lcd_pclk = 170000000, - .max_tv_pclk = 186000000, + .max_tv_pclk = 192000000, .max_downscale = 4, .max_line_width = 2048, .min_pcd = 1,