From patchwork Tue Oct 12 16:41:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553165 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFAE4C433EF for ; Tue, 12 Oct 2021 16:41:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEDC8610E7 for ; Tue, 12 Oct 2021 16:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229606AbhJLQnv (ORCPT ); Tue, 12 Oct 2021 12:43:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:36776 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbhJLQnv (ORCPT ); Tue, 12 Oct 2021 12:43:51 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8479661074; Tue, 12 Oct 2021 16:41:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056909; bh=DgDwJyTpY2SNF+BMO6REe24ZpCAwiBRSvTJpcdEY/8A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qL3NsbQjWjjIEuH66WqB6s3YfxQ7FKVpEjbbj7jUpTgT0BxfLEh6OQY9m24uZVMKa PZ4YJGhUY2o1g4z95NRGZa/p8BC995+aRQIVoOeBEkQul9B7WoVTWMrOIm6MFHE7fU ZU45f0hpOJiiXke/2vlCJVLvzehPtmv4UYxwHgxtfqvb7n1OYORBiikN5Rf2/9lgRZ aPds+EXO8OWNOKYBIK2Vx9iJxGAlkIXPUNPOnV1z2l68u0B3lUkUWYSgL4i3/fDpuh CLuK5qRqftWtKORMSxod4WcnBSngESDp2CvU4mkLpacuDJj8LqFzXtCcSZZFHu4Jq6 D4rmp6UIPrwGA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= , Russell King Subject: [PATCH 01/14] PCI: pci-bridge-emul: Fix emulation of W1C bits Date: Tue, 12 Oct 2021 18:41:32 +0200 Message-Id: <20211012164145.14126-2-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pci_bridge_emul_conf_write() function correctly clears W1C bits in cfgspace cache, but it does not inform the underlying implementation about the clear request: the .write_op() method is given the value with these bits cleared. This is wrong if the .write_op() needs to know which bits were requested to be cleared. Fix the value to be passed into the .write_op() method to have requested W1C bits set, so that it can clear them. Both pci-bridge-emul users (mvebu and aardvark) are compatible with this change. Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Cc: stable@vger.kernel.org Cc: Russell King --- drivers/pci/pci-bridge-emul.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index fdaf86a888b7..db97cddfc85e 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -431,8 +431,21 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, /* Clear the W1C bits */ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); + /* Save the new value with the cleared W1C bits into the cfgspace */ cfgspace[reg / 4] = cpu_to_le32(new); + /* + * Clear the W1C bits not specified by the write mask, so that the + * write_op() does not clear them. + */ + new &= ~(behavior[reg / 4].w1c & ~mask); + + /* + * Set the W1C bits specified by the write mask, so that write_op() + * knows about that they are to be cleared. + */ + new |= (value << shift) & (behavior[reg / 4].w1c & mask); + if (write_op) write_op(bridge, reg, old, new, mask); From patchwork Tue Oct 12 16:41:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553167 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15D04C433F5 for ; Tue, 12 Oct 2021 16:41:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F316A610E8 for ; Tue, 12 Oct 2021 16:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231165AbhJLQnx (ORCPT ); Tue, 12 Oct 2021 12:43:53 -0400 Received: from mail.kernel.org ([198.145.29.99]:36790 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbhJLQnw (ORCPT ); Tue, 12 Oct 2021 12:43:52 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 11F38610CE; Tue, 12 Oct 2021 16:41:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056911; bh=t3kJPuFKbtd46Et3jtlinmUnjKCMUFRILo+kJP7wZmg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jqmUrPQbE5X+aRz+WjMDLfSlWo1VQvjiAtRD5aAqBsuG5H3/wGGhEJvbLT/lMPtDI kzk71hMIJV+sh0KGmmN0tP0cqCkxrrRhk9ICl3/qtL2nM9f3tnQgenPdZGpzN99Caj NDwBHv5ZowQJQq9HEgX/OmPDyXhrx402INuEsDCBJefSqhps8kXxwK7EP4DJS5sCdg ETj8FsOvUtmmfame2OqZWO1X8TW7Amw5fyvNbsH59pDJHx/qbnAsOCun8/kW6VYiyL wD46W/KE+a0Ov/tsHghlzWPqdH8p8HnFRFeIsIkt0VgkQP5MQ/7X8a7PDHejGdLGhA DQv50tuQqT9JQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 02/14] PCI: aardvark: Fix return value of MSI domain .alloc() method Date: Tue, 12 Oct 2021 18:41:33 +0200 Message-Id: <20211012164145.14126-3-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org MSI domain callback .alloc() (implemented by advk_msi_irq_domain_alloc() function) should return zero on success, since non-zero value indicates failure. When the driver was converted to generic MSI API in commit f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support"), it was converted so that it returns hwirq number. Fix this. Fixes: f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 10476c00b312..b45ff2911c80 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1138,7 +1138,7 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain, domain->host_data, handle_simple_irq, NULL, NULL); - return hwirq; + return 0; } static void advk_msi_irq_domain_free(struct irq_domain *domain, From patchwork Tue Oct 12 16:41:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553169 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0BC8C4332F for ; Tue, 12 Oct 2021 16:41:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A7318610A2 for ; Tue, 12 Oct 2021 16:41:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231442AbhJLQny (ORCPT ); Tue, 12 Oct 2021 12:43:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:36828 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbhJLQny (ORCPT ); Tue, 12 Oct 2021 12:43:54 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7159361076; Tue, 12 Oct 2021 16:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056912; bh=bVdFcbLnOJnY2aUH/T5B3G9D+/EQBtky0JV3WGLfMvQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ESFau0lJMz9VP4T0otjgKPBQQvVRfPaN3A9SfZS5wWzcEkEDycmj2PEGVH/wCi1TA n3MxF9zNLOwjHXs8ZzoZ5m5SftxS/kp2YPx5pjycN9ywqqZV7k7WmFnx2RDTspJ6R2 IUonKgT/IiFNl5w7Y6FlrunTekcXZedM3Y/y8B8rqFtqvju3tn0CkoURFhavp2lHy8 f1VsDrtNUze9XMlUODZGw19Nj6v5mAH0TQ9DPFpRDjyWC+AJS9wQZ7bLTqyIAR5uzy 31umG1rpMn4nIFZp/092xrB1nVL8Q1dOlemuo8FA0CigoJOJWATTJsC2e4aYoPLi9x HMF4PZJwB7vcw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 03/14] PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG Date: Tue, 12 Oct 2021 18:41:34 +0200 Message-Id: <20211012164145.14126-4-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower 8 bits. Fix reading content of this register and add a comment describing the access to this register. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index b45ff2911c80..389ebba1dd9b 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -119,6 +119,7 @@ #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) +#define PCIE_MSI_DATA_MASK GENMASK(15, 0) /* PCIe window configuration */ #define OB_WIN_BASE_ADDR 0x4c00 @@ -1319,8 +1320,12 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; + /* + * msi_idx contains bits [4:0] of the msi_data and msi_data + * contains 16bit MSI interrupt number + */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; + msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; generic_handle_irq(msi_data); } From patchwork Tue Oct 12 16:41:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553171 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E860C433EF for ; Tue, 12 Oct 2021 16:41:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04503610C7 for ; Tue, 12 Oct 2021 16:41:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231614AbhJLQn4 (ORCPT ); Tue, 12 Oct 2021 12:43:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:36874 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbhJLQnz (ORCPT ); Tue, 12 Oct 2021 12:43:55 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id CF14A61050; Tue, 12 Oct 2021 16:41:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056913; bh=F62u5JCB/OkusKcNy5U8DqRNP/vRfmbS9D4keVux1QM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A9A7spXJzvKAZe8i8qVyFLX9I+fEnesQ12M3rHJP3RUzqzJmjP+InCC0dpZp56jK2 VlBVidCd4HOzgLlkxlnvdXQdfrt9bitxFr8aIAw7BQnds1vAzGPOx1HxZZ4QUOq0VW PSIsDOGbwrRD8myu1wIGpOfJOA9RAJb2mDKIAFE+tnTGcHtv3OQ2iSG3ggv/Kj3lsE KWI0Q26mVDX0Exmy+3FvBpcp49z5wGbIYPobUGf8Hzt2gGizL1HMbFZMVyAW8i4y4J 9mB0zaMcTjZmIhOlhGyBBXYs+LEOBmPIUbADjWwD8AOJ3QgbrX5TcBTWuwcN8DHW2C Uv+yEL+oxdYkw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 04/14] PCI: aardvark: Fix support for MSI interrupts Date: Tue, 12 Oct 2021 18:41:35 +0200 Message-Id: <20211012164145.14126-5-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark hardware supports Multi-MSI and MSI_FLAG_MULTI_PCI_MSI is already set for the MSI chip. But when allocating MSI interrupt numbers for Multi-MSI, the numbers need to be properly aligned, otherwise endpoint devices send MSI interrupt with incorrect numbers. Fix this issue by using function bitmap_find_free_region() instead of bitmap_find_next_zero_area(). To ensure that aligned MSI interrupt numbers are used by endpoint devices, we cannot use Linux virtual irq numbers (as they are random and not properly aligned). Instead we need to use the aligned hwirq numbers. Properly map Linux virtual irq numbers and hwirq MSI inner domain numbers in advk_msi_irq_compose_msi_msg() and advk_pcie_handle_msi(). This change fixes receiving MSI interrupts on Armada 3720 boards and allows using NVMe disks which use Multi-MSI feature with 3 interrupts. Without this NVMe disks freeze booting as linux nvme-core.c is waiting 60s for an interrupt. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- drivers/pci/controller/pci-aardvark.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 389ebba1dd9b..4f232ee1f115 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1106,7 +1106,7 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, msg->address_lo = lower_32_bits(msi_msg); msg->address_hi = upper_32_bits(msi_msg); - msg->data = data->irq; + msg->data = data->hwirq; } static int advk_msi_set_affinity(struct irq_data *irq_data, @@ -1123,15 +1123,11 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain, int hwirq, i; mutex_lock(&pcie->msi_used_lock); - hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, - 0, nr_irqs, 0); - if (hwirq >= MSI_IRQ_NUM) { - mutex_unlock(&pcie->msi_used_lock); - return -ENOSPC; - } - - bitmap_set(pcie->msi_used, hwirq, nr_irqs); + hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, + order_base_2(nr_irqs)); mutex_unlock(&pcie->msi_used_lock); + if (hwirq < 0) + return -ENOSPC; for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, hwirq + i, @@ -1149,7 +1145,7 @@ static void advk_msi_irq_domain_free(struct irq_domain *domain, struct advk_pcie *pcie = domain->host_data; mutex_lock(&pcie->msi_used_lock); - bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); + bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); mutex_unlock(&pcie->msi_used_lock); } @@ -1311,6 +1307,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) { u32 msi_val, msi_mask, msi_status, msi_idx; u16 msi_data; + int virq; msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); @@ -1326,7 +1323,11 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; - generic_handle_irq(msi_data); + virq = irq_find_mapping(pcie->msi_inner_domain, msi_data); + if (virq) + generic_handle_irq(virq); + else + dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data); } advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, From patchwork Tue Oct 12 16:41:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553173 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F2B0C433F5 for ; Tue, 12 Oct 2021 16:41:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 599A4610CE for ; Tue, 12 Oct 2021 16:41:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231665AbhJLQn5 (ORCPT ); Tue, 12 Oct 2021 12:43:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:36900 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbhJLQn4 (ORCPT ); Tue, 12 Oct 2021 12:43:56 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 38307610C9; Tue, 12 Oct 2021 16:41:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056915; bh=POaxQMsFYmmfSe6N1OHY94F+jXEsjfJZ3iztSXITKYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NHaBCv4tx1YBy6ElPhZpG6j4p1VYXN2LqBm6cejtkk0DBZ+s05Ra+wJ0HTK+bjnfm FJpoeZxMLnxz5oxHdi+69O55gw8OzY3kKustHDCRtA0Su3JIcU5FU/2sf5LJ/naRJ6 pgssM1cN45DL/wCmynOT7UihUTqIrvZot0Enj1pnwFij83g1+oDsNsWiT4Qa1p8EcH w/4OOFojS2WLfto3fvJKDWCCY7wcOsnXi+a01KP/qtzqsLQGKhocKT1wrx0CJEX6ka /zPd37Zfh+WsfJ7wlIKhaYkiFYcxDUxREjnHGOTzLq12pk8D2fWi2RhaK4MvB1K3cu 3Io1M+Fodn1GQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 05/14] PCI: aardvark: Fix reading MSI interrupt number Date: Tue, 12 Oct 2021 18:41:36 +0200 Message-Id: <20211012164145.14126-6-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár In advk_pcie_handle_msi() the authors expect that when bit i in the W1C register PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is updated to contain the MSI number corresponding to index i. Experiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG always contains the number of the last received MSI, overall. Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt number. Since Aardvark already forbids more than 32 interrupts and uses own allocated hwirq numbers, the msi_idx already corresponds to the received MSI number. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- Previous patches also touch PCIE_MSI_PAYLOAD_REG (adding comments, fixing reading of the register) and now we are removing it's usage completely. This is because we wanted the patches to be atomic and for the kernel to contain the explanation and comments in it's history. --- drivers/pci/controller/pci-aardvark.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 4f232ee1f115..735fd70e8dc3 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1306,7 +1306,6 @@ static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) static void advk_pcie_handle_msi(struct advk_pcie *pcie) { u32 msi_val, msi_mask, msi_status, msi_idx; - u16 msi_data; int virq; msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); @@ -1317,17 +1316,13 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; - /* - * msi_idx contains bits [4:0] of the msi_data and msi_data - * contains 16bit MSI interrupt number - */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; - virq = irq_find_mapping(pcie->msi_inner_domain, msi_data); + + virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); if (virq) generic_handle_irq(virq); else - dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data); + dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); } advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, From patchwork Tue Oct 12 16:41:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553175 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BDA5C433EF for ; Tue, 12 Oct 2021 16:41:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08190610D1 for ; Tue, 12 Oct 2021 16:41:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230148AbhJLQn6 (ORCPT ); Tue, 12 Oct 2021 12:43:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:36932 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231671AbhJLQn6 (ORCPT ); Tue, 12 Oct 2021 12:43:58 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 95BB961076; Tue, 12 Oct 2021 16:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056916; bh=hea+1UVi3ohfhJZI4mMcaUDQQxTJgXwy3BlfutwNhOc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TEqkI6uaVskBxuedI3jhG7Sql1g5tni1UIO3alo9nIb0VjA8gdTxC2KPlmoC20QMl L4HJ3LpnlmdJ4TRJLZwDWC6V+fMHOzTwBN2VWHWVdVKJ8w7wd9EwzJEoKuBc26+U1S 6bpATiZYSFqMWS/hKzmynEDYXxi0lV5Q2KFaeLw/Vcz3p51ZNGMQcUuSysrGMq6dCp cw9XM1/oF23ONtmCMyu/SlAEUy65UZHBVylRMEZKRDNZGlDjbnYpaOMlVaT8OktB6X Id2q9+EfDRidOgGtQ9joV2qW4h8n7df4cOsNI2InsbUEqaJIVZ19F1y3Fk+32tgtVO XdfbvEgXE3XiQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 06/14] PCI: aardvark: Clear all MSIs at setup Date: Tue, 12 Oct 2021 18:41:37 +0200 Message-Id: <20211012164145.14126-7-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT). Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts. Use this new mask in advk_pcie_handle_msi(); Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 735fd70e8dc3..a5fbe24b9612 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -118,6 +118,7 @@ #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) +#define PCIE_MSI_ALL_MASK GENMASK(31, 0) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) #define PCIE_MSI_DATA_MASK GENMASK(15, 0) @@ -548,6 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Clear all interrupts */ + advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); @@ -560,7 +562,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); /* Unmask all MSIs */ - advk_writel(pcie, 0, PCIE_MSI_MASK_REG); + advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); /* Enable summary interrupt for GIC SPI source */ reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); @@ -1310,7 +1312,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); - msi_status = msi_val & ~msi_mask; + msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK); for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { if (!(BIT(msi_idx) & msi_status)) From patchwork Tue Oct 12 16:41:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553177 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A80F0C433FE for ; Tue, 12 Oct 2021 16:41:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CCE3610D1 for ; Tue, 12 Oct 2021 16:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231672AbhJLQoA (ORCPT ); Tue, 12 Oct 2021 12:44:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:36950 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231671AbhJLQn7 (ORCPT ); Tue, 12 Oct 2021 12:43:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id F31E3610CE; Tue, 12 Oct 2021 16:41:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056918; bh=6aKJnxb/5GzRqLg8XGJw3pURzhC3OIpyXVGjTtt4WKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sU0iv5ap1INfyzrd6jct7YRd7dcdfbwOEkINbtwLACheCqcS/VtG7HujAEMcI3YIA HxFO/LvVgRwx834Ul5O9jto6O7jQCzDFtFgovPbMr350kF0MO++n7vTADLSZ1qHQvs 6FFPoKJEsfPmRFMY7U0a/ToLF6IqM9htOVNmxO44Q7oRLb6WvmbVEW5f8hTUaacr+j 4E1yEOzRoi01ut3CuW6jDgZSPgLzKDPUyHhpxrkUjSMA2LunjuXq9ibiKyp8UyC1ry /RbG0jDOLeZLgO234eEzkR2M3Od2eNbuJwAmDgt1lp6ka7+59eR3J6LFxK8z05CK5b Zt55wzsRPWdmA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 07/14] PCI: aardvark: Refactor unmasking summary MSI interrupt Date: Tue, 12 Oct 2021 18:41:38 +0200 Message-Id: <20211012164145.14126-8-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Refactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt so that it corresponds to the comments: - first mask all ISR0/1 - then unmask all MSIs - then unmask summary MSI interrupt Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index a5fbe24b9612..ab0a0864a300 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -555,15 +555,17 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); /* Disable All ISR0/1 Sources */ - reg = PCIE_ISR0_ALL_MASK; - reg &= ~PCIE_ISR0_MSI_INT_PENDING; - advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); - + advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); /* Unmask all MSIs */ advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); + /* Unmask summary MSI interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_MSI_INT_PENDING; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Enable summary interrupt for GIC SPI source */ reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); From patchwork Tue Oct 12 16:41:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553179 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8954C433F5 for ; Tue, 12 Oct 2021 16:42:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91758610C7 for ; Tue, 12 Oct 2021 16:42:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231682AbhJLQoB (ORCPT ); Tue, 12 Oct 2021 12:44:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:36970 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231671AbhJLQoB (ORCPT ); Tue, 12 Oct 2021 12:44:01 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5C9C8610C9; Tue, 12 Oct 2021 16:41:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056919; bh=JqILMU+QlYEBDXSATdbxuGjGipcrGzzPsX1jiWQpEfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HwT0wcrtH1vmhlc0MRL36gSSScEa9oBDEdnUFSDAD/wwAQc1qFLfxSb2r+8ux7K6b 9vydZ5u2oaG/36SKHXG1PBdnzhSFU2/7/2VBVnVuz9rli5I3raArTqv+wuoI9GjxIu IeSDZZZR/9rOjlveoHF/7oeA4bj618o1e8x8brkHV1heuSVxgj3Fjw4v8J390SzQ6N +fAYrCc6pIHK34BmpMiSvjIV5irZ2vWVSNzDfL+RcKmVTXXFf11K3J+tDJYc3O6UAd I/WL5gpNRxgbQb0oY808FJciDcY7dUvgeUhKqVHVXWT9eUgr9imJrUAgROfH2ow4cM jmzmdTvEoVahA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 08/14] PCI: aardvark: Fix masking MSI interrupts Date: Tue, 12 Oct 2021 18:41:39 +0200 Message-Id: <20211012164145.14126-9-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár We should not unmask MSIs at setup, but only when kernel asks for them to be unmasked. At setup, mask all MSIs, and implement IRQ chip callbacks for masking and unmasking particular MSIs. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- drivers/pci/controller/pci-aardvark.c | 52 ++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ab0a0864a300..1adb4c4b11b5 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -282,6 +282,7 @@ struct advk_pcie { struct irq_domain *msi_inner_domain; struct irq_chip msi_bottom_irq_chip; struct irq_chip msi_irq_chip; + raw_spinlock_t msi_irq_lock; struct msi_domain_info msi_domain_info; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; @@ -554,12 +555,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - /* Disable All ISR0/1 Sources */ + /* Disable All ISR0/1 and MSI Sources */ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); - - /* Unmask all MSIs */ - advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); + advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); /* Unmask summary MSI interrupt */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); @@ -1119,6 +1118,46 @@ static int advk_msi_set_affinity(struct irq_data *irq_data, return -EINVAL; } +static void advk_msi_irq_mask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask |= BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_irq_unmask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask &= ~BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_top_irq_mask(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void advk_msi_top_irq_unmask(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + static int advk_msi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) @@ -1213,6 +1252,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) struct msi_domain_info *msi_di; phys_addr_t msi_msg_phys; + raw_spin_lock_init(&pcie->msi_irq_lock); mutex_init(&pcie->msi_used_lock); bottom_ic = &pcie->msi_bottom_irq_chip; @@ -1220,9 +1260,13 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) bottom_ic->name = "MSI"; bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; bottom_ic->irq_set_affinity = advk_msi_set_affinity; + bottom_ic->irq_mask = advk_msi_irq_mask; + bottom_ic->irq_unmask = advk_msi_irq_unmask; msi_ic = &pcie->msi_irq_chip; msi_ic->name = "advk-MSI"; + msi_ic->irq_mask = advk_msi_top_irq_mask; + msi_ic->irq_unmask = advk_msi_top_irq_unmask; msi_di = &pcie->msi_domain_info; msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | From patchwork Tue Oct 12 16:41:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553181 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DED21C433FE for ; Tue, 12 Oct 2021 16:42:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C47A4610D1 for ; Tue, 12 Oct 2021 16:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231701AbhJLQoC (ORCPT ); Tue, 12 Oct 2021 12:44:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:37018 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231683AbhJLQoC (ORCPT ); Tue, 12 Oct 2021 12:44:02 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id BA6DB61076; Tue, 12 Oct 2021 16:41:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056920; bh=N7XzERkm3Zs23AIjqOmwEXCh5Z8xqCFEJtYZcRin6gU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JbY6unhBFz+aii0XSYgEtHEu0+0+OGBc9gZQg6v8oQm/MNmtQfuV02GZBVJW905M2 15Ftz5YU+dlvNtVkyA9cvtqLZI3r7/qB48yc8mLJ3Ug8Mtx7OT1q6N8mEJ/OiBUHgq nOyv9VnApjakPN/rWM+tSq+X7bgvyyzNnHc2ez7wXMANejfpGq46e5UIWC2LPZEU3H 07mCoRvLiQgzRa66o5PvNJngLZa/yXwtYTRBvj3g3XI5HtG0bdGYYLlZ8TLPYwDoqM AQaD3o7vm47OShdQ+u7+vZciw+MSBadFkEU33KViMDBzDZy9CkBk6ZO20g2uX4H/2t RDEz+iY4PMj0A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 09/14] PCI: aardvark: Fix setting MSI address Date: Tue, 12 Oct 2021 18:41:40 +0200 Message-Id: <20211012164145.14126-10-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár MSI address for receiving MSI interrupts needs to be correctly set before enabling processing of MSI interrupts. Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG from advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before enabling PCIE_CORE_CTRL2_MSI_ENABLE. After this we can remove the now unused member msi_msg, which was used only for MSI doorbell address. MSI address can be any address which cannot be used to DMA to. So change it to the address of the main struct advk_pcie. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Acked-by: Marc Zyngier Signed-off-by: Marek Behún Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 1adb4c4b11b5..b703b271c6b1 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -286,7 +286,6 @@ struct advk_pcie { struct msi_domain_info msi_domain_info; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; - u16 msi_msg; int link_gen; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; @@ -481,6 +480,7 @@ static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) static void advk_pcie_setup_hw(struct advk_pcie *pcie) { + phys_addr_t msi_addr; u32 reg; int i; @@ -544,6 +544,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= LANE_COUNT_1; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* Set MSI address */ + msi_addr = virt_to_phys(pcie); + advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); + advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); + /* Enable MSI */ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg |= PCIE_CORE_CTRL2_MSI_ENABLE; @@ -1105,10 +1110,10 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); - phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); + phys_addr_t msi_addr = virt_to_phys(pcie); - msg->address_lo = lower_32_bits(msi_msg); - msg->address_hi = upper_32_bits(msi_msg); + msg->address_lo = lower_32_bits(msi_addr); + msg->address_hi = upper_32_bits(msi_addr); msg->data = data->hwirq; } @@ -1250,7 +1255,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) struct device_node *node = dev->of_node; struct irq_chip *bottom_ic, *msi_ic; struct msi_domain_info *msi_di; - phys_addr_t msi_msg_phys; raw_spin_lock_init(&pcie->msi_irq_lock); mutex_init(&pcie->msi_used_lock); @@ -1273,13 +1277,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) MSI_FLAG_MULTI_PCI_MSI; msi_di->chip = msi_ic; - msi_msg_phys = virt_to_phys(&pcie->msi_msg); - - advk_writel(pcie, lower_32_bits(msi_msg_phys), - PCIE_MSI_ADDR_LOW_REG); - advk_writel(pcie, upper_32_bits(msi_msg_phys), - PCIE_MSI_ADDR_HIGH_REG); - pcie->msi_inner_domain = irq_domain_add_linear(NULL, MSI_IRQ_NUM, &advk_msi_domain_ops, pcie); From patchwork Tue Oct 12 16:41:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553183 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 980B5C4332F for ; Tue, 12 Oct 2021 16:42:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 81211610C7 for ; Tue, 12 Oct 2021 16:42:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231671AbhJLQoE (ORCPT ); Tue, 12 Oct 2021 12:44:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:37050 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231683AbhJLQoD (ORCPT ); Tue, 12 Oct 2021 12:44:03 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2425661050; Tue, 12 Oct 2021 16:42:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056922; bh=BfB4Eyv4w7WVLqCssx7tl6Wbemp0+DEE9PVBGtT/asg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K6o4ZN9sSZBtSIxP73/qLJL7yCng1XyRyj5SlpJD26KU0T/I/avEZ0rH71vlRgJG5 ry/POhlvodxI0Rth/eivjxD56/d8jByPMmxT21/I4K8HmQKCXbzcTR/nhevzYvbIxc Kvd+GqbEz0v32kLS7i2xZ8ALsRz4OZ2wHkzvRymAkQsXmhqRwuqjQ6HaY5t4smVAUb Qin17YzhNAbpMQTYPcIE6/bLuwfqwkWj7gmxXz6uj2I1pvIBMGZieC+bjMgTNDd1Oc pL8SJq2MvTCDxEyJipHFpKpZ6mTWTm2jWn9jl3rbuVVgXYipuVqr0k4MSg31CDafHx 7AsZV5G15FW5g== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 10/14] PCI: aardvark: Enable MSI-X support Date: Tue, 12 Oct 2021 18:41:41 +0200 Message-Id: <20211012164145.14126-11-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár According to PCI 3.0 specification, sending both MSI and MSI-X interrupts is done by DWORD memory write operation to doorbell message address. The write operation for MSI has zero upper 16 bits and the MSI interrupt number in the lower 16 bits, while the write operation for MSI-X contains a 32-bit value from MSI-X table. Since the driver only uses interrupt numbers from range 0..31, the upper 16 bits of the DWORD memory write operation to doorbell message address are zero even for MSI-X interrupts. Thus we can enable MSI-X interrupts. Testing proves that kernel can correctly receive MSI-X interrupts from PCIe cards which supports both MSI and MSI-X interrupts. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index b703b271c6b1..337b61508799 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1274,7 +1274,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) msi_di = &pcie->msi_domain_info; msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI; + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX; msi_di->chip = msi_ic; pcie->msi_inner_domain = From patchwork Tue Oct 12 16:41:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553185 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 231F6C433EF for ; Tue, 12 Oct 2021 16:42:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 022AC6023B for ; Tue, 12 Oct 2021 16:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231691AbhJLQoG (ORCPT ); Tue, 12 Oct 2021 12:44:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:37074 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231718AbhJLQoF (ORCPT ); Tue, 12 Oct 2021 12:44:05 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8175F61074; Tue, 12 Oct 2021 16:42:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056923; bh=MJeu2fzW5NBLKHSNKakfjSQWhTKiXXkyxY+t9ZoKJv4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GptlwadZqxMY48TDvPt4xW5/MbLhpvcBHPw2KXmAfVDICpKlj7h2Mll1JoPBtcebD XizntGVvJ2FcI8pwdKL5gtnEaEYtLpQX14chlK6UdmdQOryMUqyZTWF0Yfqh6L0N7F eXzs9R3Ar2lom15gPUWua8p+dudzhNrcqtI3fFDtDQhEo+W7WaUl1Hk4sodEf/rUes m7YMrzj4j/lrWS6nBrT0PBPcjgTlbg/r111pYDFtMK0+0KxLvj/C9HGTrPgs97p+xw dVqkreHXUBO8ox6eGEWs8gQgFAjx9WMMdDzQLdg10I56X63F6teMJ9hK7ncFY5EyQt y1kPXUDXdHS/A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 11/14] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge Date: Tue, 12 Oct 2021 18:41:42 +0200 Message-Id: <20211012164145.14126-12-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár From very vague, ambiguous and incomplete information from Marvell we deduced that the 32-bit Aardvark register at address 0x4 (PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode in the Functional Specification (only for Endpoint mode), controls two 16-bit PCIe registers: Command Register and Status Registers of PCIe Root Port. This means that bit 2 controls bus mastering and forwarding of memory and I/O requests in the upstream direction. According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early setup of the Aardvark driver. Remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of Root PCIe Bridge via emulated PCI_COMMAND on emulated bridge. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org # b2a56469d550 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access") --- drivers/pci/controller/pci-aardvark.c | 54 +++++++++++++++++++-------- 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 337b61508799..289cd45ed1ec 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -31,9 +31,6 @@ /* PCIe core registers */ #define PCIE_CORE_DEV_ID_REG 0x0 #define PCIE_CORE_CMD_STATUS_REG 0x4 -#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) -#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) -#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 @@ -516,6 +513,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; advk_writel(pcie, reg, VENDOR_ID_REG); + /* Disable Root Bridge I/O space, memory space and bus mastering */ + reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | @@ -620,19 +622,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_pcie_disable_ob_win(pcie, i); advk_pcie_train_link(pcie); - - /* - * FIXME: The following register update is suspicious. This register is - * applicable only when the PCI controller is configured for Endpoint - * mode, not as a Root Complex. But apparently when this code is - * removed, some cards stop working. This should be investigated and - * a comment explaining this should be put here. - */ - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); - reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | - PCIE_CORE_CMD_IO_ACCESS_EN | - PCIE_CORE_CMD_MEM_IO_REQ_EN; - advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); } static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) @@ -761,6 +750,37 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie) return -ETIMEDOUT; } +static pci_bridge_emul_read_status_t +advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case PCI_COMMAND: + *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); + return PCI_BRIDGE_EMUL_HANDLED; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } +} + +static void +advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case PCI_COMMAND: + advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); + break; + + default: + break; + } +} static pci_bridge_emul_read_status_t advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, @@ -862,6 +882,8 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { + .read_base = advk_pci_bridge_emul_base_conf_read, + .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, .write_pcie = advk_pci_bridge_emul_pcie_conf_write, }; From patchwork Tue Oct 12 16:41:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553187 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4843FC433FE for ; Tue, 12 Oct 2021 16:42:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34AB160F21 for ; Tue, 12 Oct 2021 16:42:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231702AbhJLQoH (ORCPT ); Tue, 12 Oct 2021 12:44:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:37104 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231683AbhJLQoG (ORCPT ); Tue, 12 Oct 2021 12:44:06 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E08FD61076; Tue, 12 Oct 2021 16:42:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056924; bh=kY1dXfyNYpcpAYJ01xtEYI0Vj2+JUlx5S8nnxpkVqUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r4LmXMM5s1xbTmRtFJb2wrJdI3P5M5btI7ZQFbceJhnAFkPtqQcYx6fS1AXBiAJLz F1vap9iqspfKsL12zuepTsTq9yjilfRfGKHVagUGpvPXbNs4ojjHIrjbs9LIE5IZNR JWDCOqyaUFwxPn5LJtRfaUwGrvMe8KpCE4HB/KjOzo7rbEz6V2TTybYw2dKIuOizQI QpOPARDfqh7PDOVaSheEIkOeeAxbrw/IEtO3+R1M9nafUXqeqazK8+NcYMUvD1fbKA icmG8/VPYQ7/wrUevJ5j1LDDTYiX3qK0zA6NFJaKAYWttoRrwRcg05bvX3Uzid9gjm V8jTnp5UCaIPA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 12/14] PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge Date: Tue, 12 Oct 2021 18:41:43 +0200 Message-Id: <20211012164145.14126-13-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark controller has something like config space of a Root Port available at offset 0x0 of internal registers - these registers are used for implementation of the emulated bridge. The default value of Class Code of this bridge corresponds to a RAID Mass storage controller, though. (This is probably intended for when the controller is used as Endpoint.) Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 289cd45ed1ec..801657e7da93 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -513,6 +513,26 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; advk_writel(pcie, reg, VENDOR_ID_REG); + /* + * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), + * because the default value is Mass storage controller (0x010400). + * + * Note that this Aardvark PCI Bridge does not have compliant Type 1 + * Configuration Space and it even cannot be accessed via Aardvark's + * PCI config space access method. Something like config space is + * available in internal Aardvark registers starting at offset 0x0 + * and is reported as Type 0. In range 0x10 - 0x34 it has totally + * different registers. + * + * Therefore driver uses emulation of PCI Bridge which emulates + * access to configuration space via internal Aardvark registers or + * emulated configuration buffer. + */ + reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); + reg &= ~0xffffff00; + reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); + /* Disable Root Bridge I/O space, memory space and bus mastering */ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); From patchwork Tue Oct 12 16:41:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553189 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6D16C433EF for ; Tue, 12 Oct 2021 16:42:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BA1CD61074 for ; Tue, 12 Oct 2021 16:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231718AbhJLQoI (ORCPT ); Tue, 12 Oct 2021 12:44:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:37160 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231683AbhJLQoI (ORCPT ); Tue, 12 Oct 2021 12:44:08 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 49F1E608FE; Tue, 12 Oct 2021 16:42:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056926; bh=A7KXi+Zwk8hcitOOVk07yzSIAKQxKQCRJEkIfaWieyY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HqPskwu7dKEbG7fJVfH061wzQxt6p2PtQbU6aBxA+85BoUEOEpHjvbhNR8AdicUzY 4l4UDCixbAWj/HasQ2VbATktSqAEvdBC6em1uqHNgs/gce+rb17srlW7g81mjMktf0 TctDp/N1ksuxQqlC0n6lvPEaeUcxDSDovtMCmo4wuqs7cnM7Yu5j+WQT5z10D4Jmji OBNJ5uk/1idYpY0DP2/lNg8+V31NIM3Vg42D+uKFHRSisfCLrXp1vV5YV5PvolBc9M KeljPLKloNVL4mimDJm0/H7+iHQR5XsbTO04fQKkv+F6B6m+eZRd2Eq/1YF0cGW48e 9gXCZRfJPZ35A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 13/14] PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge Date: Tue, 12 Oct 2021 18:41:44 +0200 Message-Id: <20211012164145.14126-14-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this, the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Custom userspace script [1] which uses setpci can trigger PCIe Hot Reset and reset the card manually. [1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 801657e7da93..ad31a172c5c2 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -781,6 +781,22 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); return PCI_BRIDGE_EMUL_HANDLED; + case PCI_INTERRUPT_LINE: { + /* + * From the whole 32bit register we support reading from HW only + * one bit: PCI_BRIDGE_CTL_BUS_RESET. + * Other bits are retrieved only from emulated config buffer. + */ + __le32 *cfgspace = (__le32 *)&bridge->conf; + u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); + if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) + val |= PCI_BRIDGE_CTL_BUS_RESET << 16; + else + val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); + *value = val; + return PCI_BRIDGE_EMUL_HANDLED; + } + default: return PCI_BRIDGE_EMUL_NOT_HANDLED; } @@ -797,6 +813,17 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); break; + case PCI_INTERRUPT_LINE: + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) + val |= HOT_RESET_GEN; + else + val &= ~HOT_RESET_GEN; + advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); + } + break; + default: break; } From patchwork Tue Oct 12 16:41:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12553191 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EA2BC433F5 for ; Tue, 12 Oct 2021 16:42:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27ADD60273 for ; Tue, 12 Oct 2021 16:42:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231717AbhJLQoJ (ORCPT ); Tue, 12 Oct 2021 12:44:09 -0400 Received: from mail.kernel.org ([198.145.29.99]:37170 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231735AbhJLQoJ (ORCPT ); Tue, 12 Oct 2021 12:44:09 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A6E136023B; Tue, 12 Oct 2021 16:42:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634056927; bh=MO9ElK6qW8fA653llwfRpuTBUH9NFIEzPdb7Xa6FnF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eotAt3cd4WtqCvgfisLLFehOxknDvWeU1PQFOA9cIsOx/J5DhXv31wI86t3Mh0Lo3 hLbIKPO/4TlNtFa3zrl69BOowHUa7Q+G3EhFDeB6+RgO8Vt5mg/HlLWtDM7E2xnnqO 3s08CXmya4l9AiSp2mXAGsGB9J/OwPzYpzp90bT9rE7ErtL/kvAkYKyrKCKHZ5u0eC RflDM1alxgxofyteoh1lMQwS56si1Oi6ts8Zm2ptDeENFFRuqjhA7ReZPT6JfKEhxf E8sDBWhbOTtnEoolcrVfSMPVInDSwVC9i0JCBzJ9YKl64UkHUc8aWVNtDNFGWDb10o rwi3qnHjm7gVg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 14/14] PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge Date: Tue, 12 Oct 2021 18:41:45 +0200 Message-Id: <20211012164145.14126-15-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211012164145.14126-1-kabel@kernel.org> References: <20211012164145.14126-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár This register is exported at address offset 0x30. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ad31a172c5c2..5d944e57c1a6 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -32,6 +32,7 @@ #define PCIE_CORE_DEV_ID_REG 0x0 #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 +#define PCIE_CORE_EXP_ROM_BAR_REG 0x30 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) @@ -781,6 +782,10 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); return PCI_BRIDGE_EMUL_HANDLED; + case PCI_ROM_ADDRESS1: + *value = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); + return PCI_BRIDGE_EMUL_HANDLED; + case PCI_INTERRUPT_LINE: { /* * From the whole 32bit register we support reading from HW only @@ -813,6 +818,10 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); break; + case PCI_ROM_ADDRESS1: + advk_writel(pcie, new, PCIE_CORE_EXP_ROM_BAR_REG); + break; + case PCI_INTERRUPT_LINE: if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);