From patchwork Thu Oct 14 13:56:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12558581 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6241DC4332F for ; Thu, 14 Oct 2021 13:57:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 35BA660EBB for ; Thu, 14 Oct 2021 13:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbhJNN7Y (ORCPT ); Thu, 14 Oct 2021 09:59:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231452AbhJNN7X (ORCPT ); Thu, 14 Oct 2021 09:59:23 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAA70C061755 for ; Thu, 14 Oct 2021 06:57:13 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id r10so19704902wra.12 for ; Thu, 14 Oct 2021 06:57:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CJsCWcU0YdDyrwMeRQ7adfzbBn9rJ1IRoawBpqp6LUY=; b=nWdcXGVnk8Oz4L0y1/sfaNNPdvqBC8SWVQ5nnv5b8TQyWXphWKaoUoiCpwNZG8Kmg7 3dj3uagsMpT5Mkox9mRqXNBxgELAR6KQRJP9qR7cIbMpgcAwTrHHxyN3OM34CHGR60Kf uIoST2ZV+XIqKoziuz9ddYYjU2uuTxUp8n0OkD0kamILuU2BO4qcyQAoYlx5tI534hXJ 8wX7ijJxd8dBsX1S0k56zxW+ymjGBOBsd4ztmANLtNmhWda2bOwt25nOHi8W1weYloLU m4XidWIX7hPvKFUYi1gyqqnTuCRudf4eTSdoq2TPK4/ZCBoXD2FMfrqCXrtT1XLD+5mN fCfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CJsCWcU0YdDyrwMeRQ7adfzbBn9rJ1IRoawBpqp6LUY=; b=5BFzov0UA92HJs/jjYWkXPl3ZyPOJpWbv5HvmgoxNxeMRJyf/O1QMMdxN/XvUt2njy TV9+N4jAudncbrjf5lAiBLFJUYrNKECdqbM2pnV10g6EXkqPACUaze/LyEXbCpz3w4D7 bmTFKobOOymH0B/Q+gQ+wOQqOdnS7IfMQv4vr1Re/zyQrUBJDgtIpgTfUJbx/CgSj/1n jl9inMVo9Epiff6u5mVlJp9D0+dqv6A5KMOR19ewKGeALE+uMI8r8owqEQ/GGSbQkz5m qPY6/8v8GJhoWPb2aT4OKGeEIBrdb9mRInzH+72cVkMMO5qQDcql1wFm4AG/mraqSt8Y P41Q== X-Gm-Message-State: AOAM531OnvPUXpQrSV7ENUk2DTsAOBXpaTQHjGN0bu/9+pSfAG87TU4m 7EkM/+uFBb5JwJTNC9CJe/Z4rQ== X-Google-Smtp-Source: ABdhPJwQIpKFObMCc8ia1BlvyYCeOcB3+iofnWS2JorNe065Bk+P85rDl3QiHz/L0kIPBi56mMyzOw== X-Received: by 2002:a5d:45c9:: with SMTP id b9mr6722258wrs.365.1634219832217; Thu, 14 Oct 2021 06:57:12 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900::97e]) by smtp.gmail.com with ESMTPSA id d1sm2596480wrr.72.2021.10.14.06.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 06:57:11 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH 1/3] dt-bindings: thermal: mediatek: Add mt8365 Date: Thu, 14 Oct 2021 15:56:34 +0200 Message-Id: <20211014135636.3644166-2-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211014135636.3644166-1-msp@baylibre.com> References: <20211014135636.3644166-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This unit is present on the mt8365 SoC as well. But there is a difference in the usage of an apmixed register. This patch adds a distinct mt8365 to the list of compatibles. Signed-off-by: Markus Schneider-Pargmann --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 5c7e7bdd029a..ba4ebffeade4 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -14,6 +14,7 @@ Required properties: - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - "mediatek,mt7622-thermal" : For MT7622 SoC - "mediatek,mt8183-thermal" : For MT8183 family of SoCs + - "mediatek,mt8365-thermal" : For MT8365 family of SoCs - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller From patchwork Thu Oct 14 13:56:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12558583 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B87B8C43217 for ; Thu, 14 Oct 2021 13:57:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95E16610CC for ; Thu, 14 Oct 2021 13:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231452AbhJNN7Z (ORCPT ); Thu, 14 Oct 2021 09:59:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231559AbhJNN7Y (ORCPT ); Thu, 14 Oct 2021 09:59:24 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C748C061764 for ; Thu, 14 Oct 2021 06:57:14 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id y3so19905771wrl.1 for ; Thu, 14 Oct 2021 06:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=31i1xoK4zj6WYEXJeZOG+hCuryOlTysPNDj29OD14Qs=; b=AbHERgV7hhK7Q6TsIVXDya02ZczmFNkqDkzMRSz+b+mHRNIq6O6J/3YIaczr+Yo5w4 L9JZQ8vTipg5kViM+Gi+d62zIR9O0Nze896kdfMcAS5x2Z3MCeiUka1h8f8/EO4VfAoP Y1SIkDm6VKBF91hvtGbAzn7tK6qAo4btprN1Zf7wqxYeAv25KVG9GgCM9bH3QPOk6z84 dtoqxU3Kj+yA8e/bObrV3McYIyICqYUULyvr7+Y0N7uKnahrTECmyrXw+uwe/YpjNldC Ur/IA7QCkYjR/X8Ta/9ylJhKw02phSqKkPvmkg+24El7J8HWAHSoFMiUHcNlDV2ncKhd 2j3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=31i1xoK4zj6WYEXJeZOG+hCuryOlTysPNDj29OD14Qs=; b=noFN5JbLx5eXfmeHbbAB2FvEjL2Qq4K1YVhtaPn/03Ds7RVQS3FCHydgQZD2TMTp5o A0oFBO0sgsUtS/5j5Jkh/oKroYEhJMAnO+oP2/wMNsxPmAq3rQRi1oEiruIKAmsgfRzQ 9CAQ48b/5OLcodDfLuLHAJOBTbqZW79/ksigFfJi/RR6YZwyoYrVZSsLJRys6EsSvV+M OHfK2mhpklDfhkqApl8KIUmcqB9T2PEonAdRQQzGQE+mtFvTZQAbjhnhteSBB9sH3W39 oS0xmTPGq0YJJ/0WL5GyTgmjTdY945WGeMpOisGnIHOtz5B1NeQeJNI9yBIOMz7J+qw+ C57w== X-Gm-Message-State: AOAM530lvLuFYz5IWDt6yVctuLDQqMwiHSfPBPmSCofNM8E891EnCxBf 4DpWTF0jQz40YySqb69FdQZTbQ== X-Google-Smtp-Source: ABdhPJzovFHxnVhnPJn8Z93ko4jfsXuTJHegbHkAVGuJQykKzBnhuZgk+oxF6vDUOvuqwSsAAyi9Bw== X-Received: by 2002:a05:600c:21cc:: with SMTP id x12mr11267492wmj.8.1634219833159; Thu, 14 Oct 2021 06:57:13 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900::97e]) by smtp.gmail.com with ESMTPSA id d1sm2596480wrr.72.2021.10.14.06.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 06:57:12 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH 2/3] thermal: mediatek: Fix apmixed error message Date: Thu, 14 Oct 2021 15:56:35 +0200 Message-Id: <20211014135636.3644166-3-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211014135636.3644166-1-msp@baylibre.com> References: <20211014135636.3644166-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Seems to be a copy and paste mistake, this is the apmixed address, not auxadc. Signed-off-by: Markus Schneider-Pargmann Fixes: a92db1c8089e (thermal: Add Mediatek thermal controller support) --- drivers/thermal/mtk_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index ede94eadddda..93ee043d70da 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -1050,7 +1050,7 @@ static int mtk_thermal_probe(struct platform_device *pdev) of_node_put(apmixedsys); if (apmixed_phys_base == OF_BAD_ADDR) { - dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + dev_err(&pdev->dev, "Can't get apmixed phys address\n"); return -EINVAL; } From patchwork Thu Oct 14 13:56:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 12558585 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F381C4167B for ; Thu, 14 Oct 2021 13:57:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A8E061029 for ; Thu, 14 Oct 2021 13:57:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231596AbhJNN7Z (ORCPT ); Thu, 14 Oct 2021 09:59:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231639AbhJNN7Y (ORCPT ); Thu, 14 Oct 2021 09:59:24 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC07FC061766 for ; Thu, 14 Oct 2021 06:57:15 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id r7so19830772wrc.10 for ; Thu, 14 Oct 2021 06:57:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AD9oqEQRrt+K7PF8CXPWRak3iEsR+fAEIvT2MdmSXYg=; b=TfoGK/YO6N+ITiDgcTK73gZE3NycgEqVa42Qf+1UO19RkHZTAwACZo/Cmjcmyp6DC+ jjOEmmUrU6AS2a+z6PLo+veVAOpA8ug9q/KSPIy+V+It3Ql3VPEcN1CES0d1MSR/alzy zTRJ5zDFqAL+v0ysrZxWiCOo7ps5tOpGeX6sWN4lgwSaWd+hoPiVPer5X6BpT8sqS1Y9 WoZ1Rbs65CYx2T5s5OYWvBlIaVl0r9BIOV8NAdYIlRnCMxOUIbfskfDg4EXOwAYBvCa8 34G71isUqFGMmYn3xDD+2dw342v5dqFtt+bbhU2WP2g0HPZ8mA8iIqW8OUb3oiKKsiEG eLFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AD9oqEQRrt+K7PF8CXPWRak3iEsR+fAEIvT2MdmSXYg=; b=B/VHdgCEm4U+wQ92qkqZN2xiZAgX0fHkFk6zswnpXnQtQndSf384PbU75mt9WdRLpA IRpOUn+j7TYumDY9rCumzyID4ZG6yTVnL+SgrllZDN3wpFZKxgt94TmvpI2mBkn+YqVY uxiXq5R4ltaxV9NFwgGWBuNj+xWNdmYUSF6xFEtNOOzjDMSCKsH1JRJbePrqUttkpLB3 6MFKybQKvuSaQ4gzmeBfyARFMnRaJ211qiUdjqdB1kX5TMCtLwuGngFO+JFmfbQ/FHfE FaqRuNouzUXXBfpOzlcL7kyMEidbzCrzEXYKjK8Uu97vct4aGfkeQsjuU2qFK9Yjvh// UJiQ== X-Gm-Message-State: AOAM531JarVOFtxfT6DYYTa1t2H24LZFeiOVVEwUjdzJCh9h2TlNp/9n ZVH4kbzP3d/lYPXp5+FlBVljOw== X-Google-Smtp-Source: ABdhPJxf6LFxs3+QRVjtPhFm8mbj6cscqF3nefyMxTfWqwVufhx+YS+YovqZvQSFJ2KDY/Mwv1LV9g== X-Received: by 2002:a5d:4ac4:: with SMTP id y4mr6830961wrs.190.1634219834060; Thu, 14 Oct 2021 06:57:14 -0700 (PDT) Received: from blmsp.lan ([2a02:2454:3e6:c900::97e]) by smtp.gmail.com with ESMTPSA id d1sm2596480wrr.72.2021.10.14.06.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 06:57:13 -0700 (PDT) From: Markus Schneider-Pargmann To: Zhang Rui , Daniel Lezcano , Matthias Brugger , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, fparent@baylibre.com, khilman@baylibre.com, Markus Schneider-Pargmann Subject: [PATCH 3/3] thermal: mediatek: add MT8365 thermal driver support Date: Thu, 14 Oct 2021 15:56:36 +0200 Message-Id: <20211014135636.3644166-4-msp@baylibre.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211014135636.3644166-1-msp@baylibre.com> References: <20211014135636.3644166-1-msp@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Fabien Parent mt8365 is similar to the other SoCs supported by the driver. It has only one bank and 3 sensors that can be multiplexed. Additionally the buffer has to be enabled and connected to AUXADC similar to the V2 version but at a different register offset. That's why I added three new configuration values to define the register, mask and bits to be set to be able to use it for both V2 and mt8365. Signed-off-by: Fabien Parent [Added apmixed control register logic] Signed-off-by: Markus Schneider-Pargmann --- drivers/thermal/mtk_thermal.c | 91 ++++++++++++++++++++++++++++++++--- 1 file changed, 85 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 93ee043d70da..7a75ae8231f2 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -31,6 +31,7 @@ #define AUXADC_CON2_V 0x010 #define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define APMIXED_SYS_TS_CON0 0x600 #define APMIXED_SYS_TS_CON1 0x604 /* Thermal Controller Registers */ @@ -245,6 +246,17 @@ enum mtk_thermal_version { /* The calibration coefficient of sensor */ #define MT8183_CALIBRATION 153 +/* MT8365 */ +#define MT8365_TEMP_AUXADC_CHANNEL 11 +#define MT8365_CALIBRATION 164 +#define MT8365_NUM_CONTROLLER 1 +#define MT8365_NUM_BANKS 1 +#define MT8365_NUM_SENSORS 3 +#define MT8365_NUM_SENSORS_PER_ZONE 3 +#define MT8365_TS1 0 +#define MT8365_TS2 1 +#define MT8365_TS3 2 + struct mtk_thermal; struct thermal_bank_cfg { @@ -271,6 +283,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -386,6 +401,24 @@ static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; +/* MT8365 thermal sensor data */ +static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { + MT8365_TS1, MT8365_TS2, MT8365_TS3 +}; + +static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +}; + +static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +}; + +static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; +static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; + +static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -460,6 +493,40 @@ static const struct mtk_thermal_data mt2701_thermal_data = { .version = MTK_THERMAL_V1, }; +/* + * The MT8365 thermal controller has one bank, which can read up to + * four temperature sensors simultaneously. The MT8365 has a total of 3 + * temperature sensors. + * + * The thermal core only gets the maximum temperature of this one bank, + * so the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data. + */ +static const struct mtk_thermal_data mt8365_thermal_data = { + .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, + .num_banks = MT8365_NUM_BANKS, + .num_sensors = MT8365_NUM_SENSORS, + .vts_index = mt8365_vts_index, + .cali_val = MT8365_CALIBRATION, + .num_controller = MT8365_NUM_CONTROLLER, + .controller_offset = mt8365_tc_offset, + .need_switch_bank = false, + .bank_data = { + { + .num_sensors = MT8365_NUM_SENSORS, + .sensors = mt8365_bank_data + }, + }, + .msr = mt8365_msr, + .adcpnp = mt8365_adcpnp, + .sensor_mux_values = mt8365_mux_values, + .version = MTK_THERMAL_V1, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, + .apmixed_buffer_ctl_mask = ~(u32)GENMASK(29, 28), + .apmixed_buffer_ctl_set = 0, +}; + /* * The MT2712 thermal controller has one bank, which can read up to * four temperature sensors simultaneously. The MT2712 has a total of 4 @@ -514,6 +581,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = ~0x37, + .apmixed_buffer_ctl_set = 0x1, }; /* @@ -958,19 +1028,27 @@ static const struct of_device_id mtk_thermal_of_match[] = { { .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, + }, + { + .compatible = "mediatek,mt8365-thermal", + .data = (void *)&mt8365_thermal_data, }, { }, }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { int tmp; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + if (!mt->conf->apmixed_buffer_ctl_reg) + return; + + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1070,8 +1148,9 @@ static int mtk_thermal_probe(struct platform_device *pdev) goto err_disable_clk_auxadc; } + mtk_thermal_turn_on_buffer(mt, apmixed_base); + if (mt->conf->version == MTK_THERMAL_V2) { - mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); }