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[2a01:c22:7b82:9800:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id d8sm7415796wrv.80.2021.10.16.03.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Oct 2021 03:50:43 -0700 (PDT) From: Martin Blumenstingl To: linux-clk@vger.kernel.org, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, knaerzche@gmail.com, mturquette@baylibre.com, Martin Blumenstingl Subject: [PATCH clk-fixes v1 1/2] clk: composite: Also consider .determine_rate for rate + mux composites Date: Sat, 16 Oct 2021 12:50:21 +0200 Message-Id: <20211016105022.303413-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211016105022.303413-1-martin.blumenstingl@googlemail.com> References: <20211016105022.303413-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211016_035046_420453_85820742 X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") switches clk_divider_ops to implement .determine_rate by default. This breaks composite clocks with multiple parents because clk-composite.c does not use the special handling for mux + divider combinations anymore (that was restricted to rate clocks which only implement .round_rate, but not .determine_rate). Alex reports: This breaks lot of clocks for Rockchip which intensively uses composites, i.e. those clocks will always stay at the initial parent, which in some cases is the XTAL clock and I strongly guess it is the same for other platforms, which use composite clocks having more than one parent (e.g. mediatek, ti ...) Example (RK3399) clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot. It will always stay at this parent, even if the mmc driver sets a rate of 200 MHz (fails, as the nature of things), which should switch it to any of its possible parent PLLs defined in mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which never happens. Restore the original behavior by changing the priority of the conditions inside clk-composite.c. Now the special rate + mux case (with rate_ops having a .round_rate - which is still the case for the default clk_divider_ops) is preferred over rate_ops which have .determine_rate defined (and not further considering the mux). Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") Reported-by: Alex Bee Signed-off-by: Martin Blumenstingl --- drivers/clk/clk-composite.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index c7b97fb0051b..ba8d4d8cf8dd 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -58,11 +58,8 @@ static int clk_composite_determine_rate(struct clk_hw *hw, long rate; int i; - if (rate_hw && rate_ops && rate_ops->determine_rate) { - __clk_hw_set_clk(rate_hw, hw); - return rate_ops->determine_rate(rate_hw, req); - } else if (rate_hw && rate_ops && rate_ops->round_rate && - mux_hw && mux_ops && mux_ops->set_parent) { + if (rate_hw && rate_ops && rate_ops->round_rate && + mux_hw && mux_ops && mux_ops->set_parent) { req->best_parent_hw = NULL; if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { @@ -107,6 +104,9 @@ static int clk_composite_determine_rate(struct clk_hw *hw, req->rate = best_rate; return 0; + } else if (rate_hw && rate_ops && rate_ops->determine_rate) { + __clk_hw_set_clk(rate_hw, hw); + return rate_ops->determine_rate(rate_hw, req); } else if (mux_hw && mux_ops && mux_ops->determine_rate) { __clk_hw_set_clk(mux_hw, hw); return mux_ops->determine_rate(mux_hw, req); From patchwork Sat Oct 16 10:50:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12563581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94657C433F5 for ; Sat, 16 Oct 2021 10:52:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5424E6108E for ; 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[2a01:c22:7b82:9800:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id d8sm7415796wrv.80.2021.10.16.03.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Oct 2021 03:50:44 -0700 (PDT) From: Martin Blumenstingl To: linux-clk@vger.kernel.org, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, knaerzche@gmail.com, mturquette@baylibre.com, Martin Blumenstingl Subject: [PATCH clk-fixes v1 2/2] clk: composite: Use rate_ops.determine_rate when also a mux is available Date: Sat, 16 Oct 2021 12:50:22 +0200 Message-Id: <20211016105022.303413-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211016105022.303413-1-martin.blumenstingl@googlemail.com> References: <20211016105022.303413-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211016_035052_526849_4962226E X-CRM114-Status: GOOD ( 18.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update clk_composite_determine_rate() to use rate_ops.determine_rate when available in combination with a mux. So far clk_divider_ops provide both, .round_rate and .determine_rate. Removing the former would make clk-composite fail silently for example on Rockchip platforms (which heavily use composite clocks). Add support for using rate_ops.determine_rate when either rate_ops.round_rate is not available or both (.round_rate and .determine_rate) are provided. Suggested-by: Alex Bee Signed-off-by: Martin Blumenstingl --- drivers/clk/clk-composite.c | 68 ++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index ba8d4d8cf8dd..c04ae0e7e4b4 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -42,6 +42,29 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, return rate_ops->recalc_rate(rate_hw, parent_rate); } +static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw, + struct clk_rate_request *req, + struct clk_hw *parent_hw, + const struct clk_ops *rate_ops) +{ + long rate; + + req->best_parent_hw = parent_hw; + req->best_parent_rate = clk_hw_get_rate(parent_hw); + + if (rate_ops->determine_rate) + return rate_ops->determine_rate(rate_hw, req); + + rate = rate_ops->round_rate(rate_hw, req->rate, + &req->best_parent_rate); + if (rate < 0) + return rate; + + req->rate = rate; + + return 0; +} + static int clk_composite_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { @@ -51,51 +74,56 @@ static int clk_composite_determine_rate(struct clk_hw *hw, struct clk_hw *rate_hw = composite->rate_hw; struct clk_hw *mux_hw = composite->mux_hw; struct clk_hw *parent; - unsigned long parent_rate; - long tmp_rate, best_rate = 0; unsigned long rate_diff; unsigned long best_rate_diff = ULONG_MAX; - long rate; - int i; + unsigned long best_rate = 0; + int i, ret; - if (rate_hw && rate_ops && rate_ops->round_rate && + if (rate_hw && rate_ops && + (rate_ops->determine_rate || rate_ops->round_rate) && mux_hw && mux_ops && mux_ops->set_parent) { req->best_parent_hw = NULL; if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { + struct clk_rate_request tmp_req = *req; + parent = clk_hw_get_parent(mux_hw); - req->best_parent_hw = parent; - req->best_parent_rate = clk_hw_get_rate(parent); - rate = rate_ops->round_rate(rate_hw, req->rate, - &req->best_parent_rate); - if (rate < 0) - return rate; + ret = clk_composite_determine_rate_for_parent(rate_hw, + &tmp_req, + parent, + rate_ops); + if (ret) + return ret; + + req->rate = tmp_req.rate; + req->best_parent_rate = tmp_req.best_parent_rate; - req->rate = rate; return 0; } for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) { + struct clk_rate_request tmp_req = *req; + parent = clk_hw_get_parent_by_index(mux_hw, i); if (!parent) continue; - parent_rate = clk_hw_get_rate(parent); - - tmp_rate = rate_ops->round_rate(rate_hw, req->rate, - &parent_rate); - if (tmp_rate < 0) + ret = clk_composite_determine_rate_for_parent(rate_hw, + &tmp_req, + parent, + rate_ops); + if (ret) continue; - rate_diff = abs(req->rate - tmp_rate); + rate_diff = abs(req->rate - tmp_req.rate); if (!rate_diff || !req->best_parent_hw || best_rate_diff > rate_diff) { req->best_parent_hw = parent; - req->best_parent_rate = parent_rate; + req->best_parent_rate = tmp_req.best_parent_rate; best_rate_diff = rate_diff; - best_rate = tmp_rate; + best_rate = tmp_req.rate; } if (!rate_diff)