From patchwork Tue Oct 19 08:43:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30398C433FE for ; Tue, 19 Oct 2021 08:43:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D16460EB9 for ; Tue, 19 Oct 2021 08:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234755AbhJSIpu (ORCPT ); Tue, 19 Oct 2021 04:45:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234730AbhJSIpr (ORCPT ); Tue, 19 Oct 2021 04:45:47 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ACA9C061765; Tue, 19 Oct 2021 01:43:35 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id f5so18677615pgc.12; Tue, 19 Oct 2021 01:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h7PwAA40r7NAb/5FPeOofbMWfGdgtuL0HMPeau8hiKs=; b=f9BYB/zy0ezsm9GvxRsGFCm3tzHvyxphbpqvMbikWQZuxNqBYcAyHo1QbaFfgWXmoH Cpo6CxcVglX4DeZpRJGlniTbsu346xZVt+aI5GbxezOsBeuMLuvEyn1AJF8HgvI3REgc tmUVcHDWbD0rBV4cJN4s977jRVesLXrsbjNzTwW4qOIZUQLQmJenSOe/BgLk2Rc2maB8 4NP5LY/4C/24wm+zuevlf/VaI51oyF1WGM78ZVKr6Rgtj1swmW4WEMfYcLYkfxXRyO9H du5SUiPRseqhEdEbxEuX+PE3ZciqjELGWavs1PhIzF5QkXTXbGGJD8pMkkyzkN9icGhn WW2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h7PwAA40r7NAb/5FPeOofbMWfGdgtuL0HMPeau8hiKs=; b=KIUbZ+hkxNNsBtaWPLYCnAIZ500iRIc7+rN92l98msRBcWrZ4sPFvwNEt4wGWA5TN3 NwYsJI68hHI4Wc8Pj10ZqwGjA5telsAMalWSQ6kziLkPm4YZfqlzIsGSziaX6LkH3A9D Tv5b86eaYDK3V7+cGdZCbJ5dgwbveSUvRL7ToMcPO586qTQ4BltJ2PCwUnOxt6xxG4Hb yIeovmzam1MCOH+zyJXAmD8jKFbtMGv1Dk3M1p52utafdT/qKOFt4z/BDVeArIJiGYt0 4h4+EqKqGJhWyY0MPrAbeSSgPDrtvo1BtMfVvg+9l66HMJpGXTT3n0g8y80Mm4RUCB6w Pe9Q== X-Gm-Message-State: AOAM533jIIuV31RH0pGLWCuTLyl61MF6RZ2zG11a/ZSFPNUEOXQ4Qa7r TV7vzRrOb2W/3MIsQceiDMc= X-Google-Smtp-Source: ABdhPJzKB3aEIRNO6YSO8LmXbk5VwNRtkkuZG53AggCZmIQ0r3UksdSPW1ndqT3alCgCZkgJ5PADMQ== X-Received: by 2002:a05:6a00:1309:b0:44d:4d1e:c930 with SMTP id j9-20020a056a00130900b0044d4d1ec930mr34064397pfu.65.1634633014561; Tue, 19 Oct 2021 01:43:34 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:34 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 01/10] media: admin-guide: add stm32-dma2d description Date: Tue, 19 Oct 2021 16:43:14 +0800 Message-Id: <1634633003-18132-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org add stm32-dma2d description for dma2d driver Signed-off-by: Dillon Min --- v6: no change. Documentation/admin-guide/media/platform-cardlist.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/admin-guide/media/platform-cardlist.rst b/Documentation/admin-guide/media/platform-cardlist.rst index 261e7772eb3e..ac73c4166d1e 100644 --- a/Documentation/admin-guide/media/platform-cardlist.rst +++ b/Documentation/admin-guide/media/platform-cardlist.rst @@ -60,6 +60,7 @@ s5p-mfc Samsung S5P MFC Video Codec sh_veu SuperH VEU mem2mem video processing sh_vou SuperH VOU video output stm32-dcmi STM32 Digital Camera Memory Interface (DCMI) +stm32-dma2d STM32 Chrom-Art Accelerator Unit sun4i-csi Allwinner A10 CMOS Sensor Interface Support sun6i-csi Allwinner V3s Camera Sensor Interface sun8i-di Allwinner Deinterlace From patchwork Tue Oct 19 08:43:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40F0BC433FE for ; Tue, 19 Oct 2021 08:43:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B9516134F for ; Tue, 19 Oct 2021 08:43:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234793AbhJSIpy (ORCPT ); Tue, 19 Oct 2021 04:45:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234784AbhJSIpw (ORCPT ); Tue, 19 Oct 2021 04:45:52 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4858C06161C; Tue, 19 Oct 2021 01:43:39 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id e7so18732153pgk.2; Tue, 19 Oct 2021 01:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XLCQB8Q/RXke9TU/xtNqqD1JtcGEgdBRulA1SQmD/6I=; b=DRSVF51W1Tri9tnncgCzpa+Z49xwTTfZLnhUOIj+bacnVoE7kW1MMmaCcqpJCBSraQ Y2pSDvmg1jq1/WSJ6KnaXnZmBw0O2+WPozZbIpFK4bH35guQjlZkBIsijMWexemR/yZy +U7b0nponUuuCqV8+G3uu2C+6gBw672j0ggUzCvR879aTFby82dmNNiXSvjmeCXga4AH Ht3rA5RbyTPmwMt21ggMVeCmfr2/0rzsdXL51TqElp8+Gl4oliDCijymVEV/5UFtzIwV eR1O4gEG7ovAZeDJmXZGZ5HPIq92MGo27wkbLOUW39hkpYwVLccUi6PwMvTj1V7xm5ag /5AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XLCQB8Q/RXke9TU/xtNqqD1JtcGEgdBRulA1SQmD/6I=; b=w7p3Whiq1/qSea6XfXL35McRhqcyBGp1GMc4xkgbOJKwS3GoDTfv/zV6xpkmmBqrw3 IIoON2K8mZ6MbNKQ5VdVVcEvueoQ+mEVHiLKUknZ1p2Guu7HrkmbOcuMRuXM/i1IVqmC NwifhWz7eyHOT0NzRw3fVQdGYF/qciZ89Y7XDo+fbxlxTqLL6jP7mGtmVpx/6MaYuPbM gOq/KgRxnW5gKkIutwk/Bw8UtuIDmubtiisUWLNhY+lMbNOxT6GfMkGeCiD1WVSPfpY5 0rMv7s4Jec4s9QqpLsICEZ80d79aAxIes9e0Pj7hxMF/BWrJNab2mcEDmo8SLeaG3IJo Te2w== X-Gm-Message-State: AOAM530mmH2IcG7ir2jf0P1IuKhUM+Y4/5HpyBqH6jevWB6Z8506STO6 nGUR+4y+AKR9zftLYy1KfJM= X-Google-Smtp-Source: ABdhPJyFWNuUVNFhzSwrdqQ9+DTsjZ/k8QBQ0HEWx0eWfAAqUJI4yEO8p9SsGhCuvM/3QBeQ6N+Twg== X-Received: by 2002:a63:340c:: with SMTP id b12mr27876611pga.241.1634633019488; Tue, 19 Oct 2021 01:43:39 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:39 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 02/10] media: dt-bindings: media: add document for STM32 DMA2d bindings Date: Tue, 19 Oct 2021 16:43:15 +0800 Message-Id: <1634633003-18132-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This adds documentation of device tree bindings for the STM32 DMA2D Signed-off-by: Dillon Min Reviewed-by: Rob Herring --- v6: no change. .../devicetree/bindings/media/st,stm32-dma2d.yaml | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml new file mode 100644 index 000000000000..f97b4a246605 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32-dma2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D binding + +description: + Chrom-ART Accelerator(DMA2D), graphical hardware accelerator + enabling enhanced graphical user interface with minimum CPU load + + It can perform the following operations. + + - Filling a part or the whole of a destination image with a specific color. + - Copying a part or the whole of a source image into a part or the whole of + a destination image. + - Copying a part or the whole of a source image into a part or the whole of + a destination image with a pixel format conversion. + - Blending a part and/or two complete source images with different pixel + format and copy the result into a part or the whole of a destination image + with a different color format. (TODO) + + +maintainers: + - Dillon Min + +properties: + compatible: + const: st,stm32-dma2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dma2d + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + }; + +... From patchwork Tue Oct 19 08:43:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5585C433EF for ; Tue, 19 Oct 2021 08:43:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC3236115A for ; Tue, 19 Oct 2021 08:43:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234788AbhJSIp6 (ORCPT ); Tue, 19 Oct 2021 04:45:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234797AbhJSIp5 (ORCPT ); Tue, 19 Oct 2021 04:45:57 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13BAC06161C; Tue, 19 Oct 2021 01:43:44 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id m26so17027512pff.3; Tue, 19 Oct 2021 01:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8KHGup7Rpu6QrYrymBE1Zjq70+Yty5ooxNn1hTc6qIk=; b=fYShuE0Y8HhsmW0xrkpC4XrkGoUBnf+34kxtCIAra4E+VKNJ8AgNyj3E/u3ObIkES+ GvG7fowi7pUvv6XeRsZ1BVWgJH1e+YbCVwq1VxIzvduTt22WGlUxBIHTK4ddPaOBalJl 63jZPxXVb0kcoqSJ5SAdI7eMFeJvC91GDrI46opjQx9FzyumOBevM3mn8eNOn8vcCzlL nGttdz9HrGluNqJepukh2PIlkUYMZiSfBFA1YWYSkImovV6byim/AQ7O3sdb+1fhCp/V bJzAeLVi7jP6QL8OfydnG7fBpF4+OPuELCKmgelG8XaUUJOM7fMXr9OVCph9Gh0/FGQf fApA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8KHGup7Rpu6QrYrymBE1Zjq70+Yty5ooxNn1hTc6qIk=; b=pdKCtH+22Vyi1cwiidCDytwPrkXcagzfv8BJ+WlavboX16W5zTPuqTfCzivta6T3YP HpFgMdD0BcGhyrCfx4AaDNkyM9B23vGpxMwFjPosjKkpscrDJDWM5FFrw80rd/y13BU7 nWrL58Ggs2JglZw9anDK4wMHqVBJaFGJbE7m3Ma8A5HmtcwgPGEh/9PLRn3lSl+vLpAv ro6597Ar+H9G31OwpfqnOEMF0qCm0XVKU9fRHFdkgvtsqi4bWOyNJtXUKgLBiUbF2B1f brS+AC8XYMdd7CPmtFWMhliu6dGkFyu+DN0Dvbwer7tseGgKhb9vHCjwFBTPMJoiSIoB YmGA== X-Gm-Message-State: AOAM532S9X7fJQKtFY+021f1YV1PWoDpgty4AyZOuXhgzjB5dGwsYh6Z NSvquhNHDXqtJpO1H3U+KN+dvXq5yBno2i0I X-Google-Smtp-Source: ABdhPJy7/unRPgOuTDXgHc4DcSGF2Mul2NmVpFRCzLO1l8unixtr5OXI8I2y8rZALj+g6tMSZ6d3Xw== X-Received: by 2002:a63:d2:: with SMTP id 201mr27681869pga.400.1634633024391; Tue, 19 Oct 2021 01:43:44 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:44 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 03/10] ARM: dts: stm32: Add DMA2D support for STM32F429 series soc Date: Tue, 19 Oct 2021 16:43:16 +0800 Message-Id: <1634633003-18132-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add DMA2D for STM32F429 series soc. Signed-off-by: Dillon Min --- v6: no change. arch/arm/boot/dts/stm32f429.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8748d5850298..1d8be5e7c8b8 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -743,6 +743,16 @@ st,mem2mem; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + mac: ethernet@40028000 { compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; reg = <0x40028000 0x8000>; From patchwork Tue Oct 19 08:43:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 864B9C433FE for ; Tue, 19 Oct 2021 08:43:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70D5460EB9 for ; Tue, 19 Oct 2021 08:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234791AbhJSIqF (ORCPT ); Tue, 19 Oct 2021 04:46:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234829AbhJSIqC (ORCPT ); Tue, 19 Oct 2021 04:46:02 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE5F6C061745; Tue, 19 Oct 2021 01:43:49 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id g5so13207378plg.1; Tue, 19 Oct 2021 01:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=11a8WRrodjbs6jBFryNK3TjxLIaCNHB0kvSxxWVC7xU=; b=pkLBJsi1UWn3VAvo3wtiy8xCGLHvs5IramWPxjf9aNuWZr/PZN0ZBeAAzxfafQYKIB 65/S1/pSkht3Qk6fsATWUUj9551mL+6Pi6bp48AAGvVu0Kp05weiKfkC1kCtp8QmDqhM S+WvBLlcEblTx8KTomo/BN98wGgOBvaq7tx7idEU/DZtDPhDoDPw8BK5iQgLx8Q9fGu6 cAdpQi+souzjcE99QcLB1oXpbWBztRxNzgUK4iMvzfbIylgMmfQyFCbwB4GSoctTXsbj KlX6AQ12jQBM/jYSnV7b02YB6yoipyG/BlnjHRdCOVm5rLP8GP2XyPqL+MKQBvDfbLpf GqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=11a8WRrodjbs6jBFryNK3TjxLIaCNHB0kvSxxWVC7xU=; b=pUy7/WEBAZS/idAgIjAHyfs+UIF876uogokem7y/7pAbzypobySLdYvjRADSg9rdL3 SfLSxk0XdnSQBMWvAppmoZ3Eh8aOQ8vDkF9hwwW1epO9W5U2t1qpuyM0A0bypc5bzbMu 5xjl/C238AvnE47+YL09qMtUqLa05mHsoIgqxFJsB/leS7Rx+CFI0i+VgDIZ3gy91pDF q0HdFuevT3+L8xAlwgCVghcfRt2TF9xkEMPwVuVg2+ZKL/uKgghBChm0oWhPI0q913H0 enxYGaGauIFoED26xSQZdEw6h2uudthyzXwpaIHoQpRXOVMWYEAqdzwPHXtPn5JuM4BS EVpA== X-Gm-Message-State: AOAM530VLHmM4QqxkBlY031u1nv4KMmJr3et8TbYtA8npJGNPZkaV0l9 MXGTDdEX8DgycZRAwEy2BIo= X-Google-Smtp-Source: ABdhPJwHL5p1H61EJ3d4KyVTH03HqMFuRWtSVTUkocgmfhLnXv0zCMAf7KKIuxNyWJClLmmjT/43Ow== X-Received: by 2002:a17:90b:4a88:: with SMTP id lp8mr5020595pjb.226.1634633029293; Tue, 19 Oct 2021 01:43:49 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:49 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 04/10] ARM: dts: stm32: Enable DMA2D on STM32F469-DISCO board Date: Tue, 19 Oct 2021 16:43:17 +0800 Message-Id: <1634633003-18132-5-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Enable DMA2D on STM32F469-DISCO board. Signed-off-by: Dillon Min --- v6: no change. arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 30905ce672a0..ba26a3375b0d 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -132,6 +132,10 @@ clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; From patchwork Tue Oct 19 08:43:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 882B7C4332F for ; Tue, 19 Oct 2021 08:44:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 674476139D for ; Tue, 19 Oct 2021 08:44:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234849AbhJSIqL (ORCPT ); Tue, 19 Oct 2021 04:46:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234809AbhJSIqI (ORCPT ); Tue, 19 Oct 2021 04:46:08 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81AC5C06161C; Tue, 19 Oct 2021 01:43:54 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id h193so3307008pgc.1; Tue, 19 Oct 2021 01:43:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9YChj8J53dFLEqWV9ieYXRrVD4Lc/MeGw3UeZhjNZXM=; b=g4s5EQwnsEOIrfK9LTCG1Do9I4ns5QjjtnT8BbyphPBkZR5PfD0DsPkxWAkhVBfgGc dBeVvyoohTzJGLio0rN6jzHwH54mE7T4q7hvRNaSigeQnMf/MGYFAekgRoV817VIsM4z cFPGaKT9PcXdahMs4b76gRbvaTsL94e+HIPPdlAhNUUmFByoqkwLiplqbQ86y9wAD8BV HWifptFCBJe9AehPjUd1zndYb2N3hrxb1joaoX6ggh2lrq0XU+83MjYjn1flyoIFOopZ dxf/lRerarzVkZPUCzwVkDcZEaclMHG/wlUkp7Mdsj1DMQqz0bF9NgM8NxOppeIn6txp PBeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9YChj8J53dFLEqWV9ieYXRrVD4Lc/MeGw3UeZhjNZXM=; b=5LMRmeQBhHSwu/O8MYqmJh9/4vQhY3byyp3BsdOhdvCSm5AsdDq2AQcA42IfysWa/C DvnITDSGG7FcGxu3MVtyKI0SSK9chkKNIoq4PSJqRIeRGN9UIJtgpAWLHHTwsziVZNiy eQ+j1myFAq87jfjFms05A9F4ZvBb0Own0HENMjYrpzU3oJ5dWshzMhdzzyuOzHqArnNq l/mj4tk0DwQctGfiCk5RWmagqXUgfvB2j8Cr07aVzb1R4hCKBu4zYZtqZ+YGo+OCMw5n Fo1XiFjVigKaqAUGi5cOFbciciy73nCZf0uCFqs9dnB3qHjD2aWobyfx6iQKcKTMZyxW RxRw== X-Gm-Message-State: AOAM530oA4nTlOhhlr0qlqFHA3uCO1VBvI4MxbXSXfnEHKUJ98l229je x3LinJ7b4xS3ovqyBw19mxM= X-Google-Smtp-Source: ABdhPJwwWc57B7dBY3YvhwQ4eK4FwfG9BLFjg0qB4PwIkbSpAd0uRo0YikHIm4xnTbA/VGX8r6Ciew== X-Received: by 2002:a62:5304:0:b0:44c:719c:a2c with SMTP id h4-20020a625304000000b0044c719c0a2cmr33506905pfb.13.1634633034123; Tue, 19 Oct 2021 01:43:54 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:53 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 05/10] media: v4l2-mem2mem: add v4l2_m2m_get_unmapped_area for no-mmu platform Date: Tue, 19 Oct 2021 16:43:18 +0800 Message-Id: <1634633003-18132-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For platforms without MMU the m2m provides a helper method v4l2_m2m_get_unmapped_area(), The mmap() routines will call this to get a proposed address for the mapping. More detailed information about get_unmapped_area can be found in Documentation/nommu-mmap.txt Signed-off-by: Dillon Min --- v6: no change. drivers/media/v4l2-core/v4l2-mem2mem.c | 21 +++++++++++++++++++++ include/media/v4l2-mem2mem.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c index e7f4bf5bc8dd..e2654b422334 100644 --- a/drivers/media/v4l2-core/v4l2-mem2mem.c +++ b/drivers/media/v4l2-core/v4l2-mem2mem.c @@ -966,6 +966,27 @@ int v4l2_m2m_mmap(struct file *file, struct v4l2_m2m_ctx *m2m_ctx, } EXPORT_SYMBOL(v4l2_m2m_mmap); +#ifndef CONFIG_MMU +unsigned long v4l2_m2m_get_unmapped_area(struct file *file, unsigned long addr, + unsigned long len, unsigned long pgoff, + unsigned long flags) +{ + struct v4l2_fh *fh = file->private_data; + unsigned long offset = pgoff << PAGE_SHIFT; + struct vb2_queue *vq; + + if (offset < DST_QUEUE_OFF_BASE) { + vq = v4l2_m2m_get_src_vq(fh->m2m_ctx); + } else { + vq = v4l2_m2m_get_dst_vq(fh->m2m_ctx); + pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); + } + + return vb2_get_unmapped_area(vq, addr, len, pgoff, flags); +} +EXPORT_SYMBOL_GPL(v4l2_m2m_get_unmapped_area); +#endif + #if defined(CONFIG_MEDIA_CONTROLLER) void v4l2_m2m_unregister_media_controller(struct v4l2_m2m_dev *m2m_dev) { diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h index 5a91b548ecc0..fdbd5257e020 100644 --- a/include/media/v4l2-mem2mem.h +++ b/include/media/v4l2-mem2mem.h @@ -495,6 +495,11 @@ __poll_t v4l2_m2m_poll(struct file *file, struct v4l2_m2m_ctx *m2m_ctx, int v4l2_m2m_mmap(struct file *file, struct v4l2_m2m_ctx *m2m_ctx, struct vm_area_struct *vma); +#ifndef CONFIG_MMU +unsigned long v4l2_m2m_get_unmapped_area(struct file *file, unsigned long addr, + unsigned long len, unsigned long pgoff, + unsigned long flags); +#endif /** * v4l2_m2m_init() - initialize per-driver m2m data * From patchwork Tue Oct 19 08:43:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90339C4332F for ; Tue, 19 Oct 2021 08:44:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 789116134F for ; Tue, 19 Oct 2021 08:44:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234132AbhJSIqO (ORCPT ); Tue, 19 Oct 2021 04:46:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234853AbhJSIqL (ORCPT ); Tue, 19 Oct 2021 04:46:11 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FC99C061769; Tue, 19 Oct 2021 01:43:59 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id c4so11653134pgv.11; Tue, 19 Oct 2021 01:43:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bzatNTKpIv4BlIffEmGaVOIbeC0H54OClaqsGTk2+Zw=; b=qk7Y6aaMUw7p1AOJxfTf2XvqG/q3sA/j53YkVdm8QLrdckbgaUezhy/mMlukXg90zo MZV5oN4Aaxku9fKZllIPnAuQ6NNK405v/+g/WgeZxy+chQlTrKLjwhulejmmdmRlIR7K 2hJEF85Zno0QNPzYP8m02Q1tuQlVtxAtw4hH/t9FE2/TbPftRREs41NVFkfbEE9CxSGf dEHCi8BNUNF1ahlouuwBqL6YnmYOEPuZCBvB7HI9U/ZiRMUWdaLw5Eu2Go9GUrnSzIvR fiJn1CwBWTsflWGR95/gRCKBHKYkQ2c6UOUUg89AlKQR/1tWPlmc2nhxxzsUgjtY3kB8 nQ4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bzatNTKpIv4BlIffEmGaVOIbeC0H54OClaqsGTk2+Zw=; b=pthIo55+KZBa9qmC3iabEwfu/xx6AWvEX9ICQ8Y4J5q2XnWXLRLD7ZYz/iSl8k962i g5aO61w8OOIozSip4bbCnBtUODPHKv8kXoNIFH8X7OCYDJ7MH96gCiVZjDklUk3/l9o7 d3UkWyj1kJLzXxOSQdQ0r9CSeqUjZQ49Nd2STLo3HerjV2ACcZnts+6WIpZx7QdcHmmy nBbwiddSkOTSnueK7O7RsLp2AZczjKZBpoJDa1V3/+ED7oG8a2bodybUjsM38hs/ZuSd voQEp3lfRFMVEFSxNwx61Ub5RiXgMUTKAYyCufFinWHC9/EWebrFROo8qUs6ah/kuOzY 4qHQ== X-Gm-Message-State: AOAM533mdkfvdiZLQS2X5g0wWFzYQjZ05rpIotEcWLJk3wO97qo2+DYI 0KJdjLEJOt8nf/76j9PiSC0= X-Google-Smtp-Source: ABdhPJz+zYTYXbwfcmo91WNsXUpc7Oih0DAr+aAgVCIyj8vNlImqLPgcmEXprlJD34M6ApWH0IUUCA== X-Received: by 2002:a63:5b09:: with SMTP id p9mr27544244pgb.321.1634633038976; Tue, 19 Oct 2021 01:43:58 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.54 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:43:58 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 06/10] media: videobuf2: Fix the size printk format Date: Tue, 19 Oct 2021 16:43:19 +0800 Message-Id: <1634633003-18132-7-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Since the type of parameter size is unsigned long, it should printk by %lu, instead of %ld, fix it. Fixes: 7952be9b6ece ("media: drivers/media/common/videobuf2: rename from videobuf") Signed-off-by: Dillon Min --- v6: no change. drivers/media/common/videobuf2/videobuf2-dma-contig.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c index b052a4e36961..7cd6648ccd26 100644 --- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c +++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c @@ -257,7 +257,7 @@ static void *vb2_dc_alloc(struct vb2_buffer *vb, ret = vb2_dc_alloc_coherent(buf); if (ret) { - dev_err(dev, "dma alloc of size %ld failed\n", size); + dev_err(dev, "dma alloc of size %lu failed\n", size); kfree(buf); return ERR_PTR(-ENOMEM); } @@ -298,9 +298,9 @@ static int vb2_dc_mmap(void *buf_priv, struct vm_area_struct *vma) vma->vm_ops->open(vma); - pr_debug("%s: mapped dma addr 0x%08lx at 0x%08lx, size %ld\n", - __func__, (unsigned long)buf->dma_addr, vma->vm_start, - buf->size); + pr_debug("%s: mapped dma addr 0x%08lx at 0x%08lx, size %lu\n", + __func__, (unsigned long)buf->dma_addr, vma->vm_start, + buf->size); return 0; } From patchwork Tue Oct 19 08:43:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEDD4C433EF for ; Tue, 19 Oct 2021 08:44:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA00161374 for ; Tue, 19 Oct 2021 08:44:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234866AbhJSIq0 (ORCPT ); Tue, 19 Oct 2021 04:46:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234867AbhJSIqS (ORCPT ); Tue, 19 Oct 2021 04:46:18 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D4D4C061768; Tue, 19 Oct 2021 01:44:04 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id lk8-20020a17090b33c800b001a0a284fcc2so1462729pjb.2; Tue, 19 Oct 2021 01:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fpv8AcIulys1PXAdWath/FGKH2Raxc3fRVYv8xcpy/Y=; b=ZQyuDd1JPbt6Yem87TsLy2jaYyQcfhxQLoLZ3GRcSyAAfjuRfnE1vU4p0fNuBbhZr5 KTuGHA3zN0B/zG798Fx3Sn5X2LvRBwBVWPTFXJdqIG5AVhT10CU0d0E1t9XflnPnmbk7 dFK4owQ0ubhSm3fREJfMfW2TgFWKcm4E5oRsXFrYPKY0AwoqWOgnAusosp0wt+mR5Sb1 AXTF55TiXmfVzuPxPLXcq9pAPUBFotptpcvKu9jX9KFPMuPHyL2ahguULvjEENZpqkSx bcey0AUXhU1bhwrU9tUOJ0fzrGyZAjvKoSQBAZZ9QrzRHWc4G9f+EDReyzsAdcUUt9qy GM0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fpv8AcIulys1PXAdWath/FGKH2Raxc3fRVYv8xcpy/Y=; b=mQhPwguFUY/yd6WFl2Dn5sK/3fkyscsmwu9Dy7HVcYLStfmI3X7oCmDcEVp3Vdyd/L tJl3TjhbNAQfZRCs9e5V7Z8o953SL7/cTOBYai7iy1YC5cnmtEDIdqOkjEFCciaz9BY9 YlnWJdZl65EdR7cYARXa0MkS2J/Hn+2ebuQL4cngGhuOboCE12I+wA6Wzi8Gd9CTrDax t/53QQcwvelHccGwz/BQW5fFrXvrbpfGRknbSBBVQV/nn6ubbkyXktGrFEcDpL96ertf LSa2CHJnMwPejNLMe3g1mtvqiCHCaGaRmZf/WVCDem99lPEEsQPThKKy+N4hbxmcw2xe D9RQ== X-Gm-Message-State: AOAM531lk5GyHegLee2O3LgFFkm9eyOa7OEjT8cG91KpiIr0koYCrX3E u6Z3tRU1gC+snEowDBqSz7Q= X-Google-Smtp-Source: ABdhPJwjGCds8GUyFgYQKvpUI+Vs44NhfMvVq6jqaLXrSPXVrqRx350tjn7R7itLUjK2s5ZQ+KtYvQ== X-Received: by 2002:a17:90a:7d0f:: with SMTP id g15mr4938039pjl.227.1634633043820; Tue, 19 Oct 2021 01:44:03 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.43.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:44:03 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 07/10] media: v4l2-ctrls: Add V4L2_CID_COLORFX_CBCR max setting Date: Tue, 19 Oct 2021 16:43:20 +0800 Message-Id: <1634633003-18132-8-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The max of V4L2_CID_COLORFX_CBCR is 0xffff, so add it to v4l2_ctrl_fill() to sure not beyond that. Signed-off-by: Dillon Min --- v6: no change. drivers/media/v4l2-core/v4l2-ctrls-defs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c index ebe82b6ba6e6..0cb6c0f18b39 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c +++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c @@ -1400,6 +1400,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, /* Max is calculated as RGB888 that is 2^24 */ *max = 0xFFFFFF; break; + case V4L2_CID_COLORFX_CBCR: + *type = V4L2_CTRL_TYPE_INTEGER; + *step = 1; + *min = 0; + *max = 0xffff; + break; case V4L2_CID_FLASH_FAULT: case V4L2_CID_JPEG_ACTIVE_MARKER: case V4L2_CID_3A_LOCK: From patchwork Tue Oct 19 08:43:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81071C433FE for ; Tue, 19 Oct 2021 08:44:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69F566115A for ; Tue, 19 Oct 2021 08:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234864AbhJSIqd (ORCPT ); Tue, 19 Oct 2021 04:46:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234857AbhJSIqZ (ORCPT ); Tue, 19 Oct 2021 04:46:25 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AB5EC06176F; Tue, 19 Oct 2021 01:44:09 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id t21so5148357plr.6; Tue, 19 Oct 2021 01:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1VqU4XTjCpirHS39n6Ik6WoFuzFscoD7Gz6T1rIL72A=; b=fPX8rWmpzjzpH/OQxS77IoGJc3xbaB8bKw+m7+Tm3IR/qeFSLZ+qfSlnSTIlLhNPUO PCOBf0TTrgZhPw7lrwp6QT6rIqSJcO7C5zaP9UftBVgxmevAzxSdqGtdmsfQgqc5SRb3 iiZf163blJRtfXNSk1bHC4H/GNa3tiFLtQUiLpLMe75nAkWPNrm/LaNuUFyccDavlJKB g8tYXh8hH80mZiNF9gkb65qVfIJPIkd8vMpeDyAmKPT8Xv6BXSFOLBrVJbv7SbZ9kIT0 jHe32FPmK19AWygbE4lmFEmUSWGQpMpZhfuT1XmgaT5L8uBDQWMW/yPHDMru+EmAubFg X/Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1VqU4XTjCpirHS39n6Ik6WoFuzFscoD7Gz6T1rIL72A=; b=QooJ/sdjZymE+KqG0YIPiTDBeatP/I5QnoEj1QSAj2IUq0uUxJrJc6lCscUuI1Q6a0 UDzG5qPOMkj1tp7nYZGtn6ZSS6unAN+bbDdBHv8eUqU9XWTcH3WNUGR/hiqntTi4fhVJ F/Nb30oBhfK2flmbkSc49+DwxrS7Bm50G4FniSFAB2HDcCeRmLCMnOTF5jGCZAyMt/ds nYeirX0oE5i9ZnuAxu8zB3D2X1ObTeLg1KNFlQAzMBw2oi3YxEkw5et2wfuDhZfQXQAR EfVV6j2cUZxKkL9wLUB/kSl5YLnWBbyFnFPnVUiG4uqppl+w59KuaYTxUre6pwr/IBk5 TOaQ== X-Gm-Message-State: AOAM530/Y+FR4gCM9VsZ/6047dN6EKddUX2E4LoGmqp++Aj+k/eF2lhW qCk5M8K1Bxq79zjQUCSQoCI= X-Google-Smtp-Source: ABdhPJyfW1mP1njhIKYVaL1M/HtxJBdQwz1eAcuC+TRtsUJLSXNJ8Z/JXZVOFK3MR3N6IyLcR1HsSA== X-Received: by 2002:a17:902:e746:b0:13f:398e:a0e2 with SMTP id p6-20020a170902e74600b0013f398ea0e2mr31807286plf.48.1634633049003; Tue, 19 Oct 2021 01:44:09 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.44.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:44:08 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 08/10] media: v4l2-ctrls: Add RGB color effects control Date: Tue, 19 Oct 2021 16:43:21 +0800 Message-Id: <1634633003-18132-9-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add V4L2_COLORFX_SET_RGB color effects control, V4L2_CID_COLORFX_RGB for RGB color setting. with two mirror changes: - change 0xFFFFFF to 0xffffff - fix comments 2^24 to 2^24 - 1 Signed-off-by: Dillon Min --- v6: add space in '(V4L2_CID_BASE+43)' to avoid checkpatch warrnings. Documentation/userspace-api/media/v4l/control.rst | 9 +++++++++ drivers/media/v4l2-core/v4l2-ctrls-defs.c | 6 ++++-- include/uapi/linux/v4l2-controls.h | 4 +++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/Documentation/userspace-api/media/v4l/control.rst b/Documentation/userspace-api/media/v4l/control.rst index f8d0b923da20..3eec65174260 100644 --- a/Documentation/userspace-api/media/v4l/control.rst +++ b/Documentation/userspace-api/media/v4l/control.rst @@ -242,8 +242,17 @@ Control IDs * - ``V4L2_COLORFX_SET_CBCR`` - The Cb and Cr chroma components are replaced by fixed coefficients determined by ``V4L2_CID_COLORFX_CBCR`` control. + * - ``V4L2_COLORFX_SET_RGB`` + - The RGB components are replaced by the fixed RGB components determined + by ``V4L2_CID_COLORFX_RGB`` control. +``V4L2_CID_COLORFX_RGB`` ``(integer)`` + Determines the Red, Green, and Blue coefficients for + ``V4L2_COLORFX_SET_RGB`` color effect. + Bits [7:0] of the supplied 32 bit value are interpreted as Blue component, + bits [15:8] as Green component, bits [23:16] as Red component, and + bits [31:24] must be zero. ``V4L2_CID_COLORFX_CBCR`` ``(integer)`` Determines the Cb and Cr coefficients for ``V4L2_COLORFX_SET_CBCR`` diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c index 0cb6c0f18b39..431f7ec17557 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c +++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c @@ -785,6 +785,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: return "Min Number of Output Buffers"; case V4L2_CID_ALPHA_COMPONENT: return "Alpha Component"; case V4L2_CID_COLORFX_CBCR: return "Color Effects, CbCr"; + case V4L2_CID_COLORFX_RGB: return "Color Effects, RGB"; /* * Codec controls @@ -1394,11 +1395,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, *min = *max = *step = *def = 0; break; case V4L2_CID_BG_COLOR: + case V4L2_CID_COLORFX_RGB: *type = V4L2_CTRL_TYPE_INTEGER; *step = 1; *min = 0; - /* Max is calculated as RGB888 that is 2^24 */ - *max = 0xFFFFFF; + /* Max is calculated as RGB888 that is 2^24 - 1 */ + *max = 0xffffff; break; case V4L2_CID_COLORFX_CBCR: *type = V4L2_CTRL_TYPE_INTEGER; diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 133e20444939..1406df0cc107 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -128,6 +128,7 @@ enum v4l2_colorfx { V4L2_COLORFX_SOLARIZATION = 13, V4L2_COLORFX_ANTIQUE = 14, V4L2_COLORFX_SET_CBCR = 15, + V4L2_COLORFX_SET_RGB = 16, }; #define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) #define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) @@ -145,9 +146,10 @@ enum v4l2_colorfx { #define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) #define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) +#define V4L2_CID_COLORFX_RGB (V4L2_CID_BASE + 43) /* last CID + 1 */ -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) +#define V4L2_CID_LASTP1 (V4L2_CID_BASE + 44) /* USER-class private control IDs */ From patchwork Tue Oct 19 08:43:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C76F2C433F5 for ; Tue, 19 Oct 2021 08:44:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AFFDE60EB9 for ; Tue, 19 Oct 2021 08:44:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234834AbhJSIqe (ORCPT ); Tue, 19 Oct 2021 04:46:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234925AbhJSIq3 (ORCPT ); Tue, 19 Oct 2021 04:46:29 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4C27C061768; Tue, 19 Oct 2021 01:44:14 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d9so9817997pfl.6; Tue, 19 Oct 2021 01:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Qf2pjhCpfk07YQKtxJ7Ycuq1vo5ZtJccHCuLQD7alI0=; b=RLrSpFbXOk9mKOfE+/CLCAUA8uCHIMz3SBRn996JqGd+oOkg9sDjTATvfD9We6xH/i sRStywzhdvf0TRWHhm+RH0Bcm6ae+vKn98Rmhmecq92q4YeqeuTiwo5sXnpkBDEQmCBa sKbIXuZFdQIxrF2wM1yceaDJZtSYA+n6iWnsBslT8wsyhhG12aIMQ2OEVT0dsMhPMGGw DZa3rUH7h+jZ5SVygqD8zzh8/+fNM0a83/CQUzxcMk/fuhbZ8/7p32gT7zmLfpXPlvIq +PAA7Lh0BVHkkpafxeRqMdpC19sEqZlbrh/XC+G1YwaO1Z6wShdCOckiRrv7vZ35Lznp 2uDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Qf2pjhCpfk07YQKtxJ7Ycuq1vo5ZtJccHCuLQD7alI0=; b=JQdE7IU7oTAPX4+pnaBfOQWPr4b1vWSEOJPPKowYgVgJYfzCvVo0IIeCU5+rcV33ZW cWGuykruEN+5VVkSKU8Gmh2hdzXGDD0oTEWOHBn8FZnT94xj8ZKpnK4dRUhiHAyxOU3g BWEC5B6u5FepRTuqLn6vwKYx0GOGLP7qK/OWos3MOS5HMXDOTIdknzBFB57U8u7q+cGS w58h5XDD/7VXBV57W4bwtm07xP3LGqI0eo4CHPshJ3Yg6eycG1Q0+XOyIq7j1FXI7sue BHX1mmueu8CJXqtjjMeWPUuDsSPq0YCZgu2ZXl5dGKmAK9zewxZDxVGRPjt3ImedG1+R vDdw== X-Gm-Message-State: AOAM531cfaij2CgBUtDTek80UaTLDKsVxwvnDkh1NALPZowSSFiXI/5L 1eKX2ctSSPYs6W4/AmFIzRE= X-Google-Smtp-Source: ABdhPJyldc/nOmHnQzAvE7388dI4Radsjo0IQ0KG1jEUqZoRWSO82e9aTHcG8Mp9CkR2nSbMCLLR8g== X-Received: by 2002:a63:1266:: with SMTP id 38mr27685059pgs.219.1634633054300; Tue, 19 Oct 2021 01:44:14 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.44.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:44:14 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 09/10] clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell Date: Tue, 19 Oct 2021 16:43:22 +0800 Message-Id: <1634633003-18132-10-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org stm32's clk driver register two ltdc gate clk to clk core by clk_hw_register_gate() and clk_hw_register_composite() first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use. second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver both of them point to the same offset of stm32's RCC register. after kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]' is no one to use. but, actually 'stm32f429_aux_clk[]' is in use. stm32f469/746/769 have the same issue, fix it. Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") Acked-by: Stephen Boyd Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-7-git-send-email-dillon.minfei@gmail.com/ Link: https://lore.kernel.org/lkml/CAPTRvHkf0cK_4ZidM17rPo99gWDmxgqFt4CDUjqFFwkOeQeFDg@mail.gmail.com/ Signed-off-by: Dillon Min --- v6: no change. drivers/clk/clk-stm32f4.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index af46176ad053..473dfe632cc5 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, }; static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { @@ -211,7 +210,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, }; static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { @@ -286,7 +284,6 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, }; static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { @@ -364,7 +361,6 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" }, }; From patchwork Tue Oct 19 08:43:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12569115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CCC2C433F5 for ; Tue, 19 Oct 2021 08:44:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8498460EB9 for ; Tue, 19 Oct 2021 08:44:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234899AbhJSIql (ORCPT ); Tue, 19 Oct 2021 04:46:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234858AbhJSIqd (ORCPT ); Tue, 19 Oct 2021 04:46:33 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 906AEC06161C; Tue, 19 Oct 2021 01:44:20 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id r2so18690555pgl.10; Tue, 19 Oct 2021 01:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KzBwc0vSYR0kZLTI8lM5juV0/8lPkqexQ27R5+OhJDc=; b=H6AP7GBhOuxzBUL/nyvQRhYxsywQ0FJ7hZWt3Nh9gOLcT5sB44WQVIbNiLJFS6EhSM 07gAd+X1ey3vjB8Zs0SWehGfuACOW8JCIREFzQiyZNoAB9WuWiXTpQ4DDkQ6MiNZVBgD J9RMTXq3/DMmXjNGNPx+9qQ3YpDVDJD42hGhGV3atQ78gnyxvODAW1FWFYSpCJtNdWvl kT+YYQtWelHaZ36Me4BPJggE+g3j2JG0NQF8Orfqn8b0mvAhZzdyb58uzS0aO+ij8BGH LJz2Grt7czoyfo6iR8JUcCs8Z9yAYlM3ImS2c9SnFkjh2jCGg+fl0M/89J9uMRM6+HSV ce/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KzBwc0vSYR0kZLTI8lM5juV0/8lPkqexQ27R5+OhJDc=; b=7x+dQkQVdmZ1tlaijs96QG3e97KX2iVUX9DNrVGOfm1CpWXDWMESNZ5halODMMi2xz CygOmchsCvNY0VYZ4jkbX6LC+ogODMfoIDsLAn+eOByITVgBtt28yyHrMD8Wrp2k5Nvk G1LkD50AkOzGQxw8xkTlW5mQyXyWi8XlX8EPsIfdK5rrhM3Ck9tQKoneru31AFuB8bOC 191uxea+N3VPmcQjNQpl4tqOapxdyitv7lB1hSaqKENMQOWDrCfGFkX1o90EsgGEpX9/ JDw9uDZL6EUzUJa07+VCDQuumy4y9YuXVY6nz5wGEoxJ+54rFAZ71KID+/QisvITeF5I 0glw== X-Gm-Message-State: AOAM533Hm289pv7jrAQbhTsjftUXxJFt8Spi23eyvmimwRMHfTEdIV3w L2sd8cTxYi5mM3eJyOlZg44= X-Google-Smtp-Source: ABdhPJxS2URASW7Sk5I0Gk85F8TbH9HbMTvmTGzxaSsErg4WTNYl4eWbeDeyowxyle3rGGapNz3kzg== X-Received: by 2002:a63:f84f:: with SMTP id v15mr28065330pgj.204.1634633059797; Tue, 19 Oct 2021 01:44:19 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id c11sm1824716pji.38.2021.10.19.01.44.14 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Oct 2021 01:44:19 -0700 (PDT) From: Dillon Min To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, gabriel.fernandez@st.com, gabriel.fernandez@foss.st.com Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 10/10] media: stm32-dma2d: STM32 DMA2D driver Date: Tue, 19 Oct 2021 16:43:23 +0800 Message-Id: <1634633003-18132-11-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> References: <1634633003-18132-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This V4L2 subdev m2m driver enables Chrom-Art Accelerator unit of STMicroelectronics STM32 SoC series. Currently support r2m, m2m, m2m_pfc functions. - r2m, Filling a part or the whole of a destination image with a specific color. - m2m, Copying a part or the whole of a source image into a part or the whole of a destination. - m2m_pfc, Copying a part or the whole of a source image into a part or the whole of a destination image with a pixel format conversion. Signed-off-by: Dillon Min --- v6: use 2592x2592 instead of 0x3fff, 0xffff. drivers/media/platform/Kconfig | 11 + drivers/media/platform/Makefile | 1 + drivers/media/platform/stm32/Makefile | 2 + drivers/media/platform/stm32/dma2d/dma2d-hw.c | 143 +++++ drivers/media/platform/stm32/dma2d/dma2d-regs.h | 113 ++++ drivers/media/platform/stm32/dma2d/dma2d.c | 739 ++++++++++++++++++++++++ drivers/media/platform/stm32/dma2d/dma2d.h | 135 +++++ 7 files changed, 1144 insertions(+) create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-hw.c create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-regs.h create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.c create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index d9f90084c2f6..0b3bdf56b44e 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -476,6 +476,17 @@ config VIDEO_STI_DELTA_DRIVER endif # VIDEO_STI_DELTA +config VIDEO_STM32_DMA2D + tristate "STM32 Chrom-Art Accelerator (DMA2D)" + depends on (VIDEO_DEV && VIDEO_V4L2 && ARCH_STM32) || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select V4L2_MEM2MEM_DEV + help + Enables DMA2D hwarware support on stm32. + + The STM32 DMA2D is a memory-to-memory engine for pixel conversion + and specialized DMA dedicated to image manipulation. + config VIDEO_RENESAS_FDP1 tristate "Renesas Fine Display Processor" depends on VIDEO_DEV && VIDEO_V4L2 diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 73ce083c2fc6..46f1c05bc576 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/ obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/ obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/ +obj-$(CONFIG_VIDEO_STM32_DMA2D) += stm32/ obj-$(CONFIG_VIDEO_MEDIATEK_VPU) += mtk-vpu/ diff --git a/drivers/media/platform/stm32/Makefile b/drivers/media/platform/stm32/Makefile index 48b36db2c2e2..896ef98a73ab 100644 --- a/drivers/media/platform/stm32/Makefile +++ b/drivers/media/platform/stm32/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32-dcmi.o +stm32-dma2d-objs := dma2d/dma2d.o dma2d/dma2d-hw.o +obj-$(CONFIG_VIDEO_STM32_DMA2D) += stm32-dma2d.o diff --git a/drivers/media/platform/stm32/dma2d/dma2d-hw.c b/drivers/media/platform/stm32/dma2d/dma2d-hw.c new file mode 100644 index 000000000000..8c1c664ab13b --- /dev/null +++ b/drivers/media/platform/stm32/dma2d/dma2d-hw.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver + * + * Copyright (c) 2021 Dillon Min + * Dillon Min, + * + * based on s5p-g2d + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Kamil Debski, + */ + +#include + +#include "dma2d.h" +#include "dma2d-regs.h" + +static inline u32 reg_read(void __iomem *base, u32 reg) +{ + return readl_relaxed(base + reg); +} + +static inline void reg_write(void __iomem *base, u32 reg, u32 val) +{ + writel_relaxed(val, base + reg); +} + +static inline void reg_set(void __iomem *base, u32 reg, u32 mask) +{ + reg_write(base, reg, reg_read(base, reg) | mask); +} + +static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) +{ + reg_write(base, reg, reg_read(base, reg) & ~mask); +} + +static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, + u32 val) +{ + reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); +} + +void dma2d_start(struct dma2d_dev *d) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START); +} + +u32 dma2d_get_int(struct dma2d_dev *d) +{ + return reg_read(d->regs, DMA2D_ISR_REG); +} + +void dma2d_clear_int(struct dma2d_dev *d) +{ + u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG); + + reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); +} + +void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode, + u16 width, u16 height) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK, + op_mode << CR_MODE_SHIFT); + + reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); +} + +void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t o_addr) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_ARGB4444) + reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_write(d->regs, DMA2D_OMAR_REG, o_addr); + + reg_write(d->regs, DMA2D_OCOLR_REG, + (frm->a_rgb[3] << 24) | + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); + + reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK, + frm->line_offset & 0x3fff); +} + +void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t f_addr) +{ + reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); + reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK, + frm->line_offset); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_A4) + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK, + (frm->a_mode << 16) & 0x03); + + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK, + frm->a_rgb[3] << 24); + + reg_write(d->regs, DMA2D_FGCOLR_REG, + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); +} + +void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t b_addr) +{ + reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); + reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK, + frm->line_offset); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_A4) + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK, + (frm->a_mode << 16) & 0x03); + + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK, + frm->a_rgb[3] << 24); + + reg_write(d->regs, DMA2D_BGCOLR_REG, + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); +} diff --git a/drivers/media/platform/stm32/dma2d/dma2d-regs.h b/drivers/media/platform/stm32/dma2d/dma2d-regs.h new file mode 100644 index 000000000000..6444592d415b --- /dev/null +++ b/drivers/media/platform/stm32/dma2d/dma2d-regs.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver + * + * Copyright (c) 2021 Dillon Min + * Dillon Min, + * + * based on s5p-g2d + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Kamil Debski, + */ + +#ifndef __DMA2D_REGS_H__ +#define __DMA2D_REGS_H__ + +#define DMA2D_CR_REG 0x0000 +#define CR_MODE_MASK GENMASK(17, 16) +#define CR_MODE_SHIFT 16 +#define CR_M2M 0x0000 +#define CR_M2M_PFC BIT(16) +#define CR_M2M_BLEND BIT(17) +#define CR_R2M (BIT(17) | BIT(16)) +#define CR_CEIE BIT(13) +#define CR_CTCIE BIT(12) +#define CR_CAEIE BIT(11) +#define CR_TWIE BIT(10) +#define CR_TCIE BIT(9) +#define CR_TEIE BIT(8) +#define CR_ABORT BIT(2) +#define CR_SUSP BIT(1) +#define CR_START BIT(0) + +#define DMA2D_ISR_REG 0x0004 +#define ISR_CEIF BIT(5) +#define ISR_CTCIF BIT(4) +#define ISR_CAEIF BIT(3) +#define ISR_TWIF BIT(2) +#define ISR_TCIF BIT(1) +#define ISR_TEIF BIT(0) + +#define DMA2D_IFCR_REG 0x0008 +#define IFCR_CCEIF BIT(5) +#define IFCR_CCTCIF BIT(4) +#define IFCR_CAECIF BIT(3) +#define IFCR_CTWIF BIT(2) +#define IFCR_CTCIF BIT(1) +#define IFCR_CTEIF BIT(0) + +#define DMA2D_FGMAR_REG 0x000c +#define DMA2D_FGOR_REG 0x0010 +#define FGOR_LO_MASK GENMASK(13, 0) + +#define DMA2D_BGMAR_REG 0x0014 +#define DMA2D_BGOR_REG 0x0018 +#define BGOR_LO_MASK GENMASK(13, 0) + +#define DMA2D_FGPFCCR_REG 0x001c +#define FGPFCCR_ALPHA_MASK GENMASK(31, 24) +#define FGPFCCR_AM_MASK GENMASK(17, 16) +#define FGPFCCR_CS_MASK GENMASK(15, 8) +#define FGPFCCR_START BIT(5) +#define FGPFCCR_CCM_RGB888 BIT(4) +#define FGPFCCR_CM_MASK GENMASK(3, 0) + +#define DMA2D_FGCOLR_REG 0x0020 +#define FGCOLR_REG_MASK GENMASK(23, 16) +#define FGCOLR_GREEN_MASK GENMASK(15, 8) +#define FGCOLR_BLUE_MASK GENMASK(7, 0) + +#define DMA2D_BGPFCCR_REG 0x0024 +#define BGPFCCR_ALPHA_MASK GENMASK(31, 24) +#define BGPFCCR_AM_MASK GENMASK(17, 16) +#define BGPFCCR_CS_MASK GENMASK(15, 8) +#define BGPFCCR_START BIT(5) +#define BGPFCCR_CCM_RGB888 BIT(4) +#define BGPFCCR_CM_MASK GENMASK(3, 0) + +#define DMA2D_BGCOLR_REG 0x0028 +#define BGCOLR_REG_MASK GENMASK(23, 16) +#define BGCOLR_GREEN_MASK GENMASK(15, 8) +#define BGCOLR_BLUE_MASK GENMASK(7, 0) + +#define DMA2D_OPFCCR_REG 0x0034 +#define OPFCCR_CM_MASK GENMASK(2, 0) + +#define DMA2D_OCOLR_REG 0x0038 +#define OCOLR_ALPHA_MASK GENMASK(31, 24) +#define OCOLR_RED_MASK GENMASK(23, 16) +#define OCOLR_GREEN_MASK GENMASK(15, 8) +#define OCOLR_BLUE_MASK GENMASK(7, 0) + +#define DMA2D_OMAR_REG 0x003c + +#define DMA2D_OOR_REG 0x0040 +#define OOR_LO_MASK GENMASK(13, 0) + +#define DMA2D_NLR_REG 0x0044 +#define NLR_PL_MASK GENMASK(29, 16) +#define NLR_NL_MASK GENMASK(15, 0) + +/* Hardware limits */ +#define MAX_WIDTH 2592 +#define MAX_HEIGHT 2592 + +#define DEFAULT_WIDTH 240 +#define DEFAULT_HEIGHT 320 +#define DEFAULT_SIZE 307200 + +#define CM_MODE_ARGB8888 0x00 +#define CM_MODE_ARGB4444 0x04 +#define CM_MODE_A4 0x0a +#endif /* __DMA2D_REGS_H__ */ diff --git a/drivers/media/platform/stm32/dma2d/dma2d.c b/drivers/media/platform/stm32/dma2d/dma2d.c new file mode 100644 index 000000000000..17af90d86898 --- /dev/null +++ b/drivers/media/platform/stm32/dma2d/dma2d.c @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * STM32 DMA2D - 2D Graphics Accelerator Driver + * + * Copyright (c) 2021 Dillon Min + * Dillon Min, + * + * based on s5p-g2d + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Kamil Debski, + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "dma2d.h" +#include "dma2d-regs.h" + +/* + * This V4L2 subdev m2m driver enables Chrom-Art Accelerator unit + * of STMicroelectronics STM32 SoC series. + * + * Currently support r2m, m2m, m2m_pfc. + * + * - r2m, Filling a part or the whole of a destination image with a specific + * color. + * - m2m, Copying a part or the whole of a source image into a part or the + * whole of a destination. + * - m2m_pfc, Copying a part or the whole of a source image into a part or the + * whole of a destination image with a pixel format conversion. + */ + +#define fh2ctx(__fh) container_of(__fh, struct dma2d_ctx, fh) + +static const struct dma2d_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_ARGB32, + .cmode = DMA2D_CMODE_ARGB8888, + .depth = 32, + }, + { + .fourcc = V4L2_PIX_FMT_RGB24, + .cmode = DMA2D_CMODE_RGB888, + .depth = 24, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + .cmode = DMA2D_CMODE_RGB565, + .depth = 16, + }, + { + .fourcc = V4L2_PIX_FMT_ARGB555, + .cmode = DMA2D_CMODE_ARGB1555, + .depth = 16, + }, + { + .fourcc = V4L2_PIX_FMT_ARGB444, + .cmode = DMA2D_CMODE_ARGB4444, + .depth = 16, + }, +}; + +#define NUM_FORMATS ARRAY_SIZE(formats) + +static const struct dma2d_frame def_frame = { + .width = DEFAULT_WIDTH, + .height = DEFAULT_HEIGHT, + .line_offset = 0, + .a_rgb = {0x00, 0x00, 0x00, 0xff}, + .a_mode = DMA2D_ALPHA_MODE_NO_MODIF, + .fmt = (struct dma2d_fmt *)&formats[0], + .size = DEFAULT_SIZE, +}; + +static struct dma2d_fmt *find_fmt(int pixelformat) +{ + unsigned int i; + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].fourcc == pixelformat) + return (struct dma2d_fmt *)&formats[i]; + } + + return NULL; +} + +static struct dma2d_frame *get_frame(struct dma2d_ctx *ctx, + enum v4l2_buf_type type) +{ + return V4L2_TYPE_IS_OUTPUT(type) ? &ctx->cap : &ctx->out; +} + +static int dma2d_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct dma2d_ctx *ctx = vb2_get_drv_priv(vq); + struct dma2d_frame *f = get_frame(ctx, vq->type); + + if (*nplanes) + return sizes[0] < f->size ? -EINVAL : 0; + + sizes[0] = f->size; + *nplanes = 1; + + return 0; +} + +static int dma2d_buf_out_validate(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + + if (vbuf->field == V4L2_FIELD_ANY) + vbuf->field = V4L2_FIELD_NONE; + if (vbuf->field != V4L2_FIELD_NONE) + return -EINVAL; + + return 0; +} + +static int dma2d_buf_prepare(struct vb2_buffer *vb) +{ + struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + struct dma2d_frame *f = get_frame(ctx, vb->vb2_queue->type); + + if (vb2_plane_size(vb, 0) < f->size) + return -EINVAL; + + vb2_set_plane_payload(vb, 0, f->size); + + return 0; +} + +static void dma2d_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); +} + +static int dma2d_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct dma2d_ctx *ctx = vb2_get_drv_priv(q); + struct dma2d_frame *f = get_frame(ctx, q->type); + + f->sequence = 0; + return 0; +} + +static void dma2d_stop_streaming(struct vb2_queue *q) +{ + struct dma2d_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *vbuf; + + for (;;) { + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (!vbuf) + return; + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } +} + +static const struct vb2_ops dma2d_qops = { + .queue_setup = dma2d_queue_setup, + .buf_out_validate = dma2d_buf_out_validate, + .buf_prepare = dma2d_buf_prepare, + .buf_queue = dma2d_buf_queue, + .start_streaming = dma2d_start_streaming, + .stop_streaming = dma2d_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct dma2d_ctx *ctx = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->drv_priv = ctx; + src_vq->ops = &dma2d_qops; + src_vq->mem_ops = &vb2_dma_contig_memops; + src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->lock = &ctx->dev->mutex; + src_vq->dev = ctx->dev->v4l2_dev.dev; + + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->drv_priv = ctx; + dst_vq->ops = &dma2d_qops; + dst_vq->mem_ops = &vb2_dma_contig_memops; + dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->lock = &ctx->dev->mutex; + dst_vq->dev = ctx->dev->v4l2_dev.dev; + + return vb2_queue_init(dst_vq); +} + +static int dma2d_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct dma2d_frame *frm; + struct dma2d_ctx *ctx = container_of(ctrl->handler, struct dma2d_ctx, + ctrl_handler); + unsigned long flags; + + spin_lock_irqsave(&ctx->dev->ctrl_lock, flags); + switch (ctrl->id) { + case V4L2_CID_COLORFX: + if (ctrl->val == V4L2_COLORFX_SET_RGB) + ctx->op_mode = DMA2D_MODE_R2M; + else if (ctrl->val == V4L2_COLORFX_NONE) + ctx->op_mode = DMA2D_MODE_M2M; + break; + case V4L2_CID_COLORFX_RGB: + frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + frm->a_rgb[2] = (ctrl->val >> 16) & 0xff; + frm->a_rgb[1] = (ctrl->val >> 8) & 0xff; + frm->a_rgb[0] = (ctrl->val >> 0) & 0xff; + break; + default: + spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags); + return -EINVAL; + } + spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags); + + return 0; +} + +static const struct v4l2_ctrl_ops dma2d_ctrl_ops = { + .s_ctrl = dma2d_s_ctrl, +}; + +static int dma2d_setup_ctrls(struct dma2d_ctx *ctx) +{ + struct v4l2_ctrl_handler *handler = &ctx->ctrl_handler; + + v4l2_ctrl_handler_init(handler, 2); + + v4l2_ctrl_new_std_menu(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX, + V4L2_COLORFX_SET_RGB, ~0x10001, + V4L2_COLORFX_NONE); + + v4l2_ctrl_new_std(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX_RGB, 0, + 0xffffff, 1, 0); + + return 0; +} + +static int dma2d_open(struct file *file) +{ + struct dma2d_dev *dev = video_drvdata(file); + struct dma2d_ctx *ctx = NULL; + int ret = 0; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + ctx->dev = dev; + /* Set default formats */ + ctx->cap = def_frame; + ctx->bg = def_frame; + ctx->out = def_frame; + ctx->op_mode = DMA2D_MODE_M2M_FPC; + ctx->colorspace = V4L2_COLORSPACE_REC709; + if (mutex_lock_interruptible(&dev->mutex)) { + kfree(ctx); + return -ERESTARTSYS; + } + + ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init); + if (IS_ERR(ctx->fh.m2m_ctx)) { + ret = PTR_ERR(ctx->fh.m2m_ctx); + mutex_unlock(&dev->mutex); + kfree(ctx); + return ret; + } + + v4l2_fh_init(&ctx->fh, video_devdata(file)); + file->private_data = &ctx->fh; + v4l2_fh_add(&ctx->fh); + + dma2d_setup_ctrls(ctx); + + /* Write the default values to the ctx struct */ + v4l2_ctrl_handler_setup(&ctx->ctrl_handler); + + ctx->fh.ctrl_handler = &ctx->ctrl_handler; + mutex_unlock(&dev->mutex); + + return 0; +} + +static int dma2d_release(struct file *file) +{ + struct dma2d_dev *dev = video_drvdata(file); + struct dma2d_ctx *ctx = fh2ctx(file->private_data); + + mutex_lock(&dev->mutex); + v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); + mutex_unlock(&dev->mutex); + v4l2_ctrl_handler_free(&ctx->ctrl_handler); + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + kfree(ctx); + + return 0; +} + +static int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, DMA2D_NAME, sizeof(cap->driver)); + strscpy(cap->card, DMA2D_NAME, sizeof(cap->card)); + strscpy(cap->bus_info, BUS_INFO, sizeof(cap->bus_info)); + + return 0; +} + +static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f) +{ + if (f->index >= NUM_FORMATS) + return -EINVAL; + + f->pixelformat = formats[f->index].fourcc; + return 0; +} + +static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f) +{ + struct dma2d_ctx *ctx = prv; + struct vb2_queue *vq; + struct dma2d_frame *frm; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + + frm = get_frame(ctx, f->type); + f->fmt.pix.width = frm->width; + f->fmt.pix.height = frm->height; + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.pixelformat = frm->fmt->fourcc; + f->fmt.pix.bytesperline = (frm->width * frm->fmt->depth) >> 3; + f->fmt.pix.sizeimage = frm->size; + f->fmt.pix.colorspace = ctx->colorspace; + f->fmt.pix.xfer_func = ctx->xfer_func; + f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc; + f->fmt.pix.quantization = ctx->quant; + + return 0; +} + +static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f) +{ + struct dma2d_ctx *ctx = prv; + struct dma2d_fmt *fmt; + enum v4l2_field *field; + u32 fourcc = f->fmt.pix.pixelformat; + + fmt = find_fmt(fourcc); + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_fmt(f->fmt.pix.pixelformat); + } + + field = &f->fmt.pix.field; + if (*field == V4L2_FIELD_ANY) + *field = V4L2_FIELD_NONE; + else if (*field != V4L2_FIELD_NONE) + return -EINVAL; + + if (f->fmt.pix.width > MAX_WIDTH) + f->fmt.pix.width = MAX_WIDTH; + if (f->fmt.pix.height > MAX_HEIGHT) + f->fmt.pix.height = MAX_HEIGHT; + + if (f->fmt.pix.width < 1) + f->fmt.pix.width = 1; + if (f->fmt.pix.height < 1) + f->fmt.pix.height = 1; + + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && !f->fmt.pix.colorspace) { + f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709; + } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + f->fmt.pix.colorspace = ctx->colorspace; + f->fmt.pix.xfer_func = ctx->xfer_func; + f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc; + f->fmt.pix.quantization = ctx->quant; + } + f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; + + return 0; +} + +static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f) +{ + struct dma2d_ctx *ctx = prv; + struct vb2_queue *vq; + struct dma2d_frame *frm; + struct dma2d_fmt *fmt; + int ret = 0; + + /* Adjust all values accordingly to the hardware capabilities + * and chosen format. + */ + ret = vidioc_try_fmt(file, prv, f); + if (ret) + return ret; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (vb2_is_busy(vq)) + return -EBUSY; + + fmt = find_fmt(f->fmt.pix.pixelformat); + if (!fmt) + return -EINVAL; + + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + ctx->colorspace = f->fmt.pix.colorspace; + ctx->xfer_func = f->fmt.pix.xfer_func; + ctx->ycbcr_enc = f->fmt.pix.ycbcr_enc; + ctx->quant = f->fmt.pix.quantization; + } + + frm = get_frame(ctx, f->type); + frm->width = f->fmt.pix.width; + frm->height = f->fmt.pix.height; + frm->size = f->fmt.pix.sizeimage; + /* Reset crop settings */ + frm->o_width = 0; + frm->o_height = 0; + frm->c_width = frm->width; + frm->c_height = frm->height; + frm->right = frm->width; + frm->bottom = frm->height; + frm->fmt = fmt; + frm->line_offset = 0; + + return 0; +} + +static void device_run(void *prv) +{ + struct dma2d_ctx *ctx = prv; + struct dma2d_dev *dev = ctx->dev; + struct dma2d_frame *frm_out, *frm_cap; + struct vb2_v4l2_buffer *src, *dst; + unsigned long flags; + + spin_lock_irqsave(&dev->ctrl_lock, flags); + dev->curr = ctx; + + src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + if (!dst || !src) + goto end; + + frm_cap = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + frm_out = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + if (!frm_cap || !frm_out) + goto end; + + src->sequence = frm_out->sequence++; + dst->sequence = frm_cap->sequence++; + v4l2_m2m_buf_copy_metadata(src, dst, true); + + clk_enable(dev->gate); + + dma2d_config_fg(dev, frm_out, + vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0)); + + /* TODO: add M2M_BLEND handler here */ + + if (ctx->op_mode != DMA2D_MODE_R2M) { + if (frm_out->fmt->fourcc == frm_cap->fmt->fourcc) + ctx->op_mode = DMA2D_MODE_M2M; + else + ctx->op_mode = DMA2D_MODE_M2M_FPC; + } + + dma2d_config_out(dev, frm_cap, + vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0)); + dma2d_config_common(dev, ctx->op_mode, frm_cap->width, frm_cap->height); + + dma2d_start(dev); +end: + spin_unlock_irqrestore(&dev->ctrl_lock, flags); +} + +static irqreturn_t dma2d_isr(int irq, void *prv) +{ + struct dma2d_dev *dev = prv; + struct dma2d_ctx *ctx = dev->curr; + struct vb2_v4l2_buffer *src, *dst; + u32 s = dma2d_get_int(dev); + + dma2d_clear_int(dev); + if (s & ISR_TCIF || s == 0) { + clk_disable(dev->gate); + + WARN_ON(!ctx); + + src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + WARN_ON(!dst); + WARN_ON(!src); + + v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); + v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); + v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx); + + dev->curr = NULL; + } + + return IRQ_HANDLED; +} + +static const struct v4l2_file_operations dma2d_fops = { + .owner = THIS_MODULE, + .open = dma2d_open, + .release = dma2d_release, + .poll = v4l2_m2m_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = v4l2_m2m_fop_mmap, +#ifndef CONFIG_MMU + .get_unmapped_area = v4l2_m2m_get_unmapped_area, +#endif +}; + +static const struct v4l2_ioctl_ops dma2d_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt, + + .vidioc_enum_fmt_vid_out = vidioc_enum_fmt, + .vidioc_g_fmt_vid_out = vidioc_g_fmt, + .vidioc_try_fmt_vid_out = vidioc_try_fmt, + .vidioc_s_fmt_vid_out = vidioc_s_fmt, + + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static const struct video_device dma2d_videodev = { + .name = DMA2D_NAME, + .fops = &dma2d_fops, + .ioctl_ops = &dma2d_ioctl_ops, + .minor = -1, + .release = video_device_release, + .vfl_dir = VFL_DIR_M2M, +}; + +static const struct v4l2_m2m_ops dma2d_m2m_ops = { + .device_run = device_run, +}; + +static const struct of_device_id stm32_dma2d_match[]; + +static int dma2d_probe(struct platform_device *pdev) +{ + struct dma2d_dev *dev; + struct video_device *vfd; + struct resource *res; + int ret = 0; + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + spin_lock_init(&dev->ctrl_lock); + mutex_init(&dev->mutex); + atomic_set(&dev->num_inst, 0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + dev->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dev->regs)) + return PTR_ERR(dev->regs); + + dev->gate = clk_get(&pdev->dev, "dma2d"); + if (IS_ERR(dev->gate)) { + dev_err(&pdev->dev, "failed to get dma2d clock gate\n"); + ret = -ENXIO; + return ret; + } + + ret = clk_prepare(dev->gate); + if (ret) { + dev_err(&pdev->dev, "failed to prepare dma2d clock gate\n"); + goto put_clk_gate; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, "failed to find IRQ\n"); + ret = -ENXIO; + goto unprep_clk_gate; + } + + dev->irq = res->start; + + ret = devm_request_irq(&pdev->dev, dev->irq, dma2d_isr, + 0, pdev->name, dev); + if (ret) { + dev_err(&pdev->dev, "failed to install IRQ\n"); + goto unprep_clk_gate; + } + + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); + if (ret) + goto unprep_clk_gate; + + vfd = video_device_alloc(); + if (!vfd) { + v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); + ret = -ENOMEM; + goto unreg_v4l2_dev; + } + + *vfd = dma2d_videodev; + vfd->lock = &dev->mutex; + vfd->v4l2_dev = &dev->v4l2_dev; + vfd->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING; + + platform_set_drvdata(pdev, dev); + dev->m2m_dev = v4l2_m2m_init(&dma2d_m2m_ops); + if (IS_ERR(dev->m2m_dev)) { + v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n"); + ret = PTR_ERR(dev->m2m_dev); + goto rel_vdev; + } + + ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); + if (ret) { + v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); + goto free_m2m; + } + + video_set_drvdata(vfd, dev); + dev->vfd = vfd; + v4l2_info(&dev->v4l2_dev, "device registered as /dev/video%d\n", + vfd->num); + return 0; + +free_m2m: + v4l2_m2m_release(dev->m2m_dev); +rel_vdev: + video_device_release(vfd); +unreg_v4l2_dev: + v4l2_device_unregister(&dev->v4l2_dev); +unprep_clk_gate: + clk_unprepare(dev->gate); +put_clk_gate: + clk_put(dev->gate); + + return ret; +} + +static int dma2d_remove(struct platform_device *pdev) +{ + struct dma2d_dev *dev = platform_get_drvdata(pdev); + + v4l2_info(&dev->v4l2_dev, "Removing " DMA2D_NAME); + v4l2_m2m_release(dev->m2m_dev); + video_unregister_device(dev->vfd); + v4l2_device_unregister(&dev->v4l2_dev); + vb2_dma_contig_clear_max_seg_size(&pdev->dev); + clk_unprepare(dev->gate); + clk_put(dev->gate); + + return 0; +} + +static const struct of_device_id stm32_dma2d_match[] = { + { + .compatible = "st,stm32-dma2d", + .data = NULL, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_dma2d_match); + +static struct platform_driver dma2d_pdrv = { + .probe = dma2d_probe, + .remove = dma2d_remove, + .driver = { + .name = DMA2D_NAME, + .of_match_table = stm32_dma2d_match, + }, +}; + +module_platform_driver(dma2d_pdrv); + +MODULE_AUTHOR("Dillon Min "); +MODULE_DESCRIPTION("STM32 Chrom-Art Accelerator DMA2D driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/stm32/dma2d/dma2d.h b/drivers/media/platform/stm32/dma2d/dma2d.h new file mode 100644 index 000000000000..3f03a7ca9ee3 --- /dev/null +++ b/drivers/media/platform/stm32/dma2d/dma2d.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ST stm32 DMA2D - 2D Graphics Accelerator Driver + * + * Copyright (c) 2021 Dillon Min + * Dillon Min, + * + * based on s5p-g2d + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Kamil Debski, + */ + +#ifndef __DMA2D_H__ +#define __DMA2D_H__ + +#include +#include +#include + +#define DMA2D_NAME "stm-dma2d" +#define BUS_INFO "platform:stm-dma2d" +enum dma2d_op_mode { + DMA2D_MODE_M2M, + DMA2D_MODE_M2M_FPC, + DMA2D_MODE_M2M_BLEND, + DMA2D_MODE_R2M +}; + +enum dma2d_cmode { + /* output pfc cmode from ARGB888 to ARGB4444 */ + DMA2D_CMODE_ARGB8888, + DMA2D_CMODE_RGB888, + DMA2D_CMODE_RGB565, + DMA2D_CMODE_ARGB1555, + DMA2D_CMODE_ARGB4444, + /* bg or fg pfc cmode from L8 to A4 */ + DMA2D_CMODE_L8, + DMA2D_CMODE_AL44, + DMA2D_CMODE_AL88, + DMA2D_CMODE_L4, + DMA2D_CMODE_A8, + DMA2D_CMODE_A4 +}; + +enum dma2d_alpha_mode { + DMA2D_ALPHA_MODE_NO_MODIF, + DMA2D_ALPHA_MODE_REPLACE, + DMA2D_ALPHA_MODE_COMBINE +}; + +struct dma2d_fmt { + u32 fourcc; + int depth; + enum dma2d_cmode cmode; +}; + +struct dma2d_frame { + /* Original dimensions */ + u32 width; + u32 height; + /* Crop size */ + u32 c_width; + u32 c_height; + /* Offset */ + u32 o_width; + u32 o_height; + u32 bottom; + u32 right; + u16 line_offset; + /* Image format */ + struct dma2d_fmt *fmt; + /* [0]: blue + * [1]: green + * [2]: red + * [3]: alpha + */ + u8 a_rgb[4]; + /* + * AM[1:0] of DMA2D_FGPFCCR + */ + enum dma2d_alpha_mode a_mode; + u32 size; + unsigned int sequence; +}; + +struct dma2d_ctx { + struct v4l2_fh fh; + struct dma2d_dev *dev; + struct dma2d_frame cap; + struct dma2d_frame out; + struct dma2d_frame bg; + /* fb_buf always point to bg address */ + struct v4l2_framebuffer fb_buf; + /* + * MODE[17:16] of DMA2D_CR + */ + enum dma2d_op_mode op_mode; + struct v4l2_ctrl_handler ctrl_handler; + enum v4l2_colorspace colorspace; + enum v4l2_ycbcr_encoding ycbcr_enc; + enum v4l2_xfer_func xfer_func; + enum v4l2_quantization quant; +}; + +struct dma2d_dev { + struct v4l2_device v4l2_dev; + struct v4l2_m2m_dev *m2m_dev; + struct video_device *vfd; + /* for device open/close etc */ + struct mutex mutex; + /* to avoid the conflict with device running and user setting + * at the same time + */ + spinlock_t ctrl_lock; + atomic_t num_inst; + void __iomem *regs; + struct clk *gate; + struct dma2d_ctx *curr; + int irq; +}; + +void dma2d_start(struct dma2d_dev *d); +u32 dma2d_get_int(struct dma2d_dev *d); +void dma2d_clear_int(struct dma2d_dev *d); +void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t o_addr); +void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t f_addr); +void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t b_addr); +void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode, + u16 width, u16 height); + +#endif /* __DMA2D_H__ */