From patchwork Thu Dec 13 23:14:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10730055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45BEF91E for ; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3644A2CBD5 for ; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 27D6E2CE24; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AB4802CBD5 for ; Thu, 13 Dec 2018 23:15:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ACN3DnP2iQm1oBjgAxuEhMRKAoxupjBZ5dA91TbseqA=; b=laPEsDov9dpbaB5lv1gkoq+fdl ghyY7EO4Pdbt3JUb/xAYLa746i6Y+v3fbRqiMfR1loleG1zwu/rM8wRjWbU3MV/zUNmiHiYPFkMie 3N/Wqebjhg66VyAV1eMzTVaQjFmSomfm35FlmkeS0xkXNfu538ZPZnzGMbAuu/KRQ98mqEImeiOEO GNj0P2oyrAnTZJ/7Ds4KX6dixXx16YzU0mBPgXEvunttNnWIFy4YRX87Q4ykdB0VDJkcEMAGWAj6g +7XzUsMTq2B8VwWAVRCjQTxpZi8/fwIud5JyOxU36vUA7Gy6sUhjW0AyJKuSoqHBQUBEAliLNOUTd Ptvc6nJA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gXaCD-0004T3-6Q; Thu, 13 Dec 2018 23:15:09 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gXaC8-0003WL-OB for linux-riscv@lists.infradead.org; Thu, 13 Dec 2018 23:15:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1544742905; x=1576278905; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Dw7BVJruXEjQ+4ypD9yLQOYA/HM5jvLkotJAMWN215w=; b=i4Op6rYBz6frxmjG47IDvn2GqrcKooigIt4jhDlQbdtwl5hLw60HZBxx 2XzGSbRw7FTwnS7suOk/Lgo7cef7LpNckOkwT71ykpTlmgF/iPGdunnOJ h15xPf5EGi9RA+n+S63ou9CQadbhURs8o10qCt5zu+kHPukFzR2Agotuy UWt8ZMIckJrr7xaE/41O3LJDpjOzYfR4APORCzcTyFgIlhYt73MOEbMnx 8J2LEXCSJKvrd0+HTjrvXc47Fw+rt+lKoZotv2D+IclGyufUXd0qAnSPj mMAXSsxNkKflxu4egA98e8X4EnADpt+11xZZAqQ5+UePMb7jzzFciP8AJ A==; X-IronPort-AV: E=Sophos;i="5.56,350,1539619200"; d="scan'208";a="97770424" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 14 Dec 2018 07:14:52 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 13 Dec 2018 14:56:27 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:53 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Date: Thu, 13 Dec 2018 15:14:26 -0800 Message-Id: <1544742869-19980-2-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_151504_936361_EFF77571 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Damien Le Moal , Palmer Dabbelt , Dmitriy Cherkasov , Anup Patel , Daniel Lezcano , Rob Herring , Christoph Hellwig , Atish Patra , Albert Ou , Thomas Gleixner , linux-riscv@lists.infradead.org, Christoph Hellwig MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Palmer Dabbelt In RISC-V systems, timebase-frequency is per cpu instead of one instance for entire SOC as there is a individual timer per each CPU. Fix the DT binding accordingly. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph Hellwig [Atish: Update the commit text] Signed-off-by: Atish Patra Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af..b0b038d6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -93,9 +93,9 @@ Linux is allowed to run on. cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -113,6 +113,7 @@ Linux is allowed to run on. }; cpu@1 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart This device tree matches the Spike ISA golden model as run with `spike -p1`. cpus { + timebase-frequency = <1000000>; cpu@0 { device_type = "cpu"; reg = <0x00000000>; From patchwork Thu Dec 13 23:14:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10730057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDA1113AF for ; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD81B2CBD5 for ; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0C4F2CE24; Thu, 13 Dec 2018 23:15:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F45D2CBD5 for ; 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14 Dec 2018 07:14:53 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 13 Dec 2018 14:56:27 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:53 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Date: Thu, 13 Dec 2018 15:14:27 -0800 Message-Id: <1544742869-19980-3-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_151506_235950_50C3B40E X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Dmitriy Cherkasov , Anup Patel , Daniel Lezcano , Christoph Hellwig , Atish Patra , Rob Herring , Palmer Dabbelt , linux-riscv@lists.infradead.org, Thomas Gleixner MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Follow the updated DT specs and read the timebase-frequency from the boot cpu. Keep the old DT reading as well for backward compatibility. This patch is rework of old patch from Palmer. Signed-off-by: Atish Patra --- arch/riscv/kernel/time.c | 9 +-------- drivers/clocksource/riscv_timer.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 1911c8f6..225fe743 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -20,14 +20,7 @@ unsigned long riscv_timebase; void __init time_init(void) { - struct device_node *cpu; - u32 prop; - - cpu = of_find_node_by_path("/cpus"); - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); - riscv_timebase = prop; + timer_probe(); lpj_fine = riscv_timebase / HZ; - timer_probe(); } diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 084e97dc..75262409 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -83,6 +83,35 @@ void riscv_timer_interrupt(void) evdev->event_handler(evdev); } +static void __init riscv_timebase_frequency(struct device_node *node, + int hartid) +{ + u32 timebase; + + if (!of_property_read_u32(node, "timebase-frequency", &timebase)) + goto check; + + /* + * As per the DT specification, timebase-frequency should be present + * under individual cpu node. Unfortunately, there are already available + * HiFive Unleashed devices where the timebase-frequency entry is under + * CPUs. check under parent "cpus" node to cover those devices. + */ + if (!of_property_read_u32(node->parent, "timebase-frequency", + &timebase)) + goto check; + + panic("RISC-V system with no timebase-frequency in DTS for hart [%d]\n", + hartid); + +check: + /* RISC-V ISA specification mandates that every cpu has a timer */ + if (!riscv_timebase) + riscv_timebase = timebase; + else if (riscv_timebase && riscv_timebase != timebase) + pr_warn("RISC-V system with different timebase-frequency\n"); +} + static int __init riscv_timer_init_dt(struct device_node *n) { int cpuid, hartid, error; @@ -90,10 +119,12 @@ static int __init riscv_timer_init_dt(struct device_node *n) hartid = riscv_of_processor_hartid(n); cpuid = riscv_hartid_to_cpuid(hartid); + riscv_timebase_frequency(n, hartid); if (cpuid != smp_processor_id()) return 0; + /* This should be called only for boot cpu */ cs = per_cpu_ptr(&riscv_clocksource, cpuid); clocksource_register_hz(cs, riscv_timebase); From patchwork Thu Dec 13 23:14:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10730059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F027B13AF for ; Thu, 13 Dec 2018 23:15:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E29CB2CBD5 for ; Thu, 13 Dec 2018 23:15:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D62382CE24; Thu, 13 Dec 2018 23:15:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8C5552CBD5 for ; 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14 Dec 2018 07:14:53 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 13 Dec 2018 14:56:27 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:54 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Date: Thu, 13 Dec 2018 15:14:28 -0800 Message-Id: <1544742869-19980-4-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_151506_806460_A880BC96 X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Dmitriy Cherkasov , Anup Patel , Daniel Lezcano , Christoph Hellwig , Atish Patra , Rob Herring , Palmer Dabbelt , linux-riscv@lists.infradead.org, Thomas Gleixner MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- drivers/clocksource/riscv_timer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 75262409..c9e65086 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -49,7 +49,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) return get_cycles64(); } -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { +static struct clocksource riscv_clocksource = { .name = "riscv_clocksource", .rating = 300, .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), @@ -115,7 +115,6 @@ static void __init riscv_timebase_frequency(struct device_node *node, static int __init riscv_timer_init_dt(struct device_node *n) { int cpuid, hartid, error; - struct clocksource *cs; hartid = riscv_of_processor_hartid(n); cpuid = riscv_hartid_to_cpuid(hartid); @@ -125,8 +124,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) return 0; /* This should be called only for boot cpu */ - cs = per_cpu_ptr(&riscv_clocksource, cpuid); - clocksource_register_hz(cs, riscv_timebase); + clocksource_register_hz(&riscv_clocksource, riscv_timebase); error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", From patchwork Thu Dec 13 23:14:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10730061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B235C13AF for ; Thu, 13 Dec 2018 23:15:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2DC42CBD5 for ; Thu, 13 Dec 2018 23:15:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 967B62CE24; Thu, 13 Dec 2018 23:15:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 45A972CBD5 for ; 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14 Dec 2018 07:14:53 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 13 Dec 2018 14:56:28 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:54 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Date: Thu, 13 Dec 2018 15:14:29 -0800 Message-Id: <1544742869-19980-5-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_151516_969502_FA0243C8 X-CRM114-Status: GOOD ( 12.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Dmitriy Cherkasov , Anup Patel , Daniel Lezcano , Christoph Hellwig , Atish Patra , Rob Herring , Palmer Dabbelt , linux-riscv@lists.infradead.org, Thomas Gleixner MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, clocksource registration happens for an invalid cpu for non-smp kernels. This lead to kernel panic as cpu hotplug registration will fail for those cpus. Do not proceed if hartid is invalid. Take this opprtunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra --- drivers/clocksource/riscv_timer.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index c9e65086..c1e1260e 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -117,6 +117,11 @@ static int __init riscv_timer_init_dt(struct device_node *n) int cpuid, hartid, error; hartid = riscv_of_processor_hartid(n); + if (hartid < 0) { + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", + n, hartid); + return hartid; + } cpuid = riscv_hartid_to_cpuid(hartid); riscv_timebase_frequency(n, hartid); @@ -124,14 +129,19 @@ static int __init riscv_timer_init_dt(struct device_node *n) return 0; /* This should be called only for boot cpu */ - clocksource_register_hz(&riscv_clocksource, riscv_timebase); + error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); + if (error) { + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", + error, cpuid); + return error; + } error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", riscv_timer_starting_cpu, riscv_timer_dying_cpu); if (error) - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", + error); return error; }