From patchwork Thu Oct 21 10:45:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574691 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4430CC43217 for ; Thu, 21 Oct 2021 10:45:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 278C161205 for ; Thu, 21 Oct 2021 10:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231156AbhJUKrz (ORCPT ); Thu, 21 Oct 2021 06:47:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:57862 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230436AbhJUKru (ORCPT ); Thu, 21 Oct 2021 06:47:50 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 11AAF61251; Thu, 21 Oct 2021 10:45:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813134; bh=wk5uiUWZ32H6G8kB/T6suMV60EzFme/8IrrV+JrElTs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kMF1fy+V1MZkRQ7nxPst4CQJPaQtHZg1M5uxyYSoiZBljtCTIN2OVvfDSQScrk6jY kuO00CgcaOVJCSVSf4lApYiDJLwFPt1myshRwV1LuDrBiGaxFOndOE0Bih3vdjqFte ha9fQWlw7yQ1XE9sGztxlZr1Bh13PpQ2es/wAIesSub+W1/ej3a6dn9S1XPc9+Pah9 SJnxQjuQ7wk7/YvFT1X0m9zqJ6Ra/MWKStHg27zwDi+8eQLjC7uftVg+36VmsYshd+ 05ZlUZwhb2/6wipFBmeUFWd22oUvZO0PuWxBr/miOpbXup4t8vQbGaXbTpVE6INF6Q uHWwLtjK/IQvQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZi-002z4q-Vg; Thu, 21 Oct 2021 11:45:30 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Kishon Vijay Abraham I Subject: [PATCH v15 01/13] PCI: kirin: Reorganize the PHY logic inside the driver Date: Thu, 21 Oct 2021 11:45:08 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pcie-kirin PCIe driver contains internally a PHY interface for Kirin 960. As the next patches will add support for using an external PHY driver, reorganize the driver in a way that the PHY part will be self-contained. This could be moved to a separate PHY driver, but a change like that would mean a non-backward-compatible DT schema change. Cc: Kishon Vijay Abraham I Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 298 ++++++++++++++---------- 1 file changed, 173 insertions(+), 125 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 026fd1e42a55..b4063a3434df 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -28,26 +28,16 @@ #define to_kirin_pcie(x) dev_get_drvdata((x)->dev) -#define REF_CLK_FREQ 100000000 - /* PCIe ELBI registers */ #define SOC_PCIECTRL_CTRL0_ADDR 0x000 #define SOC_PCIECTRL_CTRL1_ADDR 0x004 -#define SOC_PCIEPHY_CTRL2_ADDR 0x008 -#define SOC_PCIEPHY_CTRL3_ADDR 0x00c #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) /* info located in APB */ #define PCIE_APP_LTSSM_ENABLE 0x01c -#define PCIE_APB_PHY_CTRL0 0x0 -#define PCIE_APB_PHY_CTRL1 0x4 #define PCIE_APB_PHY_STATUS0 0x400 #define PCIE_LINKUP_ENABLE (0x8020) #define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) -#define PIPE_CLK_STABLE (0x1 << 19) -#define PHY_REF_PAD_BIT (0x1 << 8) -#define PHY_PWR_DOWN_BIT (0x1 << 22) -#define PHY_RST_ACK_BIT (0x1 << 16) /* info located in sysctrl */ #define SCTRL_PCIE_CMOS_OFFSET 0x60 @@ -60,6 +50,29 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) +struct kirin_pcie { + struct dw_pcie *pci; + struct phy *phy; + void __iomem *apb_base; + void *phy_priv; /* Needed for Kirin 960 PHY */ +}; + +/* + * Kirin 960 PHY. Can't be split into a PHY driver without changing the + * DT schema. + */ + +#define REF_CLK_FREQ 100000000 + +/* PHY info located in APB */ +#define PCIE_APB_PHY_CTRL0 0x0 +#define PCIE_APB_PHY_CTRL1 0x4 +#define PCIE_APB_PHY_STATUS0 0x400 +#define PIPE_CLK_STABLE BIT(19) +#define PHY_REF_PAD_BIT BIT(8) +#define PHY_PWR_DOWN_BIT BIT(22) +#define PHY_RST_ACK_BIT BIT(16) + /* peri_crg ctrl */ #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 @@ -69,8 +82,6 @@ #define REF_2_PERST_MAX 25000 #define PERST_2_ACCESS_MIN 10000 #define PERST_2_ACCESS_MAX 12000 -#define LINK_WAIT_MIN 900 -#define LINK_WAIT_MAX 1000 #define PIPE_CLK_WAIT_MIN 550 #define PIPE_CLK_WAIT_MAX 600 #define TIME_CMOS_MIN 100 @@ -78,118 +89,112 @@ #define TIME_PHY_PD_MIN 10 #define TIME_PHY_PD_MAX 11 -struct kirin_pcie { - struct dw_pcie *pci; - void __iomem *apb_base; - void __iomem *phy_base; +struct hi3660_pcie_phy { + struct device *dev; + void __iomem *base; struct regmap *crgctrl; struct regmap *sysctrl; struct clk *apb_sys_clk; struct clk *apb_phy_clk; struct clk *phy_ref_clk; - struct clk *pcie_aclk; - struct clk *pcie_aux_clk; + struct clk *aclk; + struct clk *aux_clk; int gpio_id_reset; }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->apb_base + reg); -} - /* Registers in PCIePHY */ -static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie, +static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy, u32 val, u32 reg) { - writel(val, kirin_pcie->phy_base + reg); + writel(val, hi3660_pcie_phy->base + reg); } -static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) +static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy, + u32 reg) { - return readl(kirin_pcie->phy_base + reg); + return readl(hi3660_pcie_phy->base + reg); } -static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) +static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy) { - struct device *dev = &pdev->dev; + struct device *dev = phy->dev; - kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); - if (IS_ERR(kirin_pcie->phy_ref_clk)) - return PTR_ERR(kirin_pcie->phy_ref_clk); + phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); + if (IS_ERR(phy->phy_ref_clk)) + return PTR_ERR(phy->phy_ref_clk); - kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(kirin_pcie->pcie_aux_clk)) - return PTR_ERR(kirin_pcie->pcie_aux_clk); + phy->aux_clk = devm_clk_get(dev, "pcie_aux"); + if (IS_ERR(phy->aux_clk)) + return PTR_ERR(phy->aux_clk); - kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); - if (IS_ERR(kirin_pcie->apb_phy_clk)) - return PTR_ERR(kirin_pcie->apb_phy_clk); + phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); + if (IS_ERR(phy->apb_phy_clk)) + return PTR_ERR(phy->apb_phy_clk); - kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); - if (IS_ERR(kirin_pcie->apb_sys_clk)) - return PTR_ERR(kirin_pcie->apb_sys_clk); + phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); + if (IS_ERR(phy->apb_sys_clk)) + return PTR_ERR(phy->apb_sys_clk); - kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk"); - if (IS_ERR(kirin_pcie->pcie_aclk)) - return PTR_ERR(kirin_pcie->pcie_aclk); + phy->aclk = devm_clk_get(dev, "pcie_aclk"); + if (IS_ERR(phy->aclk)) + return PTR_ERR(phy->aclk); return 0; } -static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) +static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) { - kirin_pcie->apb_base = - devm_platform_ioremap_resource_byname(pdev, "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); - - kirin_pcie->phy_base = - devm_platform_ioremap_resource_byname(pdev, "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - - kirin_pcie->crgctrl = - syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); - if (IS_ERR(kirin_pcie->crgctrl)) - return PTR_ERR(kirin_pcie->crgctrl); - - kirin_pcie->sysctrl = - syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); - if (IS_ERR(kirin_pcie->sysctrl)) - return PTR_ERR(kirin_pcie->sysctrl); + struct device *dev = phy->dev; + struct platform_device *pdev; + + /* registers */ + pdev = container_of(dev, struct platform_device, dev); + + phy->base = devm_platform_ioremap_resource_byname(pdev, "phy"); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); + if (IS_ERR(phy->crgctrl)) + return PTR_ERR(phy->crgctrl); + + phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); + if (IS_ERR(phy->sysctrl)) + return PTR_ERR(phy->sysctrl); + + /* gpios */ + phy->gpio_id_reset = of_get_named_gpio(dev->of_node, + "reset-gpios", 0); + if (phy->gpio_id_reset == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (!gpio_is_valid(phy->gpio_id_reset)) { + dev_err(phy->dev, "unable to get a valid gpio pin\n"); + return -ENODEV; + } return 0; } -static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie) +static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy) { - struct device *dev = kirin_pcie->pci->dev; + struct device *dev = phy->dev; u32 reg_val; - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); + reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); reg_val &= ~PHY_REF_PAD_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); + kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0); + reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0); reg_val &= ~PHY_PWR_DOWN_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0); + kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0); usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX); - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); + reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); reg_val &= ~PHY_RST_ACK_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); + kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX); - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); + reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0); if (reg_val & PIPE_CLK_STABLE) { dev_err(dev, "PIPE clk is not stable\n"); return -EINVAL; @@ -198,105 +203,157 @@ static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie) return 0; } -static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) +static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy) { u32 val; - regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); + regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); val |= PCIE_DEBOUNCE_PARAM; val &= ~PCIE_OE_BYPASS; - regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); + regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); } -static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) +static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable) { int ret = 0; if (!enable) goto close_clk; - ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ); + ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); if (ret) return ret; - ret = clk_prepare_enable(kirin_pcie->phy_ref_clk); + ret = clk_prepare_enable(phy->phy_ref_clk); if (ret) return ret; - ret = clk_prepare_enable(kirin_pcie->apb_sys_clk); + ret = clk_prepare_enable(phy->apb_sys_clk); if (ret) goto apb_sys_fail; - ret = clk_prepare_enable(kirin_pcie->apb_phy_clk); + ret = clk_prepare_enable(phy->apb_phy_clk); if (ret) goto apb_phy_fail; - ret = clk_prepare_enable(kirin_pcie->pcie_aclk); + ret = clk_prepare_enable(phy->aclk); if (ret) goto aclk_fail; - ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk); + ret = clk_prepare_enable(phy->aux_clk); if (ret) goto aux_clk_fail; return 0; close_clk: - clk_disable_unprepare(kirin_pcie->pcie_aux_clk); + clk_disable_unprepare(phy->aux_clk); aux_clk_fail: - clk_disable_unprepare(kirin_pcie->pcie_aclk); + clk_disable_unprepare(phy->aclk); aclk_fail: - clk_disable_unprepare(kirin_pcie->apb_phy_clk); + clk_disable_unprepare(phy->apb_phy_clk); apb_phy_fail: - clk_disable_unprepare(kirin_pcie->apb_sys_clk); + clk_disable_unprepare(phy->apb_sys_clk); apb_sys_fail: - clk_disable_unprepare(kirin_pcie->phy_ref_clk); + clk_disable_unprepare(phy->phy_ref_clk); return ret; } -static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) +static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) { + struct hi3660_pcie_phy *phy = pcie->phy_priv; int ret; /* Power supply for Host */ - regmap_write(kirin_pcie->sysctrl, + regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); - kirin_pcie_oe_enable(kirin_pcie); - ret = kirin_pcie_clk_ctrl(kirin_pcie, true); + hi3660_pcie_phy_oe_enable(phy); + + ret = hi3660_pcie_phy_clk_ctrl(phy, true); if (ret) return ret; /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ - regmap_write(kirin_pcie->sysctrl, + regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); - regmap_write(kirin_pcie->crgctrl, + regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); - regmap_write(kirin_pcie->sysctrl, + regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); - ret = kirin_pcie_phy_init(kirin_pcie); + ret = hi3660_pcie_phy_start(phy); if (ret) - goto close_clk; + goto disable_clks; /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) { + if (!gpio_request(phy->gpio_id_reset, "pcie_perst")) { usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1); + ret = gpio_direction_output(phy->gpio_id_reset, 1); if (ret) - goto close_clk; + goto disable_clks; usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); - return 0; } -close_clk: - kirin_pcie_clk_ctrl(kirin_pcie, false); +disable_clks: + hi3660_pcie_phy_clk_ctrl(phy, false); return ret; } +static int hi3660_pcie_phy_init(struct platform_device *pdev, + struct kirin_pcie *pcie) +{ + struct device *dev = &pdev->dev; + struct hi3660_pcie_phy *phy; + int ret; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + pcie->phy_priv = phy; + phy->dev = dev; + + /* registers */ + pdev = container_of(dev, struct platform_device, dev); + + ret = hi3660_pcie_phy_get_clk(phy); + if (ret) + return ret; + + return hi3660_pcie_phy_get_resource(phy); +} + +/* + * The non-PHY part starts here + */ + +/* Registers in PCIeCTRL */ +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, + u32 val, u32 reg) +{ + writel(val, kirin_pcie->apb_base + reg); +} + +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) +{ + return readl(kirin_pcie->apb_base + reg); +} + +static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + kirin_pcie->apb_base = + devm_platform_ioremap_resource_byname(pdev, "apb"); + if (IS_ERR(kirin_pcie->apb_base)) + return PTR_ERR(kirin_pcie->apb_base); + + return 0; +} + static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, bool on) { @@ -444,7 +501,7 @@ static int kirin_pcie_probe(struct platform_device *pdev) pci->pp.ops = &kirin_pcie_host_ops; kirin_pcie->pci = pci; - ret = kirin_pcie_get_clk(kirin_pcie, pdev); + ret = hi3660_pcie_phy_init(pdev, kirin_pcie); if (ret) return ret; @@ -452,16 +509,7 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; - kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) { - return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) { - dev_err(dev, "unable to get a valid gpio pin\n"); - return -ENODEV; - } - - ret = kirin_pcie_power_on(kirin_pcie); + ret = hi3660_pcie_phy_power_on(kirin_pcie); if (ret) return ret; @@ -479,8 +527,8 @@ static struct platform_driver kirin_pcie_driver = { .probe = kirin_pcie_probe, .driver = { .name = "kirin-pcie", - .of_match_table = kirin_pcie_match, - .suppress_bind_attrs = true, + .of_match_table = kirin_pcie_match, + .suppress_bind_attrs = true, }, }; builtin_platform_driver(kirin_pcie_driver); From patchwork Thu Oct 21 10:45:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574677 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E255C4332F for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 518176138B for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230484AbhJUKrv (ORCPT ); Thu, 21 Oct 2021 06:47:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:57784 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230383AbhJUKrt (ORCPT ); Thu, 21 Oct 2021 06:47:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D95D16112D; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813133; bh=D/hWJuhwiXXcxdcDXCNpHmnUvvgUiKzbMRKlutA4TUk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hyfsGzqQ1/ao7I2OMbOgzWhAyNbbG78wCkJL8ydv54xYBU5dzn35s/n79C3tiels6 6iQtYLwDyvjgSbD7pecO0dPiO6aZ8MvF05ILtpcWqMszv3e334Ze6tgF1htSTHImkz wsDO4wll2e+knf/byTDYLkK2J1bF+jCDaN0T179xSug0vQKCFeflUMzMA+Bp7Xg3az JLY/LXJjL86XEVH24aOxRDnMQAZOYSkMMnS206cLrvI5qThPG8Y4YCZpunZLg4HZv4 5GE/Lljz54yivQYWiERAFBdkSGW50xBk0U9a5C9HE+tVfjazfPZRt6y681zVmlirlP 23mERLYgUMhjg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z4t-0M; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Kishon Vijay Abraham I Subject: [PATCH v15 02/13] PCI: kirin: Add support for a PHY layer Date: Thu, 21 Oct 2021 11:45:09 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pcie-kirin driver contains both PHY and generic PCI driver on it. The best would be, instead, to support a PCI PHY driver, making the driver more generic. However, it is too late to remove the Kirin 960 PHY, as a change like that would make the DT schema incompatible with past versions. So, add support for an external PHY driver without removing the existing Kirin 960 PHY from it. Cc: Kishon Vijay Abraham I Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Kishon Vijay Abraham I --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 95 +++++++++++++++++++++---- 1 file changed, 80 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index b4063a3434df..91a7c096bf8f 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -8,16 +8,18 @@ * Author: Xiaowei Song */ -#include #include +#include #include #include #include #include #include #include +#include #include #include +#include #include #include #include @@ -50,11 +52,18 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) +enum pcie_kirin_phy_type { + PCIE_KIRIN_INTERNAL_PHY, + PCIE_KIRIN_EXTERNAL_PHY +}; + struct kirin_pcie { + enum pcie_kirin_phy_type type; + struct dw_pcie *pci; struct phy *phy; void __iomem *apb_base; - void *phy_priv; /* Needed for Kirin 960 PHY */ + void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */ }; /* @@ -476,8 +485,63 @@ static const struct dw_pcie_host_ops kirin_pcie_host_ops = { .host_init = kirin_pcie_host_init, }; +static int kirin_pcie_power_on(struct platform_device *pdev, + struct kirin_pcie *kirin_pcie) +{ + struct device *dev = &pdev->dev; + int ret; + + if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { + ret = hi3660_pcie_phy_init(pdev, kirin_pcie); + if (ret) + return ret; + + return hi3660_pcie_phy_power_on(kirin_pcie); + } + + kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); + if (IS_ERR(kirin_pcie->phy)) + return PTR_ERR(kirin_pcie->phy); + + ret = phy_init(kirin_pcie->phy); + if (ret) + goto err; + + ret = phy_power_on(kirin_pcie->phy); + if (ret) + goto err; + + return 0; +err: + phy_exit(kirin_pcie->phy); + return ret; +} + +static int __exit kirin_pcie_remove(struct platform_device *pdev) +{ + struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); + + if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) + return 0; + + phy_power_off(kirin_pcie->phy); + phy_exit(kirin_pcie->phy); + + return 0; +} + +static const struct of_device_id kirin_pcie_match[] = { + { + .compatible = "hisilicon,kirin960-pcie", + .data = (void *)PCIE_KIRIN_INTERNAL_PHY + }, + {}, +}; + static int kirin_pcie_probe(struct platform_device *pdev) { + enum pcie_kirin_phy_type phy_type; + const struct of_device_id *of_id; struct device *dev = &pdev->dev; struct kirin_pcie *kirin_pcie; struct dw_pcie *pci; @@ -488,6 +552,14 @@ static int kirin_pcie_probe(struct platform_device *pdev) return -EINVAL; } + of_id = of_match_device(kirin_pcie_match, dev); + if (!of_id) { + dev_err(dev, "OF data missing\n"); + return -EINVAL; + } + + phy_type = (long)of_id->data; + kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); if (!kirin_pcie) return -ENOMEM; @@ -500,31 +572,24 @@ static int kirin_pcie_probe(struct platform_device *pdev) pci->ops = &kirin_dw_pcie_ops; pci->pp.ops = &kirin_pcie_host_ops; kirin_pcie->pci = pci; - - ret = hi3660_pcie_phy_init(pdev, kirin_pcie); - if (ret) - return ret; + kirin_pcie->type = phy_type; ret = kirin_pcie_get_resource(kirin_pcie, pdev); if (ret) return ret; - ret = hi3660_pcie_phy_power_on(kirin_pcie); - if (ret) - return ret; - platform_set_drvdata(pdev, kirin_pcie); + ret = kirin_pcie_power_on(pdev, kirin_pcie); + if (ret) + return ret; + return dw_pcie_host_init(&pci->pp); } -static const struct of_device_id kirin_pcie_match[] = { - { .compatible = "hisilicon,kirin960-pcie" }, - {}, -}; - static struct platform_driver kirin_pcie_driver = { .probe = kirin_pcie_probe, + .remove = __exit_p(kirin_pcie_remove), .driver = { .name = "kirin-pcie", .of_match_table = kirin_pcie_match, From patchwork Thu Oct 21 10:45:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574695 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71CFEC433F5 for ; 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Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 03/13] PCI: kirin: Use regmap for APB registers Date: Thu, 21 Oct 2021 11:45:10 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PHY layer need to access APB registers too, for Kirin 970. So, place them into a named regmap. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 49 +++++++++++++------------ 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 91a7c096bf8f..86c13661e02d 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -61,8 +61,8 @@ struct kirin_pcie { enum pcie_kirin_phy_type type; struct dw_pcie *pci; + struct regmap *apb; struct phy *phy; - void __iomem *apb_base; void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */ }; @@ -340,25 +340,27 @@ static int hi3660_pcie_phy_init(struct platform_device *pdev, * The non-PHY part starts here */ -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->apb_base + reg); -} +static const struct regmap_config pcie_kirin_regmap_conf = { + .name = "kirin_pcie_apb", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { - kirin_pcie->apb_base = - devm_platform_ioremap_resource_byname(pdev, "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); + struct device *dev = &pdev->dev; + void __iomem *apb_base; + + apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); + if (IS_ERR(apb_base)) + return PTR_ERR(apb_base); + + kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, + &pcie_kirin_regmap_conf); + if (IS_ERR(kirin_pcie->apb)) + return PTR_ERR(kirin_pcie->apb); return 0; } @@ -368,13 +370,13 @@ static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, { u32 val; - val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR); + regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val); if (on) val = val | PCIE_ELBI_SLV_DBI_ENABLE; else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; - kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR); + regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val); } static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, @@ -382,13 +384,13 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, { u32 val; - val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR); + regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val); if (on) val = val | PCIE_ELBI_SLV_DBI_ENABLE; else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; - kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); + regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val); } static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, @@ -448,8 +450,9 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, static int kirin_pcie_link_up(struct dw_pcie *pci) { struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); + u32 val; + regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) return 1; @@ -461,8 +464,8 @@ static int kirin_pcie_start_link(struct dw_pcie *pci) struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); /* assert LTSSM enable */ - kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT, - PCIE_APP_LTSSM_ENABLE); + regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE, + PCIE_LTSSM_ENABLE_BIT); return 0; } From patchwork Thu Oct 21 10:45:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574701 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2DA2C43217 for ; Thu, 21 Oct 2021 10:45:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C650561037 for ; Thu, 21 Oct 2021 10:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231207AbhJUKr4 (ORCPT ); Thu, 21 Oct 2021 06:47:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:58068 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230330AbhJUKry (ORCPT ); Thu, 21 Oct 2021 06:47:54 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 42D2461221; Thu, 21 Oct 2021 10:45:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813138; bh=yQHUwi5Y2/NnZxeHX2/8vkuz21cl665OqBicpY57bdg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AAZpEGpWBiuMAT/9q7MMaUvNPZuRnwY314/K3ldQxFKo1jG9G0P3lHRCdXz6yZMwc ghkrRWQmVU7buY1uYiQLpioGP4NGz3I86PTUVGmzM9MKsmrCaM2MQNir7Gok4P9cIw EY31Dsm7g2+tcx75RtvYm7LuDad5WoIqTwW/ZmsBdh6ddfrHgkJyrflvKKoa2LNAKP 48CQIlAUp5XjtqyOniD2T8DWhbQWtAd0FugUtEuiX/ZNBvhpGlJc8GRpo2xDOU2+Rt SHXnLWZE/HqMrcqXN7BvOHgDJBrSKgM4VGbvsJhHi22dJP/oRvY/XmMoaugW0H4ATB WQp/6TNofzJlg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z4z-1t; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Kishon Vijay Abraham I Subject: [PATCH v15 04/13] PCI: kirin: Add support for bridge slot DT schema Date: Thu, 21 Oct 2021 11:45:11 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On HiKey970, there's a PEX 8606 PCI bridge on its PHY with 6 lanes. Only 4 lanes are connected: lane 0 - connected to Kirin 970; lane 4 - M.2 slot; lane 5 - mini PCIe slot; lane 6 - in-board Ethernet controller. Each lane has its own PERST# gpio pin, and needs a clock request. Add support to parse a DT schema containing the above data. Cc: Kishon Vijay Abraham I Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 262 +++++++++++++++++++++--- 1 file changed, 231 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 86c13661e02d..de375795a3b8 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -52,6 +52,19 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) +/* + * Max number of connected PCI slots at an external PCI bridge + * + * This is used on HiKey 970, which has a PEX 8606 bridge with has + * 4 connected lanes (lane 0 upstream, and the other tree lanes, + * one connected to an in-board Ethernet adapter and the other two + * connected to M.2 and mini PCI slots. + * + * Each slot has a different clock source and uses a separate PERST# + * pin. + */ +#define MAX_PCI_SLOTS 3 + enum pcie_kirin_phy_type { PCIE_KIRIN_INTERNAL_PHY, PCIE_KIRIN_EXTERNAL_PHY @@ -64,6 +77,19 @@ struct kirin_pcie { struct regmap *apb; struct phy *phy; void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */ + + /* DWC PERST# */ + int gpio_id_dwc_perst; + + /* Per-slot PERST# */ + int num_slots; + int gpio_id_reset[MAX_PCI_SLOTS]; + const char *reset_names[MAX_PCI_SLOTS]; + + /* Per-slot clkreq */ + int n_gpio_clkreq; + int gpio_id_clkreq[MAX_PCI_SLOTS]; + const char *clkreq_names[MAX_PCI_SLOTS]; }; /* @@ -108,7 +134,6 @@ struct hi3660_pcie_phy { struct clk *phy_ref_clk; struct clk *aclk; struct clk *aux_clk; - int gpio_id_reset; }; /* Registers in PCIePHY */ @@ -171,16 +196,6 @@ static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) if (IS_ERR(phy->sysctrl)) return PTR_ERR(phy->sysctrl); - /* gpios */ - phy->gpio_id_reset = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (phy->gpio_id_reset == -EPROBE_DEFER) { - return -EPROBE_DEFER; - } else if (!gpio_is_valid(phy->gpio_id_reset)) { - dev_err(phy->dev, "unable to get a valid gpio pin\n"); - return -ENODEV; - } - return 0; } @@ -297,15 +312,7 @@ static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) if (ret) goto disable_clks; - /* perst assert Endpoint */ - if (!gpio_request(phy->gpio_id_reset, "pcie_perst")) { - usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(phy->gpio_id_reset, 1); - if (ret) - goto disable_clks; - usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); - return 0; - } + return 0; disable_clks: hi3660_pcie_phy_clk_ctrl(phy, false); @@ -347,11 +354,98 @@ static const struct regmap_config pcie_kirin_regmap_conf = { .reg_stride = 4, }; +static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + char name[32]; + int ret, i; + + /* This is an optional property */ + ret = of_gpio_named_count(np, "hisilicon,clken-gpios"); + if (ret < 0) + return 0; + + if (ret > MAX_PCI_SLOTS) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + + pcie->n_gpio_clkreq = ret; + + for (i = 0; i < pcie->n_gpio_clkreq; i++) { + pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, + "hisilicon,clken-gpios", i); + if (pcie->gpio_id_clkreq[i] < 0) + return pcie->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + pcie->clkreq_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!pcie->clkreq_names[i]) + return -ENOMEM; + } + + return 0; +} + +static int kirin_pcie_parse_port(struct kirin_pcie *pcie, + struct platform_device *pdev, + struct device_node *node) +{ + struct device *dev = &pdev->dev; + struct device_node *parent, *child; + int ret, slot, i; + char name[32]; + + for_each_available_child_of_node(node, parent) { + for_each_available_child_of_node(parent, child) { + i = pcie->num_slots; + + pcie->gpio_id_reset[i] = of_get_named_gpio(child, + "reset-gpios", 0); + if (pcie->gpio_id_reset[i] < 0) + continue; + + pcie->num_slots++; + if (pcie->num_slots > MAX_PCI_SLOTS) { + dev_err(dev, "Too many PCI slots!\n"); + return -EINVAL; + } + + ret = of_pci_get_devfn(child); + if (ret < 0) { + dev_err(dev, "failed to parse devfn: %d\n", ret); + goto put_node; + } + + slot = PCI_SLOT(ret); + + sprintf(name, "pcie_perst_%d", slot); + pcie->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!pcie->reset_names[i]) { + ret = -ENOMEM; + goto put_node; + } + } + } + + return 0; + +put_node: + of_node_put(child); + return ret; +} + static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *child, *node = dev->of_node; void __iomem *apb_base; + int ret; apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); if (IS_ERR(apb_base)) @@ -362,7 +456,32 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->apb)) return PTR_ERR(kirin_pcie->apb); + /* pcie internal PERST# gpio */ + kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node, + "reset-gpios", 0); + if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) { + dev_err(dev, "unable to get a valid gpio pin\n"); + return -ENODEV; + } + + ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev); + if (ret) + return ret; + + /* Parse OF children */ + for_each_available_child_of_node(node, child) { + ret = kirin_pcie_parse_port(kirin_pcie, pdev, child); + if (ret) + goto put_node; + } + return 0; + +put_node: + of_node_put(child); + return ret; } static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, @@ -419,9 +538,33 @@ static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, return PCIBIOS_SUCCESSFUL; } +static int kirin_pcie_add_bus(struct pci_bus *bus) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); + int i, ret; + + if (!kirin_pcie->num_slots) + return 0; + + /* Send PERST# to each slot */ + for (i = 0; i < kirin_pcie->num_slots; i++) { + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1); + if (ret) { + dev_err(pci->dev, "PERST# %s error: %d\n", + kirin_pcie->reset_names[i], ret); + } + } + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); + + return 0; +} + + static struct pci_ops kirin_pci_ops = { .read = kirin_pcie_rd_own_conf, .write = kirin_pcie_wr_own_conf, + .add_bus = kirin_pcie_add_bus, }; static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -477,6 +620,44 @@ static int kirin_pcie_host_init(struct pcie_port *pp) return 0; } +static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie, + struct device *dev) +{ + int ret, i; + + for (i = 0; i < kirin_pcie->num_slots; i++) { + if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) { + dev_err(dev, "unable to get a valid %s gpio\n", + kirin_pcie->reset_names[i]); + return -ENODEV; + } + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i], + kirin_pcie->reset_names[i]); + if (ret) + return ret; + } + + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) { + dev_err(dev, "unable to get a valid %s gpio\n", + kirin_pcie->clkreq_names[i]); + return -ENODEV; + } + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], + kirin_pcie->clkreq_names[i]); + if (ret) + return ret; + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } + + return 0; +} + static const struct dw_pcie_ops kirin_dw_pcie_ops = { .read_dbi = kirin_pcie_read_dbi, .write_dbi = kirin_pcie_write_dbi, @@ -499,24 +680,43 @@ static int kirin_pcie_power_on(struct platform_device *pdev, if (ret) return ret; - return hi3660_pcie_phy_power_on(kirin_pcie); + ret = hi3660_pcie_phy_power_on(kirin_pcie); + if (ret) + return ret; + } else { + kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); + if (IS_ERR(kirin_pcie->phy)) + return PTR_ERR(kirin_pcie->phy); + + ret = kirin_pcie_gpio_request(kirin_pcie, dev); + if (ret) + return ret; + + ret = phy_init(kirin_pcie->phy); + if (ret) + goto err; + + ret = phy_power_on(kirin_pcie->phy); + if (ret) + goto err; } - kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); - if (IS_ERR(kirin_pcie->phy)) - return PTR_ERR(kirin_pcie->phy); + /* perst assert Endpoint */ + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = phy_init(kirin_pcie->phy); - if (ret) - goto err; + if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) { + ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1); + if (ret) + goto err; + } - ret = phy_power_on(kirin_pcie->phy); - if (ret) - goto err; + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); return 0; err: - phy_exit(kirin_pcie->phy); + if (kirin_pcie->type != PCIE_KIRIN_INTERNAL_PHY) + phy_exit(kirin_pcie->phy); + return ret; } From patchwork Thu Oct 21 10:45:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574685 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D88C433FE for ; Thu, 21 Oct 2021 10:45:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A2896121F for ; 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Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 05/13] PCI: kirin: Give more time for PERST# reset to finish Date: Thu, 21 Oct 2021 11:45:12 +0100 Message-Id: <1aa50f736464cd6e871d05990684b35faef76767.1634812676.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Before code refactor, the PERST# signals were sent at the end of the power_on logic. Then, the PCI core would probe for the buses and add them. The new logic changed it to send PERST# signals during add_bus operation. That altered the timings. Also, HiKey 970 require a little more waiting time for the PCI bridge - which is outside the SoC - to finish the PERST# reset, and then initialize the eye diagram. So, increase the waiting time for the PERST# signals to what's required for it to also work with HiKey 970. Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index de375795a3b8..bc329673632a 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -113,7 +113,7 @@ struct kirin_pcie { #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 /* Time for delay */ -#define REF_2_PERST_MIN 20000 +#define REF_2_PERST_MIN 21000 #define REF_2_PERST_MAX 25000 #define PERST_2_ACCESS_MIN 10000 #define PERST_2_ACCESS_MAX 12000 From patchwork Thu Oct 21 10:45:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574679 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68041C433F5 for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39E4F6121E for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbhJUKru (ORCPT ); Thu, 21 Oct 2021 06:47:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:57726 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230374AbhJUKrt (ORCPT ); Thu, 21 Oct 2021 06:47:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id BEC2860E8C; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813133; bh=rqnvK2L3kPPqtUr9fmz5c9EBY5JEqrOrWtMYvqiaU0U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OpLKIVc6JLbCcoO61ei4WErVvgYHxeZXNk6KckPl1zwtJDUdbw8F7fLJBSMWs4eYW Vhs/SnbW807Q4EaoiLCWetjU6YBpEUe+SjpPiVXSzLQesZTUpEZckSfjXya0WgxmQ3 bOjC7PGInfPqjz7wDCR860XrYNt5GUJ4GhGIBCMriU6nzKcXB9Ddio7IGCM2PVzBb7 TnzZC2WiOlo2EQpS/nZHMB117urpFOUfGdQ4jpV/dAsBd5qDbn742AfgjrlxvSEWwg cF3gH+5anfcrDTzwajlQbcZ1L0Mc4qqzBvaAAIwnHKsRRHlxoChdWNBPff7WL2lq7n OHBGxXtp08p8Q== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z55-3F; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 06/13] PCI: kirin: Add Kirin 970 compatible Date: Thu, 21 Oct 2021 11:45:13 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Now that everything is in place, add a compatible for Kirin 970. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index bc329673632a..475ef57d5261 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -738,6 +738,10 @@ static const struct of_device_id kirin_pcie_match[] = { .compatible = "hisilicon,kirin960-pcie", .data = (void *)PCIE_KIRIN_INTERNAL_PHY }, + { + .compatible = "hisilicon,kirin970-pcie", + .data = (void *)PCIE_KIRIN_EXTERNAL_PHY + }, {}, }; From patchwork Thu Oct 21 10:45:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574681 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0D09C433FE for ; Thu, 21 Oct 2021 10:45:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B671D61037 for ; Thu, 21 Oct 2021 10:45:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbhJUKrv (ORCPT ); Thu, 21 Oct 2021 06:47:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:57798 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230409AbhJUKrt (ORCPT ); Thu, 21 Oct 2021 06:47:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E41F161208; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813133; bh=Le9rsnoOOiUm4zRVQqPf1pAHpDOh5WHVhQ4AmH10+fI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S0yEXYeHrbatFCAPThgBXMTRU0NnCXFOc4TFM/T9zDN3B2cAPMWFaiPvBGFccaPU3 ILyAszbfjtdVSackllLbJbcYDcD9appiW1VhuEqSyryTBg66ClBj2+4XNOLayrGg2C GnGiwW7z/aOi+k0SpH5Y1skMVumpiEwC1bCguKMeMhMvvGqPEQ72q1C4f6a8P0NQ6E 3wo9lkRYfoCGscSjURmJIncQr7Cim267aM41oHfQu/Z1mOz3PXb9JRRYnm83S+D4mP igBXkcZnKw5MraBLA6cFtt8hz+SaHbDwo7q12QyrQT10CsvIoTWc/c9NQLIfED0cV+ +RRf2rrcR/AFQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z58-3n; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 07/13] PCI: kirin: Add MODULE_* macros Date: Thu, 21 Oct 2021 11:45:14 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This driver misses the MODULE_* macros. Add them. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 475ef57d5261..b55830d2a19b 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -804,3 +804,8 @@ static struct platform_driver kirin_pcie_driver = { }, }; builtin_platform_driver(kirin_pcie_driver); + +MODULE_DEVICE_TABLE(of, kirin_pcie_match); +MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs"); +MODULE_AUTHOR("Xiaowei Song "); +MODULE_LICENSE("GPL v2"); From patchwork Thu Oct 21 10:45:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574697 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE944C433FE for ; Thu, 21 Oct 2021 10:45:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B47D060E8C for ; Thu, 21 Oct 2021 10:45:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231195AbhJUKr6 (ORCPT ); Thu, 21 Oct 2021 06:47:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:58106 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231129AbhJUKry (ORCPT ); Thu, 21 Oct 2021 06:47:54 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A978C613A3; Thu, 21 Oct 2021 10:45:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813138; bh=gRzjZR2i3+PX8QmmnpFooG4PYPyeUIKfI68izIx0rcA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=awd0UBwc4sT/qWLw4vsMner260mTCeEAuC3MVS4/ktoSKEc/EMiX8tNWQPuha4X5v kweP1lCu2o+8crHQPqGR88ldwhQ+yhLn3RRGjnxu3lzrNDz+Mdg+d8wjdCm1CT5KA/ 1JFayfSNan3M2vNRRRWjMBsBM6J0lWc9WsPkpxT5kYjSCxFJMvhYBWYen6Z6GMy7xe muC7NZp6NqG4lpn9/G98DLeqqAVEHO8vfPSB4HvqoiJIxn+G3ltXG0f5gBEmDfK7dS uBCe0bovjYozfpkH1AcZp3j4OJYoWpcNGBMuQUom8m+iMIkQNmBwxTqw6iGaCf2DLR dfOVfZ579mrBw== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5B-4W; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Alex Dewar , Andy Shevchenko , Bjorn Helgaas , Jaehoon Chung , Luca Ceresoli , Manivannan Sadhasivam , Nobuhiro Iwamatsu , Paul Walmsley , Rob Herring , Simon Xue , Srikanth Thokala , Wesley Sheng , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Xiaowei Song Subject: [PATCH v15 08/13] PCI: kirin: Allow building it as a module Date: Thu, 21 Oct 2021 11:45:15 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There's nothing preventing this driver to be loaded as a module. So, change its config from bool to tristate. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 071a1fb12beb..62ce3abf0f19 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -274,7 +274,7 @@ config PCIE_KEEMBAY_EP config PCIE_KIRIN depends on OF && (ARM64 || COMPILE_TEST) - bool "HiSilicon Kirin series SoCs PCIe controllers" + tristate "HiSilicon Kirin series SoCs PCIe controllers" depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help From patchwork Thu Oct 21 10:45:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574693 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E9B1C433FE for ; Thu, 21 Oct 2021 10:45:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3570960F9E for ; Thu, 21 Oct 2021 10:45:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231196AbhJUKr4 (ORCPT ); Thu, 21 Oct 2021 06:47:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:57890 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230422AbhJUKrv (ORCPT ); Thu, 21 Oct 2021 06:47:51 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C45B06120F; Thu, 21 Oct 2021 10:45:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813135; bh=9pMk1k6uGmU9IojtZe74/yowfnvVlZuYtg/BQ7QzHME=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SIGM+j6spFov+VGW3zCMRqBhXHOCWMC1dxD7MHCl1zaFh3Hj6PihZx0bm5V4DwY2O J05aTzTCxFVf1fbGGtxFBLhv+QrUgk/i93Hf9YFRvNajJuzLBZYklx9uvVoYbima+1 CDUZeVBp46evwMa2vNPI5BuWLpzSESUcUnPznfETDKr5+wZSiRUiMy4MtLXJen5iKU 8/UUEHQ/VB1kNrGj08FQP5dJ1xCrnuvQ1p800fx85M2nGQdJPzjveFlJA/uNJycuKm nogS8oIZl9KY2LRDKaleziF5bpGkrjFcuQRX9hvG+tcweNfhAs5BM0QdUJsdnhIVH/ Y/O3Cxr+l8tfg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5E-5A; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 09/13] PCI: kirin: Add power_off support for Kirin 960 PHY Date: Thu, 21 Oct 2021 11:45:16 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In order to prepare for module unload, add a power_off method for HiKey 960. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index b55830d2a19b..64221a204db2 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -343,6 +343,18 @@ static int hi3660_pcie_phy_init(struct platform_device *pdev, return hi3660_pcie_phy_get_resource(phy); } +static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie) +{ + struct hi3660_pcie_phy *phy = pcie->phy_priv; + + /* Drop power supply for Host */ + regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00); + + hi3660_pcie_phy_clk_ctrl(phy, false); + + return 0; +} + /* * The non-PHY part starts here */ @@ -560,7 +572,6 @@ static int kirin_pcie_add_bus(struct pci_bus *bus) return 0; } - static struct pci_ops kirin_pci_ops = { .read = kirin_pcie_rd_own_conf, .write = kirin_pcie_wr_own_conf, @@ -714,8 +725,12 @@ static int kirin_pcie_power_on(struct platform_device *pdev, return 0; err: - if (kirin_pcie->type != PCIE_KIRIN_INTERNAL_PHY) + if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { + hi3660_pcie_phy_power_off(kirin_pcie); + } else { + phy_power_off(kirin_pcie->phy); phy_exit(kirin_pcie->phy); + } return ret; } @@ -725,7 +740,7 @@ static int __exit kirin_pcie_remove(struct platform_device *pdev) struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) - return 0; + return hi3660_pcie_phy_power_off(kirin_pcie); phy_power_off(kirin_pcie->phy); phy_exit(kirin_pcie->phy); From patchwork Thu Oct 21 10:45:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574683 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65E92C433EF for ; Thu, 21 Oct 2021 10:45:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A8666121E for ; Thu, 21 Oct 2021 10:45:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230374AbhJUKrw (ORCPT ); Thu, 21 Oct 2021 06:47:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:57800 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230413AbhJUKrt (ORCPT ); Thu, 21 Oct 2021 06:47:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E16226120C; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813133; bh=afPaNM6wvpFiYxWvoOcUCgw1GJtsKqDLOtbDz3hIjU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d2LrAqWO46tVm06e0RFWXpP8U+oYLy5hn9KxQtr66RBacog0Fb+zjRV3H2D693DDf zkcFn4fdMBdKUwGGc2HgVjJHoHSdzQKgLwbT3yOxOf8AvGP6WJuizHBSBYtSf6w3Ct DdpPHxLLvhR4vrs5Rl7MGrnMJzqulaZohfhYJ6PG7N4L38lB8Z64GZtmm9PfSdKK+s ifTuG+Eg7lNSkib7E3h50c7GXKSPgdq+aEGnT2tZzCayWqZkCqmu4YtFyiglfYSHUz b6lJwD8YQ+OCsY77BphecOQcnseJQZync0587NlUMv9p7y87ItOKmynqeUjjdjzXz2 ToKRB5Ay1q8kQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5H-5v; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 10/13] PCI: kirin: Move the power-off code to a common routine Date: Thu, 21 Oct 2021 11:45:17 +0100 Message-Id: <64f6e8da3e5fff38b6c8fcb208ace46efe6555bb.1634812676.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of having two copies of the same logic, place the power-off logic on a separate function. No functional changes. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 26 ++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 64221a204db2..f4ea27b37968 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -680,6 +680,19 @@ static const struct dw_pcie_host_ops kirin_pcie_host_ops = { .host_init = kirin_pcie_host_init, }; +static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie) +{ + int i; + + if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) + return hi3660_pcie_phy_power_off(kirin_pcie); + + phy_power_off(kirin_pcie->phy); + phy_exit(kirin_pcie->phy); + + return 0; +} + static int kirin_pcie_power_on(struct platform_device *pdev, struct kirin_pcie *kirin_pcie) { @@ -725,12 +738,7 @@ static int kirin_pcie_power_on(struct platform_device *pdev, return 0; err: - if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { - hi3660_pcie_phy_power_off(kirin_pcie); - } else { - phy_power_off(kirin_pcie->phy); - phy_exit(kirin_pcie->phy); - } + kirin_pcie_power_off(kirin_pcie); return ret; } @@ -739,11 +747,7 @@ static int __exit kirin_pcie_remove(struct platform_device *pdev) { struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); - if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) - return hi3660_pcie_phy_power_off(kirin_pcie); - - phy_power_off(kirin_pcie->phy); - phy_exit(kirin_pcie->phy); + kirin_pcie_power_off(kirin_pcie); return 0; } From patchwork Thu Oct 21 10:45:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574675 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AD1C433EF for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 288856128B for ; Thu, 21 Oct 2021 10:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbhJUKru (ORCPT ); Thu, 21 Oct 2021 06:47:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:57776 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230376AbhJUKrt (ORCPT ); Thu, 21 Oct 2021 06:47:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D2B2460F9E; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813133; bh=1MK9BXA7JWARnl0O9y6KyH5YzDwUZkQB6sHYmBqTrdA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u7GLPKmUv3zdswlYOSlvmYa40RNIcOtr84teq9XxEE53NzvQf2HIipaM5mhYHqYpM Eh/i9uEuFKaCMqx+1/M8gstuWRX3yry5ho4pTubUNB3TvkB+RQocFMHloYsco0kE3J RJ9+f51wJWL0UXXwQ7L/OIg13bwwr7m1fGw8LU1kIM+hNPZ7EOUXUnA3KI9ncIh3zn G6EUtOhCUGH/HQBKRhlyN36T3rQvEy7MWFVYrvQJwQCOdpKh0vcmPWU8sMuKeN0R8C vLydU4uumpcjm93bi/ZZvjug/utCRYr26L/ApnIG9mPGLTIgClEUk1xpFSVE+TNDV8 nbI3C4yK9iacQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5K-6h; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 11/13] PCI: kirin: Disable clkreq during poweroff sequence Date: Thu, 21 Oct 2021 11:45:18 +0100 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The logic at kirin_pcie_gpio_request() enables some clkreq GPIO lines. Disable them during power-off. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index f4ea27b37968..4c3fa02b7108 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -687,6 +687,9 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie) if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) return hi3660_pcie_phy_power_off(kirin_pcie); + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) + gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1); + phy_power_off(kirin_pcie->phy); phy_exit(kirin_pcie->phy); From patchwork Thu Oct 21 10:45:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574687 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43FF5C4332F for ; Thu, 21 Oct 2021 10:45:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 295EE6121F for ; Thu, 21 Oct 2021 10:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230376AbhJUKry (ORCPT ); Thu, 21 Oct 2021 06:47:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:57856 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230316AbhJUKru (ORCPT ); Thu, 21 Oct 2021 06:47:50 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E8DE861212; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813134; bh=eLjGS50emBath6Dva8luhePYLJ4Az8GwBrWJmSsy4uk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sYRpMVtzxNPkcsOF60SFW1uOdAQ1EHGjL/Hh9spBJtxXkOQltTAynSugOPk7YVgOB uTKHVvtxH5vBZbv/G9cxew4EeXQ7aEX8qw/zRiL1p2IUpc4HehWShHz+j7CtLubBg7 YuiBp4o7K16S4CIDs/VY2ZoDi7P8uRBdXVtKIRMiUDx55UD9lNChFdA5tdkiy/xQNN tJZBlZ6+GizPKffv5ERxfUEYHjPrrkiezSXc4yBdgKnFDxAeyCZa5UCd4Zn2sFOMj+ 0niGK7alY+oIeAGEJMM3Wvv/INQ6u+tVgc9BC9ZV2YRkqi8e/EZwtDMvJbIMckntlt k5N5Stc7/i7Eg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5N-7N; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 12/13] PCI: kirin: De-init the dwc driver Date: Thu, 21 Oct 2021 11:45:19 +0100 Message-Id: <838621e1c84ebaac153ccd9c36ea5e1254c61ead.1634812676.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The logic under .remove ops is missing a call to dw_pcie_host_deinit(). Add it, in order to allow the DWC core to be properly cleaned up. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 4c3fa02b7108..fea4d717fff3 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -750,6 +750,8 @@ static int __exit kirin_pcie_remove(struct platform_device *pdev) { struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); + dw_pcie_host_deinit(&kirin_pcie->pci->pp); + kirin_pcie_power_off(kirin_pcie); return 0; From patchwork Thu Oct 21 10:45:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12574689 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C526C433EF for ; Thu, 21 Oct 2021 10:45:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1696960E8C for ; Thu, 21 Oct 2021 10:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231138AbhJUKry (ORCPT ); Thu, 21 Oct 2021 06:47:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:57860 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230372AbhJUKru (ORCPT ); Thu, 21 Oct 2021 06:47:50 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id ED86F61213; Thu, 21 Oct 2021 10:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634813134; bh=G+b584k4tQ2fwQ3W1w2eccdVGaOwa88+od2/2SHzSWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZcInEMA7hEXIKyTYrkM556DcXiVzD16UwAqKHOkSKMKgK0yCOR3buGMvLIQFjdgj1 Q7bss6AQunAN7kGKNT9Cc3WsZM+JnZsQ5rr/QZ7qZMQIQ/eRbcQY6L+UJ4renUKcSe 1UZpsGl8DBJJcDlaLF77qenoSsjo8ih5hrpcCIYCqZHGOZc8vj9gl4d06uFi8oiq3U VllcP1gE3JgIO0oD9ZQttuuINq9ryFJ+fK9U+RnMAFokNu11jLKelEpScWeYy6/7XJ ws9SwQd8Ldn9OaJ3PWuCpeMDGgeR38NUH+Xgxf1z7bCPmsOr/FgwLSJjbDMwSqfYsb KPR89UByUOqtw== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mdVZj-002z5Q-89; Thu, 21 Oct 2021 11:45:31 +0100 From: Mauro Carvalho Chehab To: Lorenzo Pieralisi Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v15 13/13] PCI: kirin: Allow removing the driver Date: Thu, 21 Oct 2021 11:45:20 +0100 Message-Id: <53b40494252444a9b830827922c4e3a301b8f863.1634812676.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Now that everything is in place at the poweroff sequence, this driver can use module_platform_driver(), which allows it to be removed. Acked-by: Xiaowei Song Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/ drivers/pci/controller/dwc/pcie-kirin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index fea4d717fff3..cdf568ea0f68 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -827,7 +827,7 @@ static struct platform_driver kirin_pcie_driver = { .suppress_bind_attrs = true, }, }; -builtin_platform_driver(kirin_pcie_driver); +module_platform_driver(kirin_pcie_driver); MODULE_DEVICE_TABLE(of, kirin_pcie_match); MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs");