From patchwork Mon Oct 25 19:13:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 12582647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBA73C433EF for ; Mon, 25 Oct 2021 19:27:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A499E6105A for ; Mon, 25 Oct 2021 19:27:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A499E6105A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csgraf.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:59630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mf5cw-0006gT-My for qemu-devel@archiver.kernel.org; Mon, 25 Oct 2021 15:27:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mf5Pu-0000fq-DT for qemu-devel@nongnu.org; Mon, 25 Oct 2021 15:13:54 -0400 Received: from mail.csgraf.de ([85.25.223.15]:48314 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mf5Ps-0000Qf-Nw for qemu-devel@nongnu.org; Mon, 25 Oct 2021 15:13:54 -0400 Received: from localhost.localdomain (dynamic-095-114-012-148.95.114.pool.telefonica.de [95.114.12.148]) by csgraf.de (Postfix) with ESMTPSA id AB55260803C7; Mon, 25 Oct 2021 21:13:50 +0200 (CEST) From: Alexander Graf To: Cameron Esfahani Subject: [PATCH] hvf: arm: Ignore cache operations on MMIO Date: Mon, 25 Oct 2021 21:13:49 +0200 Message-Id: <20211025191349.52992-1-agraf@csgraf.de> X-Mailer: git-send-email 2.30.1 (Apple Git-130) MIME-Version: 1.0 Received-SPF: pass client-ip=85.25.223.15; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kettenis@openbsd.org, qemu-devel@nongnu.org, AJ Barris , Roman Bolshakov , Paolo Bonzini , osy@github.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Apple's Hypervisor.Framework forwards cache operations as MMIO traps into user space. For MMIO however, these have no meaning: There is no cache attached to them. So let's filter SYS instructions for DATA exits out and treat them as nops. This fixes OpenBSD booting as guest. Signed-off-by: Alexander Graf Reported-by: AJ Barris Reviewed-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index bff3e0cde7..46ff4892a7 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1098,6 +1098,33 @@ static void hvf_sync_vtimer(CPUState *cpu) } } +static bool hvf_emulate_insn(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + uint32_t insn; + + /* + * We ran into an instruction that traps for data, but is not + * hardware predecoded. This should not ever happen for well + * behaved guests. Let's try to see if we can somehow rescue + * the situation. + */ + + cpu_synchronize_state(cpu); + if (cpu_memory_rw_debug(cpu, env->pc, &insn, 4, 0)) { + /* Could not read the instruction */ + return false; + } + + if ((insn & 0xffc00000) == 0xd5000000) { + /* MSR/MRS/SYS/SYSL - happens for cache ops which are nops on data */ + return true; + } + + return false; +} + int hvf_vcpu_exec(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -1156,6 +1183,11 @@ int hvf_vcpu_exec(CPUState *cpu) hvf_exit->exception.physical_address, isv, iswrite, s1ptw, len, srt); + if (!isv) { + g_assert(hvf_emulate_insn(cpu)); + advance_pc = true; + break; + } assert(isv); if (iswrite) {