From patchwork Sat Oct 30 00:18:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12594057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AC6AC433F5 for ; Sat, 30 Oct 2021 00:11:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1DCF6103E for ; Sat, 30 Oct 2021 00:11:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C1DCF6103E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19A036EA97; Sat, 30 Oct 2021 00:11:41 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFCA36EA97 for ; Sat, 30 Oct 2021 00:11:39 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10152"; a="231041031" X-IronPort-AV: E=Sophos;i="5.87,194,1631602800"; d="scan'208";a="231041031" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2021 17:11:39 -0700 X-IronPort-AV: E=Sophos;i="5.87,194,1631602800"; d="scan'208";a="487763100" Received: from josouza-mobl2.jf.intel.com (HELO josouza-mobl2.intel.com) ([10.24.14.60]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2021 17:11:39 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Cc: Karthik B S , Vandita Kulkarni , =?utf-8?b?VmlsbGUgU3lyasOk?= =?utf-8?b?bMOk?= , =?utf-8?q?Jos=C3=A9_Rober?= =?utf-8?q?to_de_Souza?= Date: Fri, 29 Oct 2021 17:18:01 -0700 Message-Id: <20211030001801.237548-1-jose.souza@intel.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/display: Exit PSR when doing async flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Changing the buffer in the middle of the scanout then entering an period of flip idleness will cause part of the previous buffer being diplayed to user when PSR is enabled. So here disabling and scheduling activation after a few milliseconds when async flip is enabled in the state. The async flip check that we had in PSR compute is not executed at every flip so it was not doing anything useful and is also being dropped here. Cc: Karthik B S Cc: Vandita Kulkarni Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9d589d471e335..d1301e2729553 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -731,12 +731,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->uapi.async_flip) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 sel fetch not enabled, async flip enabled\n"); - return false; - } - /* Wa_14010254185 Wa_14010103792 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { drm_dbg_kms(&dev_priv->drm, @@ -1780,6 +1774,11 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, if (psr->enabled && needs_to_disable) intel_psr_disable_locked(intel_dp); + if (psr->enabled && crtc_state->uapi.async_flip) { + intel_psr_exit(intel_dp); + schedule_work(&intel_dp->psr.work); + } + mutex_unlock(&psr->lock); } }