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Peter Anvin" , , , "Borislav Petkov" Subject: [PATCH v3 1/6] x86/mce/inject: Check if a bank is unpopulated before error injection Date: Thu, 4 Nov 2021 16:58:41 -0500 Message-ID: <20211104215846.254012-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e098f2d-97c2-4c17-9871-08d99fde525a X-MS-TrafficTypeDiagnostic: MN2PR12MB4373: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BJ+bJ18SusNsPK6PdOeXVosyCChq1ejaVzJm+7jfCHe16qo29DDtRqRrPDwGBBliwXmye/MWBRlfUmlB9b2oMy6JEAjEBWSonAhVL8IcdLn82FjB/1Lvac99xj0u/4Jliw18X1hT6o94S+MPqZCQ8tBzxA+JQ636NJTXRhYcPxX8ddTC+hZWLs/vvvoehbm/TM7mO3NfoEBEGXGXGW6/6jG2ARUn/ujaJqa/9htNw+T0JkqyG9vxrTrRZMn3avAbGoaz8V0kmCO8lVz1zCnkVL0we8DyYZ8jrhMm7BlWQJFLruzrl78ZompNwWIbMB5rIp/O4P+k+f99VdVffTMgn/+0MtPlg63YT4BRogMSfazdpK+NK58xhQRzaa+KTmmbsMz4lr8qWzGiflnklPz/8+OLSoX6wLg/hB7ka/TgeZc/moqaoxhUm70nAcZykZPsKBdRLR6TTLFxKvgL0kX64s3POFwsRSDTElzZUPCvRaQWBAijMG7+A7goXTSK6+S+EFDhbVugV8OxKidcADmnkgMnb+q/NSdTxk9NJYPN4tqsnQ23vv9tNtdSVC9a0eTYbuH7Pv1TRbdzpc8hNXWXS55TP4bFVPfQkXG8MkVSx+bEiHB7ngiutrW8bUIfFNpwPYEy3XSEWgvAy2vv/0xhiwI8xid+a1UPnWLaHvRj/39CkFX0G46IXxiSSzX2KUoHorPjbAyKsMI194XGoSQLfe++gVpbITaKoQXYfSootd5hsz7pprNj2jXqYACVe/BwRgjLKzTnMZv/xaWYJYdMHCKPk8cmV1QhT0lsNAIEsg452qpstYP5A/mT9+bJSj6k X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(336012)(8676002)(86362001)(26005)(426003)(8936002)(2616005)(54906003)(36860700001)(110136005)(316002)(16526019)(186003)(7696005)(47076005)(82310400003)(5660300002)(508600001)(356005)(81166007)(70586007)(6666004)(83380400001)(36756003)(70206006)(4326008)(1076003)(2906002)(15650500001)(966005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:06.0982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e098f2d-97c2-4c17-9871-08d99fde525a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4373 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The MCA_IPID register uniquely identifies a bank's type on Scalable MCA (SMCA) systems. When an MCA bank is not populated, the MCA_IPID register will read as zero and writes to it will be ignored. On a hw-type error injection (injection which writes the actual MCA registers in an attempt to cause a real MCE) check the value of this register before trying to inject the error. Do not impose any limitations on a sw injection and allow the user to test out all the decoding paths without relying on the available hardware, as its purpose is to just test the code. [ bp: Heavily massage. ] Signed-off-by: Smita Koralahalli Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211019233641.140275-2-Smita.KoralahalliChannabasappa@amd.com --- v2: simulate -> inject. Corrected according to kernel commenting style. boot_cpu_has() -> cpu_feature_enabled(). Error simulation not possible: Bank %llu unpopulated -> Cannot set IPID - bank %llu unpopulated. Used user provided IPID value on sw injection without checking underlying hardware and defined it under inj_ipid_set(). v3: Restructure and simplify the code. For !sw injection fail the injection if IPID is zero and do otherwise. --- arch/x86/kernel/cpu/mce/inject.c | 44 +++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 0bfc14041bbb..fcec99e6c5d1 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -74,7 +74,6 @@ MCE_INJECT_SET(status); MCE_INJECT_SET(misc); MCE_INJECT_SET(addr); MCE_INJECT_SET(synd); -MCE_INJECT_SET(ipid); #define MCE_INJECT_GET(reg) \ static int inj_##reg##_get(void *data, u64 *val) \ @@ -95,6 +94,20 @@ DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n"); DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n"); DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n"); DEFINE_SIMPLE_ATTRIBUTE(synd_fops, inj_synd_get, inj_synd_set, "%llx\n"); + +/* Use the user provided IPID value on a sw injection. */ +static int inj_ipid_set(void *data, u64 val) +{ + struct mce *m = (struct mce *)data; + + if (cpu_feature_enabled(X86_FEATURE_SMCA)) { + if (inj_type == SW_INJ) + m->ipid = val; + } + + return 0; +} + DEFINE_SIMPLE_ATTRIBUTE(ipid_fops, inj_ipid_get, inj_ipid_set, "%llx\n"); static void setup_inj_struct(struct mce *m) @@ -577,6 +590,35 @@ static int inj_bank_set(void *data, u64 val) } m->bank = val; + + /* + * sw-only injection allows to write arbitrary values into the MCA + * registers because it tests only the decoding paths. + */ + if (inj_type == SW_INJ) + goto inject; + + /* + * Read IPID value to determine if a bank is populated on the target + * CPU. + */ + if (cpu_feature_enabled(X86_FEATURE_SMCA)) { + u64 ipid; + + if (rdmsrl_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), + &ipid)) { + pr_err("Error reading IPID on CPU%d\n", m->extcpu); + return -EINVAL; + } + + if (!ipid) { + pr_err("Cannot inject into bank %llu - it is unpopulated\n", + val); + return -ENODEV; + } + } + +inject: do_inject(); /* Reset injection struct */ From patchwork Thu Nov 4 21:58:42 2021 Content-Type: text/plain; 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Peter Anvin" , , Subject: [PATCH v3 2/6] x86/mce/inject: Set the valid bit in MCA_STATUS before error injection Date: Thu, 4 Nov 2021 16:58:42 -0500 Message-ID: <20211104215846.254012-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9f9d5bda-7497-4bf8-9467-08d99fde5301 X-MS-TrafficTypeDiagnostic: CY4PR12MB1686: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gH3h40EcZq7mxavqXDTlEuQaQ9e57EbS+C5Noy91moIzFInHz8+UBkbeEKmre3kOkpEUXbQod6RpRy8MeXAwi0BSWMvHkZmDDQ+U2JiyMXdf6gcVB9XYncv6///9LvTNmrBCjfTtycPCHksMkndHidgaFRav7PJxfAKjVEjG+sSG2knth3n6QJrQiKxDug7NBTFjKg+7bzjfHdIPR7FPnktccZWuxFgR7MftdGlC+0T90EUN90T0Jf5rkbmeDxUGphbpqHZBz128L8mQ3jTcn8w0oRAxbCtHbAY+6L9nlxpDozES79dx7+4ggGxHqNfeK78qhOMtD/Eq2ZmaNJOdQIzaIvs4o0oREqheK5NYkBuJA3nifgnOWhKfnnACmMQfc6pUSAj1EMXtli3BNkOSwg3BdR8TXtB/wAm6MF1vhYPipJVOuP7D6rnpGELylRoItMaHsSupQxuGR306UvPxfC8SgPn2Dw/o82PnIYM5JjMgzm4cxniFxbebzbBx5I2UAOJTlwXPejcItbd5iWtNaAqQ9djvfatHbO0EeGhbLRHWxqAGYXB/mxm/zbmjiZO0GmIlleiDKi1L4hPKYqGTd3G7aDAEMIr3LNptaFEGiD2Md21kwghco1VrfGiAqMtrtb4Zd8blQ0jE2yaFDeYl2px03anyshth7MLCMI5DnH6zHbxRA94KBAUkpUfv15fgjkQTqRvhcnfTWG8mHTJl4bxALoLIF2C4wYs0Dc3m52nQWJu+LWJIf2FvEMVji99t4GL0DWWGBnbKJOvylXVys7eiawFhH6Y1hcgSBB8JSlNJT95DaKQMi6brPYVKk3A1 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(186003)(4326008)(70586007)(16526019)(8676002)(83380400001)(26005)(70206006)(54906003)(356005)(81166007)(316002)(6666004)(110136005)(966005)(36860700001)(7696005)(82310400003)(426003)(36756003)(336012)(1076003)(47076005)(508600001)(8936002)(86362001)(2616005)(5660300002)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:07.1935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f9d5bda-7497-4bf8-9467-08d99fde5301 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1686 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org MCA handlers check the valid bit in each status register (MCA_STATUS[Val]) and examine the remainder of the status register only if the valid bit is set. Set the valid bit unconditionally in the corresponding MCA_STATUS register and correct any Val=0 injections made by the user. Signed-off-by: Smita Koralahalli Link: https://lkml.kernel.org/r/20211019233641.140275-3-Smita.KoralahalliChannabasappa@amd.com --- v2: Added a warning statement instead of setting the valid bit. v3: Reverted the changes and set the valid bit conditionally. --- arch/x86/kernel/cpu/mce/inject.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index fcec99e6c5d1..5e83a1ce7ac8 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -503,6 +503,8 @@ static void do_inject(void) i_mce.tsc = rdtsc_ordered(); + i_mce.status |= MCI_STATUS_VAL; + if (i_mce.misc) i_mce.status |= MCI_STATUS_MISCV; From patchwork Thu Nov 4 21:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12603833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CED9AC433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT044.mail.protection.outlook.com (10.13.175.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 21:59:09 +0000 Received: from ethanolx50f7host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 4 Nov 2021 16:59:07 -0500 From: Smita Koralahalli To: , , CC: Tony Luck , "H . Peter Anvin" , , Subject: [PATCH v3 3/6] x86/mce/inject: Check for writes ignored in status registers Date: Thu, 4 Nov 2021 16:58:43 -0500 Message-ID: <20211104215846.254012-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e2aa9e4-1b83-4989-ca83-08d99fde5438 X-MS-TrafficTypeDiagnostic: DM6PR12MB4563: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U6jlnduAVINh/bXjicUGuuq7QkYwyrazjmIb4Dn+Vpbs97KyQ1XClAewPktrndVNtnAQ+aQoP1g5JF/HLxqMnXbSRjh08xb4ar8X3TnJaapZSubur7r/aad1lNltX/qwvmwpxoCtG6LWUi+RdBAsI3NJCV3DUMDcEaE3m/YDoVGvioMUiVOQpIw/hR9KIqix4t3tNIK/3OceKVTYuVz9tNBzmrq0Y6H1IrmAdlANYoxG5dcs+npAhSgBA+YAR7iWusiYCE2ZjlJpTePhtyYevE17ghw9YnTeSVhmziOPOul0Sna3DjidSpEznI2aFnNMRbmr1bLnG9fygoVCSCI9GxKDXe++bYSQY+/zN9/RkzyQoLoHjBmYqon58VsQD2uC7XTcYfn70UGbp4kYM50cSVlcKjp4FGUQftn2+fC4bPPmZsJR4+Y9+KRNuL8yCHeHeSWnYi0UKtq5WfbxmYtZ5VvltnsQDuqvVtWRH9ACs9Ywce+Et+ns2TGBoNUUFmCpzpsjrzBOUcL2ZxicqGWKO76z3CSzdBCAuqmeLz7g8R+yvZ9lRXyD/7wDk4s6M146m+gIa5O/lvO4Wi2TOgwObONUSrYy/X8IVzo4QR/4XecDmgE4DsemQpihJaQCWcke0Yf4bALoID5H3UL4OiM3BUSSy9kmpekTTbMhC8xMNKR/Shi0kTPFjzb8icIzEvdTR/B5ETQDP5rZ0szjslQsKC81/D+4eRTq4ICWUprz8HUuAnSp+0loL8xx+MxQEI44CBZLPihMsUmib083DfoaspQgV38Qk1casyB8nezfT1gtyHjb7oJdNaMxIMsW+tFjpI6J/n9K1kkamAmq3SNkY0bj1chBZwVFj+hA9i0GJdI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(5660300002)(356005)(186003)(8936002)(110136005)(83380400001)(426003)(81166007)(2616005)(16526019)(26005)(82310400003)(966005)(36756003)(316002)(508600001)(1076003)(54906003)(70206006)(4326008)(8676002)(36860700001)(336012)(2906002)(47076005)(6666004)(7696005)(86362001)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:09.2310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e2aa9e4-1b83-4989-ca83-08d99fde5438 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4563 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org According to Section 2.1.16.3 under HWCR[McStatusWrEn] in "PPR for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021", the status register may sometimes enforce write ignored behavior independent of the value of HWCR[McStatusWrEn] depending on the platform settings. Hence, evaluate for writes ignored for MCA_STATUS and MCA_DESTAT separately, before doing error injection. If true, return with an error code. Deferred errors on an SMCA platform use different MSR for MCA_DESTAT. Hence, evaluate MCA_DESTAT instead of MCA_STATUS on deferred errors, and do not modify the existing value in MCA_STATUS by writing and reading from it. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Smita Koralahalli Link: https://lkml.kernel.org/r/20211019233641.140275-5-Smita.KoralahalliChannabasappa@amd.com --- v2: msr_ops -> mca_msr_reg(). simulation -> injection. pr_info() -> pr_err(). Aligned on ",". v3: Removed "x86/mce: Use mca_msr_reg() in prepare_msrs()" patch and made changes on the existing MCx_{STATUS, ADDR, MISC} macros. --- arch/x86/kernel/cpu/mce/inject.c | 35 ++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 5e83a1ce7ac8..4d5689342384 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -470,9 +470,17 @@ static void toggle_nb_mca_mst_cpu(u16 nid) __func__, PCI_FUNC(F3->devfn), NBCFG); } +struct mce_err_handler { + struct mce *mce; + int err; +}; + +static struct mce_err_handler mce_err; + static void prepare_msrs(void *info) { - struct mce m = *(struct mce *)info; + struct mce_err_handler *i_mce_err = ((struct mce_err_handler *)info); + struct mce m = *i_mce_err->mce; u8 b = m.bank; wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); @@ -480,9 +488,17 @@ static void prepare_msrs(void *info) if (boot_cpu_has(X86_FEATURE_SMCA)) { if (m.inject_flags == DFR_INT_INJ) { wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + if (!m.status) + goto out; + wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); } else { wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); + rdmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); + if (!m.status) + goto out; + wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); } @@ -490,9 +506,18 @@ static void prepare_msrs(void *info) wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); } else { wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); + rdmsrl(MSR_IA32_MCx_STATUS(b), m.status); + if (!m.status) + goto out; + wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); } + +out: + pr_err("Error injection is not available\n"); + i_mce_err->err = -EINVAL; + return; } static void do_inject(void) @@ -501,6 +526,9 @@ static void do_inject(void) unsigned int cpu = i_mce.extcpu; u8 b = i_mce.bank; + mce_err.mce = &i_mce; + mce_err.err = 0; + i_mce.tsc = rdtsc_ordered(); i_mce.status |= MCI_STATUS_VAL; @@ -552,10 +580,13 @@ static void do_inject(void) i_mce.mcgstatus = mcg_status; i_mce.inject_flags = inj_type; - smp_call_function_single(cpu, prepare_msrs, &i_mce, 0); + smp_call_function_single(cpu, prepare_msrs, &mce_err, 0); toggle_hw_mce_inject(cpu, false); + if (mce_err.err) + goto err; + switch (inj_type) { case DFR_INT_INJ: smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); From patchwork Thu Nov 4 21:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12603835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 889DAC433F5 for ; Thu, 4 Nov 2021 21:59:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75B2861266 for ; Thu, 4 Nov 2021 21:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232273AbhKDWBw (ORCPT ); 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Thu, 4 Nov 2021 16:59:08 -0500 From: Smita Koralahalli To: , , CC: Tony Luck , "H . Peter Anvin" , , Subject: [PATCH v3 4/6] x86/mce/inject: Simplify evaluation of writes ignored in status registers Date: Thu, 4 Nov 2021 16:58:44 -0500 Message-ID: <20211104215846.254012-5-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6f0a5088-3d9c-4f02-d695-08d99fde54c7 X-MS-TrafficTypeDiagnostic: BL0PR12MB4948: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PkSjU2Tu5wPddNePxgi0iatqi+Yg6tVp2JaGCV/OW2VSyeEkhyt8w7ZZWkXzlFs8KzDr4LP7byybWbTMMay0rNcjjfdTAHLtVOoQBfN2ZyWeFky8A2JyNVo3YFxhJ4s/9Oja1XiuUAkK8+bNnnq7E+IreBYr6LFypRTOaZ7GKDsKY+JShKzucDyHZWYGYdNaf+nu5rUUa+gRBWyEdXlg7TLpsZ6XWF7F+AJZ4SgBZggp8Gh2vrDVF0sginvmRieWBN2/AyuYJjNm27kaXJqrbbby//pTuk9C66PscUnnuLr0Q6Jk8yIu9AXR2VxKRmhrgDqXS/Dl3Y7K6kFrCVNMiail0a3yL7FKtdGi3CK6oUVEbYWRd7tMDgmPD7GWH76NpMpgy44itMvGJAgeNZ5Ll2P9w48xRquyFqAhbP0JVzG2oRB5ZT3LJaDYd0U38hKzQZpOjGz4y3zJkT9jgIWFuV/TfMUmAphJJ5zDY/3TpOE+CFe7M78EiYZv+JsrGFoePt3S22Mc1eZmwUsstK4mD3EmTkDywfddbfb/Y/5biz+cfbj41b5+IzVeRQNhuVH5zks2ymozWrPbXJ5IpSwAVaI6lhCTolPpwJ/qe0bBHAwax650S0Q1BNcHMWIdz0zEDSckO/lEQSDtBUrrAN4o9xCqazYqdYjTn/ifGb3XYxepeB2saK5H49RvCasWkKr4wfRyQDu6l5UnAVsYcs+ugYfXXCOJir3+XxXppX9uKtY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(316002)(36860700001)(336012)(26005)(426003)(54906003)(8936002)(110136005)(186003)(2616005)(16526019)(36756003)(2906002)(47076005)(82310400003)(4326008)(1076003)(7696005)(81166007)(83380400001)(70206006)(70586007)(6666004)(5660300002)(86362001)(8676002)(356005)(508600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:10.1695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f0a5088-3d9c-4f02-d695-08d99fde54c7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4948 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Clean up code in prepare_msrs() and avoid reading the status variable and checking for writes ignored each time for SMCA, legacy and deferred case. Signed-off-by: Smita Koralahalli --- arch/x86/kernel/cpu/mce/inject.c | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 4d5689342384..8772d8820994 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -483,41 +483,34 @@ static void prepare_msrs(void *info) struct mce m = *i_mce_err->mce; u8 b = m.bank; + u32 status_reg = MSR_IA32_MCx_STATUS(b); + wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); if (boot_cpu_has(X86_FEATURE_SMCA)) { if (m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - if (!m.status) - goto out; - + status_reg = MSR_AMD64_SMCA_MCx_DESTAT(b); wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); } else { - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - rdmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - if (!m.status) - goto out; - + status_reg = MSR_AMD64_SMCA_MCx_STATUS(b); wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); } wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); } else { - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); - rdmsrl(MSR_IA32_MCx_STATUS(b), m.status); - if (!m.status) - goto out; - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); } -out: - pr_err("Error injection is not available\n"); - i_mce_err->err = -EINVAL; - return; + wrmsrl(status_reg, m.status); + rdmsrl(status_reg, m.status); + + if (!m.status) { + pr_err("Error injection is not available\n"); + i_mce_err->err = -EINVAL; + return; + } } static void do_inject(void) From patchwork Thu Nov 4 21:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12603837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37FF2C433EF for ; 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Peter Anvin" , , Subject: [PATCH v3 5/6] x86/mce/inject: Restructure prepare_msrs() Date: Thu, 4 Nov 2021 16:58:45 -0500 Message-ID: <20211104215846.254012-6-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef007fec-e16b-4252-fb9e-08d99fde55f3 X-MS-TrafficTypeDiagnostic: MW3PR12MB4378: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:551; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TjVd8ZxDTWCtXeOG6gVOhO7LLqai54lmuyfJH097jb4zNuBYT9GwP/j2FGfbmYjm3WHg5JyWM9D/1rDBh/9I9QtLhKnYWAyftOZySSwxF2DnNQ75H9CO4VO4rUBn9cXD1q4BGHPq+V9bI8nIBxLnh53kIy+SBGpKR2GRtj/1Pw8LnAs9dCLsjWAEiAI9xnT2bpNHQ97B9xO7TRRdQz4kCQ2WEv2agogrPb7uI42VGEC/r0xIenN5IMyMeTUP7h/d99St4ILBs3vzMK+a1mQ+XIh9Vxet5aiDAk9V6p6gm+XM1MBAWQ5DWEmE3l12OvEvYwmnQrwIuClOa4Vu5/k0Wzxs/WafSrcWWq9leU5mshjeovhqPPE032rkNl0LqnuKByAwtigHUNU7PkENVv9mbomPiURE7fwFQPHigSq3w57/vqFLefsOD13gOGdyKNJsgoYi9H460C9Qei0b52MKG4U91br9NPOIjeTaOESMA55Ko9QT+HO4ZWnoI//kZzAjqFpVDhZsEdXnFO7EjiZyp6qoJSdTPq1Yt1zH3waHshQ8ne/Zhxu1412gPXiwVwHS8qVOBwexSr02K5P/ArjLQGwWH5sRv7MHY+81lndPHH5PFgM8vb6uHOLDP84WKWm+WxsYE5Ex1+FtkmRvNaCau6VhvOc4aTppvKdSIzBJBwG1HYhECu+uMOgk+UDCOflT15glZUr5HQrMQYFXCUtXOeyQMaHndoSzYZD75nJB40s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(8676002)(508600001)(336012)(110136005)(1076003)(4326008)(316002)(83380400001)(16526019)(36860700001)(36756003)(47076005)(186003)(70206006)(81166007)(26005)(8936002)(6666004)(70586007)(82310400003)(5660300002)(356005)(2616005)(2906002)(7696005)(86362001)(426003)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:12.1326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef007fec-e16b-4252-fb9e-08d99fde55f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4378 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Rearrange the calls and write to registers MCx_{ADDR, MISC, SYND} and MCG_STATUS so that they are only done if error injection is available. Signed-off-by: Smita Koralahalli --- arch/x86/kernel/cpu/mce/inject.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 8772d8820994..d4e6d753018f 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -484,23 +484,19 @@ static void prepare_msrs(void *info) u8 b = m.bank; u32 status_reg = MSR_IA32_MCx_STATUS(b); - - wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); + u32 addr_reg = MSR_IA32_MCx_ADDR(b); + u32 misc_reg = MSR_IA32_MCx_MISC(b); if (boot_cpu_has(X86_FEATURE_SMCA)) { if (m.inject_flags == DFR_INT_INJ) { status_reg = MSR_AMD64_SMCA_MCx_DESTAT(b); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + addr_reg = MSR_AMD64_SMCA_MCx_DEADDR(b); } else { status_reg = MSR_AMD64_SMCA_MCx_STATUS(b); - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); + addr_reg = MSR_AMD64_SMCA_MCx_ADDR(b); } - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); - wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); - } else { - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); + misc_reg = MSR_AMD64_SMCA_MCx_MISC(b); } wrmsrl(status_reg, m.status); @@ -511,6 +507,13 @@ static void prepare_msrs(void *info) i_mce_err->err = -EINVAL; return; } + + wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); + wrmsrl(addr_reg, m.addr); + wrmsrl(misc_reg, m.misc); + + if (boot_cpu_has(X86_FEATURE_SMCA)) + wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); } static void do_inject(void) From patchwork Thu Nov 4 21:58:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12603839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA2FC433F5 for ; Thu, 4 Nov 2021 21:59:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B85C66127A for ; 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Thu, 4 Nov 2021 16:59:12 -0500 From: Smita Koralahalli To: , , CC: Tony Luck , "H . Peter Anvin" , , Subject: [PATCH v3 6/6] x86/mce/mce-inject: Return error code to userspace from mce-inject module Date: Thu, 4 Nov 2021 16:58:46 -0500 Message-ID: <20211104215846.254012-7-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40f66d58-da61-47f6-05be-08d99fde573d X-MS-TrafficTypeDiagnostic: DM5PR12MB1771: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2399; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VljK5NVenoGnlFLQP2nV9v58qIOOIdlGyoK/1QGz2tLuXdDlhMxYAA/h0P/8Tf1MYrYEZETdaTwp/FIrdcIyunVTRGpI0EMj7XRfG5gm3o0PIbwKZCZYsCynKQT4KAxxvNVLswsUCMFSrCvFbXlBY4oO5zcGJzsx8ehdhRgl0r1eWeD9hGcWvZ8+5eNgDhOH3ySq3XBa1x5nrdJ5bc6eW3UivRRqZSDpYv8L2Bl24RVRGDzgKqreARJ+zonvDrv1v9MJe5EYlPSpEZ8AvuulNAKBOgjs/GhSnTA92NPnP7e90vLGGSe4g8Khprr8FneUIgyFFwJfFTVzN1X/XFduCWRQRo0OffqDGd+k8DpHqjM5BxtUA21OemwCxcDPUlrEgnYWzFwEmZWSMdJQcELpS7zhuCXj6WsO744WpyAILfnV/4wI7rS1NGSYpk8aEzzb6NLnpHGsYawlCqTAEz7CQvjE6PTnb/XYgtnMS3lTHQ0UdLPlI2m+Rvlek8d7wOxCMD2opIsjdQIMikLB9Eo19UGH0ylmCg+WFdkuRWPFQGYImnhEE44BYZ5azlIHnQfWkAC1IcYroh1rgE+nG/piYN2Q4m/cdWXxc778Kp93rJCBeuJc0Isdh1QhPdZKgLsPmTeT/paljy5oLAqPc55gG1jR8HT5QW+hqussz2KEo6NXZT1OpHkh8wsH8r9AwR27L+E6EavmSkQMmqZxD9YJKZgNyPHJsRLiZ67OLanZ2cYJ2302dPvkkeqXOklCTvDrE92ZqZnVIfeqdLYMK93bjJN23URzzDyg9pfWK8c1pr0RduSEk/P+8D0TH3ttQmb3 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(36756003)(2616005)(8936002)(54906003)(110136005)(36860700001)(5660300002)(316002)(82310400003)(16526019)(47076005)(86362001)(336012)(83380400001)(1076003)(186003)(6666004)(81166007)(426003)(70586007)(8676002)(508600001)(966005)(26005)(356005)(4326008)(70206006)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 21:59:14.2989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40f66d58-da61-47f6-05be-08d99fde573d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1771 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Currently, the mce-inject module fails silently and user must look for kernel logs to determine if the injection has succeeded. Save time for the user and return error code from the module with appropriate error statements if error injection fails. Signed-off-by: Smita Koralahalli Link: https://lkml.kernel.org/r/20211019233641.140275-6-Smita.KoralahalliChannabasappa@amd.com --- v2: Added pr_err() along with error code. v3: Rephrased the statement: No online CPUs available for error injection -> Chosen CPU is not online. --- arch/x86/kernel/cpu/mce/inject.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index d4e6d753018f..09f46d213cf5 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -569,8 +569,11 @@ static void do_inject(void) } cpus_read_lock(); - if (!cpu_online(cpu)) + if (!cpu_online(cpu)) { + pr_err("Chosen CPU is not online\n"); + mce_err.err = -ENODEV; goto err; + } toggle_hw_mce_inject(cpu, true); @@ -653,7 +656,7 @@ static int inj_bank_set(void *data, u64 val) /* Reset injection struct */ setup_inj_struct(&i_mce); - return 0; + return mce_err.err; } MCE_INJECT_GET(bank);