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There will be a single flash_info entry when flash IDs collide, and the differentiation between the flash types will be made at runtime if possible. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 7 +++++-- drivers/mtd/spi-nor/sysfs.c | 2 +- include/linux/mtd/spi-nor.h | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ea26f27a3229..3d97c189c332 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3132,7 +3132,7 @@ static void spi_nor_debugfs_init(struct spi_nor *nor, { struct mtd_info *mtd = &nor->mtd; - mtd->dbg.partname = info->name; + mtd->dbg.partname = nor->name; mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN", info->id_len, info->id); } @@ -3271,7 +3271,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, spi_nor_set_mtd_info(nor); - dev_info(dev, "%s (%lld Kbytes)\n", info->name, + if (!nor->name) + nor->name = info->name; + + dev_info(dev, "%s (%lld Kbytes)\n", nor->name, (long long)mtd->size >> 10); dev_dbg(dev, diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c index 9aec9d8a98ad..017119768f32 100644 --- a/drivers/mtd/spi-nor/sysfs.c +++ b/drivers/mtd/spi-nor/sysfs.c @@ -25,7 +25,7 @@ static ssize_t partname_show(struct device *dev, struct spi_mem *spimem = spi_get_drvdata(spi); struct spi_nor *nor = spi_mem_get_drvdata(spimem); - return sysfs_emit(buf, "%s\n", nor->info->name); + return sysfs_emit(buf, "%s\n", nor->name); } static DEVICE_ATTR_RO(partname); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fc90fce26e33..be7ebaf092fe 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -369,6 +369,7 @@ struct spi_nor_flash_parameter; * @bouncebuf: bounce buffer used when the buffer passed by the MTD * layer is not DMA-able * @bouncebuf_size: size of the bounce buffer + * @name: used to point to correct name in case of ID collisions. * @info: SPI NOR part JEDEC MFR ID and other info * @manufacturer: SPI NOR manufacturer * @addr_width: number of address bytes @@ -398,6 +399,7 @@ struct spi_nor { struct spi_mem *spimem; u8 *bouncebuf; size_t bouncebuf_size; + const char *name; const struct flash_info *info; const struct spi_nor_manufacturer *manufacturer; u8 addr_width; From patchwork Sat Nov 6 11:36:53 2021 Content-Type: text/plain; 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d="scan'208";a="150948757" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2021 04:37:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sat, 6 Nov 2021 04:37:13 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sat, 6 Nov 2021 04:37:08 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , , , , , , , Tudor Ambarus Subject: [PATCH v3 2/6] mtd: spi-nor: macronix: Handle ID collision b/w MX25L3233F and MX25L3205D Date: Sat, 6 Nov 2021 13:36:53 +0200 Message-ID: <20211106113657.172690-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211106113657.172690-1-tudor.ambarus@microchip.com> References: <20211106113657.172690-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211106_094701_191420_FE324C31 X-CRM114-Status: GOOD ( 13.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Macronix has a bad habbit of reusing flash IDs. While MX25L3233F supports RDSFDP opcode, MX25L3205D does not support it and does not recommend issuing opcodes that are not supported ("It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode."). We tested the RDSFDP on the MX25L3205D and the conclusion is that the flash didn't reply anything. Given that it is unlikely that RDSFDP will cause any problems for the old MX25L3205D, differentiate between the two flashes by parsing SFDP. Tested MX25L3233F. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4 0xeb, for erases SPINOR_OP_BE_4K 0x20, and for writes SPINOR_OP_PP 0x02. Signed-off-by: Tudor Ambarus Acked-by: Pratyush Yadav --- # cat /sys/devices/platform/ahb/ahb:apb/f0020000.spi/spi_master/spi1/spi1.0/spi-nor/jedec_id c22016 # cat /sys/devices/platform/ahb/ahb:apb/f0020000.spi/spi_master/spi1/spi1.0/spi-nor/manufacturer macronix # cat /sys/devices/platform/ahb/ahb:apb/f0020000.spi/spi_master/spi1/spi1.0/spi-nor/partname mx25l3233f # cat /sys/devices/platform/ahb/ahb:apb/f0020000.spi/spi_master/spi1/spi1.0/spi-nor/sfdp > mx25l3233f-sfdp # xxd -p mx25l3233f-sfdp 53464450000101ff00000109300000ffc2000104600000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520f1ffffffff0144eb086b 083b04bbeeffffffffff00ffffff00ff0c200f5210d800ffffffffffffff ffffffffffff003650269cf97764fecfffffffffffff # sha1sum mx25l3233f-sfdp 1b6e0f75b4a6d08d570082992455affa72b2dc81 mx25l3233f-sfdp drivers/mtd/spi-nor/macronix.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index ffd702ec8f50..58b6cd9b194c 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,24 @@ #include "core.h" +static int mx25l3205d_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + /* + * Macronix has a bad habit of reusing flash IDs: MX25L3233F collides + * with MX25L3205D. MX25L3233F defines SFDP tables, while the older + * variant does not. + */ + nor->name = "mx25l3233f"; + + return 0; +} + +static const struct spi_nor_fixups mx25l3205d_fixups = { + .post_bfpt = mx25l3205d_post_bfpt_fixups, +}; + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -39,7 +57,10 @@ static const struct flash_info macronix_parts[] = { { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, + { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SPI_NOR_PARSE_SFDP | + SECT_4K) + /* ID collision with mx25l3233f. */ + .fixups = &mx25l3205d_fixups }, { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, From patchwork Sat Nov 6 11:36:54 2021 Content-Type: text/plain; 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d="scan'208";a="150948760" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2021 04:37:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sat, 6 Nov 2021 04:37:17 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sat, 6 Nov 2021 04:37:13 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , , , , , , , Tudor Ambarus Subject: [PATCH v3 3/6] mtd: spi-nor: macronix: Handle ID collision b/w MX25L12805D and MX25L12835F Date: Sat, 6 Nov 2021 13:36:54 +0200 Message-ID: <20211106113657.172690-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211106113657.172690-1-tudor.ambarus@microchip.com> References: <20211106113657.172690-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211106_094744_197452_6304F9C2 X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MX25L12835F define SFDP, while MX25L12805D does not. Signed-off-by: Tudor Ambarus Tested-by: Heiko Thiery Acked-by: Pratyush Yadav --- # cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0 .0/spi-nor/sfdp | xxd -p 53464450000101ff00000109300000ffc2000104600000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520f1ffffffff0744eb086b 083b04bbfeffffffffff00ffffff44eb0c200f5210d800ffffffffffffff ffffffffffff003600279df9c06485cbffffffffffff drivers/mtd/spi-nor/macronix.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 58b6cd9b194c..ac3b6ddb5c8d 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -26,6 +26,24 @@ static const struct spi_nor_fixups mx25l3205d_fixups = { .post_bfpt = mx25l3205d_post_bfpt_fixups, }; +static int mx25l12805d_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + /* + * Macronix has a bad habit of reusing flash IDs: MX25L12835F collides + * with MX25L12805D. MX25L12835F defines SFDP tables, while the older + * variant does not. + */ + nor->name = "mx25l12835f"; + + return 0; +} + +static const struct spi_nor_fixups mx25l12805d_fixups = { + .post_bfpt = mx25l12805d_post_bfpt_fixups, +}; + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -70,8 +88,10 @@ static const struct flash_info macronix_parts[] = { { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K | - SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SPI_NOR_PARSE_SFDP | + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) + /* ID collision with mx25l12835f. */ + .fixups = &mx25l12805d_fixups }, { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, { "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | From patchwork Sat Nov 6 11:36:55 2021 Content-Type: text/plain; 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d="scan'208";a="150948765" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2021 04:37:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sat, 6 Nov 2021 04:37:22 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sat, 6 Nov 2021 04:37:18 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , , , , , , , Tudor Ambarus Subject: [PATCH v3 4/6] mtd: spi-nor: Introduce Manufacturer ID collisions driver Date: Sat, 6 Nov 2021 13:36:55 +0200 Message-ID: <20211106113657.172690-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211106113657.172690-1-tudor.ambarus@microchip.com> References: <20211106113657.172690-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211106_094724_249707_538056CF X-CRM114-Status: GOOD ( 21.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some manufacturers completely ignore the manufacturer's identification code standard (JEP106) and do not define the manufacturer ID continuation scheme. This will result in manufacturer ID collisions. An an example, JEP106BA requires Boya that it's manufacturer ID to be preceded by 8 continuation codes. Boya's identification code must be: 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x68. But Boya ignores the continuation scheme and its ID collides with the manufacturer defined in bank one: Convex Computer. Introduce the manuf-id-collisions driver in order to address ID collisions between manufacturers. flash_info entries will be added in a first come, first served manner. Differentiation between flashes will be done at runtime if possible. Where runtime differentiation is not possible, new compatibles will be introduced, but this will be done as a last resort. Every new flash addition that define the SFDP tables, should dump its SFDP tables in the patch's comment section below the --- line, so that we can reference it in case of collisions. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/manuf-id-collisions.c | 31 +++++++++++++++++++++++ drivers/mtd/spi-nor/sysfs.c | 2 +- include/linux/mtd/spi-nor.h | 6 ++++- 6 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 drivers/mtd/spi-nor/manuf-id-collisions.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 6b904e439372..48763d10daad 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o +spi-nor-objs += manuf-id-collisions.o spi-nor-objs += atmel.o spi-nor-objs += catalyst.o spi-nor-objs += eon.o diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3d97c189c332..908fa16fd8f9 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1829,6 +1829,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) } static const struct spi_nor_manufacturer *manufacturers[] = { + &spi_nor_manuf_id_collisions, &spi_nor_atmel, &spi_nor_catalyst, &spi_nor_eon, @@ -3273,6 +3274,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, if (!nor->name) nor->name = info->name; + if (!nor->manufacturer_name) + nor->manufacturer_name = nor->manufacturer->name; dev_info(dev, "%s (%lld Kbytes)\n", nor->name, (long long)mtd->size >> 10); diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 9dd8ada65f0c..86545b6435f2 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -500,6 +500,7 @@ struct sfdp { }; /* Manufacturer drivers. */ +extern const struct spi_nor_manufacturer spi_nor_manuf_id_collisions; extern const struct spi_nor_manufacturer spi_nor_atmel; extern const struct spi_nor_manufacturer spi_nor_catalyst; extern const struct spi_nor_manufacturer spi_nor_eon; diff --git a/drivers/mtd/spi-nor/manuf-id-collisions.c b/drivers/mtd/spi-nor/manuf-id-collisions.c new file mode 100644 index 000000000000..4dcdf98c3eec --- /dev/null +++ b/drivers/mtd/spi-nor/manuf-id-collisions.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Used to handle collisions between manufacturers, where manufacturers are + * ignorant enough to not implement the ID continuation scheme described in the + * JEP106 JEDEC standard. + */ + +#include +#include "core.h" + +static void boya_late_init(struct spi_nor *nor) +{ + nor->manufacturer_name = "boya"; +} + +static const struct spi_nor_fixups boya_fixups = { + .late_init = boya_late_init, +}; + +static const struct flash_info id_collision_parts[] = { + /* Boya */ + { "by25q128as", INFO(0x684018, 0, 64 * 1024, 256, SPI_NOR_SKIP_SFDP | + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + .fixups = &boya_fixups }, +}; + +const struct spi_nor_manufacturer spi_nor_manuf_id_collisions = { + .parts = id_collision_parts, + .nparts = ARRAY_SIZE(id_collision_parts), +}; diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c index 017119768f32..fa0cf1a96797 100644 --- a/drivers/mtd/spi-nor/sysfs.c +++ b/drivers/mtd/spi-nor/sysfs.c @@ -14,7 +14,7 @@ static ssize_t manufacturer_show(struct device *dev, struct spi_mem *spimem = spi_get_drvdata(spi); struct spi_nor *nor = spi_mem_get_drvdata(spimem); - return sysfs_emit(buf, "%s\n", nor->manufacturer->name); + return sysfs_emit(buf, "%s\n", nor->manufacturer_name); } static DEVICE_ATTR_RO(manufacturer); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index be7ebaf092fe..a12f3a3d80f0 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -369,7 +369,10 @@ struct spi_nor_flash_parameter; * @bouncebuf: bounce buffer used when the buffer passed by the MTD * layer is not DMA-able * @bouncebuf_size: size of the bounce buffer - * @name: used to point to correct name in case of ID collisions. + * @name: used to point to correct flash name in case of ID + * collisions. + * @manufacturer_name: used to point to correct manufacturer name in case of + * ID collisions. * @info: SPI NOR part JEDEC MFR ID and other info * @manufacturer: SPI NOR manufacturer * @addr_width: number of address bytes @@ -400,6 +403,7 @@ struct spi_nor { u8 *bouncebuf; size_t bouncebuf_size; const char *name; + const char *manufacturer_name; const struct flash_info *info; const struct spi_nor_manufacturer *manufacturer; u8 addr_width; From patchwork Sat Nov 6 11:36:56 2021 Content-Type: text/plain; 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d="scan'208";a="150948769" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2021 04:37:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sat, 6 Nov 2021 04:37:27 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sat, 6 Nov 2021 04:37:22 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , , , , , , , Tudor Ambarus Subject: [PATCH v3 5/6] mtd: spi-nor: manuf-id-collisions: Add support for xt25f128b Date: Sat, 6 Nov 2021 13:36:56 +0200 Message-ID: <20211106113657.172690-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211106113657.172690-1-tudor.ambarus@microchip.com> References: <20211106113657.172690-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211106_094713_189710_0AD99518 X-CRM114-Status: UNSURE ( 9.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Flash does not support continuation codes and may collide with a flash of other manufacturer, Intersil being an example. Signed-off-by: Tudor Ambarus --- 0000000 4653 5044 0100 ff01 0000 0901 0030 ff00 0000010 000b 0301 0060 ff00 ffff ffff ffff ffff 0000020 ffff ffff ffff ffff ffff ffff ffff ffff 0000030 20e5 fff1 ffff 07ff eb44 6b08 3b08 bb42 0000040 ffee ffff ffff ff00 ffff ff00 200c 520f 0000050 d810 ff00 ffff ffff ffff ffff ffff ffff 0000060 3600 2700 f99f 6477 e8d9 ffff drivers/mtd/spi-nor/manuf-id-collisions.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mtd/spi-nor/manuf-id-collisions.c b/drivers/mtd/spi-nor/manuf-id-collisions.c index 4dcdf98c3eec..7827cfc584df 100644 --- a/drivers/mtd/spi-nor/manuf-id-collisions.c +++ b/drivers/mtd/spi-nor/manuf-id-collisions.c @@ -17,12 +17,25 @@ static const struct spi_nor_fixups boya_fixups = { .late_init = boya_late_init, }; +static void xtx_late_init(struct spi_nor *nor) +{ + nor->manufacturer_name = "xtx"; +} + +static const struct spi_nor_fixups xtx_fixups = { + .late_init = xtx_late_init, +}; + static const struct flash_info id_collision_parts[] = { /* Boya */ { "by25q128as", INFO(0x684018, 0, 64 * 1024, 256, SPI_NOR_SKIP_SFDP | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) .fixups = &boya_fixups }, + + /* XTX (XTX Technology Limited) */ + { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256, SPI_NOR_PARSE_SFDP) + .fixups = &xtx_fixups }, }; const struct spi_nor_manufacturer spi_nor_manuf_id_collisions = { From patchwork Sat Nov 6 11:36:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12606357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18052C433F5 for ; Sat, 6 Nov 2021 17:20:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB33061037 for ; Sat, 6 Nov 2021 17:20:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CB33061037 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; 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d="scan'208";a="142416176" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2021 04:37:33 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sat, 6 Nov 2021 04:37:32 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sat, 6 Nov 2021 04:37:27 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , , , , , , , Tudor Ambarus Subject: [PATCH v3 6/6] mtd: spi-nor: manuf-id-collisions: Add support for xm25qh64c Date: Sat, 6 Nov 2021 13:36:57 +0200 Message-ID: <20211106113657.172690-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211106113657.172690-1-tudor.ambarus@microchip.com> References: <20211106113657.172690-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211106_094640_923319_C3B3F026 X-CRM114-Status: UNSURE ( 9.44 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Do not apply without: # xxd -p /path/to/sfdp # sha1sum /path/to/sfdp # cat /path/to/jedec_id # cat /path/to/partname # cat /path/to/manufacturer Flash ignores the manufacturer continuation codes and is likely to collide with other manufacturers flashes. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/manuf-id-collisions.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mtd/spi-nor/manuf-id-collisions.c b/drivers/mtd/spi-nor/manuf-id-collisions.c index 7827cfc584df..0d0989dd25be 100644 --- a/drivers/mtd/spi-nor/manuf-id-collisions.c +++ b/drivers/mtd/spi-nor/manuf-id-collisions.c @@ -17,6 +17,15 @@ static const struct spi_nor_fixups boya_fixups = { .late_init = boya_late_init, }; +static void xmc_late_init(struct spi_nor *nor) +{ + nor->manufacturer_name = "xmc"; +} + +static const struct spi_nor_fixups xmc_fixups = { + .late_init = xmc_late_init, +}; + static void xtx_late_init(struct spi_nor *nor) { nor->manufacturer_name = "xtx"; @@ -33,6 +42,10 @@ static const struct flash_info id_collision_parts[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) .fixups = &boya_fixups }, + /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ + { "xm25qh64c", INFO(0x204017, 0, 64 * 1024, 128, SPI_NOR_PARSE_SFDP) + .fixups = &xmc_fixups }, + /* XTX (XTX Technology Limited) */ { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256, SPI_NOR_PARSE_SFDP) .fixups = &xtx_fixups },