From patchwork Wed Nov 10 07:33:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12611503 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16EB5C433F5 for ; Wed, 10 Nov 2021 07:33:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA780611C9 for ; Wed, 10 Nov 2021 07:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229791AbhKJHgo (ORCPT ); Wed, 10 Nov 2021 02:36:44 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:55340 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbhKJHgo (ORCPT ); Wed, 10 Nov 2021 02:36:44 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7Xpmd126035; Wed, 10 Nov 2021 01:33:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636529631; bh=MEBUaleoK0z/qGjLb6abG3y1/ihAKFWw3z1FEVJfRDg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hPKhOSlgHD7vPj3UFJ8dPf0riRArPwQnrRwpgLnTNjt8N9kFtLaNYgFsNBvd8gkF5 sgF3+d7i7iUSu4JsBLOAwWWt625pNeWQnsAROl37lemSbHmBMruOBpVveLLYRWqZJZ Nf8VIHD4dLMYCA9mRs+9hPZLjZ+mqw8SYEHYXxCA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AA7Xpmt059025 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Nov 2021 01:33:51 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 10 Nov 2021 01:33:50 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 10 Nov 2021 01:33:51 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7XiT2020054; Wed, 10 Nov 2021 01:33:48 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I Subject: [PATCH 1/3] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Date: Wed, 10 Nov 2021 13:03:41 +0530 Message-ID: <20211110073343.12396-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211110073343.12396-1-kishon@ti.com> References: <20211110073343.12396-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D–July 2018–Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452f/sprz452f.pdf Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 865258d8c53c..38ab1d3f144d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -35,6 +35,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -105,6 +110,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -528,7 +535,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, @@ -540,6 +551,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -565,6 +581,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 bytes. Force the MRRS to + * 128 bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); From patchwork Wed Nov 10 07:33:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12611505 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9750BC433EF for ; Wed, 10 Nov 2021 07:34:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7BADD611C9 for ; Wed, 10 Nov 2021 07:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229930AbhKJHgs (ORCPT ); Wed, 10 Nov 2021 02:36:48 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54880 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229906AbhKJHgr (ORCPT ); Wed, 10 Nov 2021 02:36:47 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7Xsje087444; Wed, 10 Nov 2021 01:33:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636529634; bh=v2RhFi+MlwouzGOPhxiLA1I96shpgu+XqvCENLeXfLs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VqRg6PBrdd+KvCZQRbDRRuCWI2FnOkqp2ChTWmIz3vTPnLi9ZLXK8ZTppjvv2cVWY xBsXK9+T+eUF44sVXhrgpPfM7mkIh4FFNO0m8hkpsl6xWqB3y+LkqM1c7iLlgnvhvw +4jffbVI6nwpmZwj64MjZbDlRJOTKFlwQVm55XRY= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AA7XsiK128690 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Nov 2021 01:33:54 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 10 Nov 2021 01:33:54 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 10 Nov 2021 01:33:54 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7XiT3020054; Wed, 10 Nov 2021 01:33:51 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I Subject: [PATCH 2/3] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET Date: Wed, 10 Nov 2021 13:03:42 +0530 Message-ID: <20211110073343.12396-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211110073343.12396-1-kishon@ti.com> References: <20211110073343.12396-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org AM654 RootComplex has a hard coded 64 bit BAR of size 1MB and also has both MSI and MSI-X capability in it's config space. If PCIEPORTBUS is enabled, it tries to configure MSI-X and msix_mask_all() adds about 10 Second boot up delay when it tries to write to undefined location. Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET so that msix_map_region() returns NULL for Root Complex and avoid un-desirable writes to MSI-X table. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 38ab1d3f144d..6a352528d971 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -557,8 +557,14 @@ static void ks_pcie_quirk(struct pci_dev *dev) { 0, }, }; - if (pci_is_root_bus(bus)) + if (pci_is_root_bus(bus)) { bridge = dev; + if (pci_match_id(am6_pci_devids, bridge)) { + struct resource *r = &dev->resource[0]; + + r->flags |= IORESOURCE_UNSET; + } + } /* look for the host bridge */ while (!pci_is_root_bus(bus)) { From patchwork Wed Nov 10 07:33:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12611507 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB84AC433F5 for ; Wed, 10 Nov 2021 07:34:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C86B611F2 for ; Wed, 10 Nov 2021 07:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbhKJHg4 (ORCPT ); Wed, 10 Nov 2021 02:36:56 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54890 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229944AbhKJHgu (ORCPT ); Wed, 10 Nov 2021 02:36:50 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7Xvpr087459; Wed, 10 Nov 2021 01:33:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636529637; bh=Sk3ObvVytjQMAmV+/5MeG1AT2qz2GdCxjih7w+8/iO4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g0VXSYSLkO47EH6mU8F1HwdtnA0W2ssNXhz2D3VSeMqqQwmQUr0HkIXA9kfERx2Sa m47NnRtqi7naTuOfEVnpbJHVi3ANqe1z3wSCPGUZDU7Q4Md5Bq0IIj3UwxGtG92o2U p7o7AnIXT+3gJXilECEECNUR6/dWslkjndyQR8Lk= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AA7XvC5065168 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Nov 2021 01:33:57 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 10 Nov 2021 01:33:57 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 10 Nov 2021 01:33:57 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AA7XiT4020054; Wed, 10 Nov 2021 01:33:54 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I Subject: [PATCH 3/3] PCI: keystone: Set DMA mask and coherent DMA mask Date: Wed, 10 Nov 2021 13:03:43 +0530 Message-ID: <20211110073343.12396-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211110073343.12396-1-kishon@ti.com> References: <20211110073343.12396-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set DMA mask and coherent DMA mask such to indicate the device can address the entire address space (32-bit in the case of K2G and 48-bit in the case of AM654). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 6a352528d971..23649c01fe41 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1203,6 +1203,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) && + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { + dev_err(dev, "Cannot set DMA mask\n"); + return -EINVAL; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1;