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Mon, 15 Nov 2021 05:54:19 +0000 From: Vidya Sagar Subject: Query about secondary_bu_reset implementation To: , , , CC: Manikanta Maddireddy , , Message-ID: <40b03450-8f42-29d5-b65e-43644ec44940@nvidia.com> Date: Mon, 15 Nov 2021 11:24:16 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 Content-Language: en-US X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95819d04-0694-42dc-be63-08d9a7fc5fcc X-MS-TrafficTypeDiagnostic: BYAPR12MB3031: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oemTQ3m+dUQw7rzpMuQdAb+icymyzH+LO5HPRvtUKIi2TF4HHLK56h+GHuzO2OpVg6OU07S02hMiAVwC/wkKY+qgt32RGjwU8lH7Zhx0LGTR7r/pQoNCn2wVQkGeIV4B8BF7OyEIFt/x8BVI+VHdMftRNg7z5kHBxnMp2cOfLmgI+Fyxtc66323Q2YmdlWVZUBjldFYPLVdt1td+KaPzNL0BnLtmTyE+5A6tqv/gLkNen7xv5EONhuuvMf8FPDpzZJ9m76E2Vnmxs/RhrR0xs8b2F2wy+MaG6Oz8ISEtnR8bS1BU3cWd3L/T5Bi9Ep801eogUInJ74x+bE+NtLgfkalzCsaScZ+TEAglw9/9L3Fwirwne5bKj+WnMK14XAw3psf/8djtgPN3Fy5JST3Ar0vCo46nmDL0OevcCtno7gOXEI5FcKfKEz5B3bBShGLaaYNm+JH0VtSfs+JkFxWXmK+qfFv4ixlmkGaw9jCNY7iP5vyCc7FJxLEqXKoxFTdf7ycunVGIv92zaFNq55bfurWjXufWuhuBqcqyont4xFf/RYf53IDvZ5SBxzDwrzkKz00afUzSkC4X1Su/NC+uRTUnjuUznS96mDjsKIKJvLWOOw0RaRrr43LAaH6tW2835yQUqKLipV4fQpCYLzeNhPvXkHfVr0mr+gjhyvMRHv0iQvI3pENCF0lq+QKPu1lihN15msWUuO27aUK2k58SiAOX2rtDUzAU/zm3vrEei+w= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(16576012)(4326008)(8936002)(316002)(6666004)(186003)(356005)(5660300002)(26005)(110136005)(82310400003)(31696002)(508600001)(83380400001)(36860700001)(16526019)(31686004)(54906003)(7636003)(2616005)(426003)(47076005)(70206006)(70586007)(2906002)(8676002)(36756003)(336012)(86362001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2021 05:54:22.9447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95819d04-0694-42dc-be63-08d9a7fc5fcc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3031 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi folks, Regarding the below commit that added pci_dev_wait() API to wait for the device (supposed to be a downstream device.. i.e. and endpoint) get ready, I'm wondering, given the 'dev' pointer here points to an upstream device (i.e. a root port) because the same is passed to pcibios_reset_secondary_bus() API, how is passing a root port's dev pointer to pci_dev_wait() is going to serve the purpose? My understanding is that it would always get the response immediately as the reset is applied to the endpoint here (through secondary bus reset) and not to the root port, right? or am I missing something here? commit 6b2f1351af567110cec80d7c067314c633a14f50 Author: Sinan Kaya Date: Tue Feb 27 14:14:12 2018 -0600 PCI: Wait for device to become ready after secondary bus reset Setting Secondary Bus Reset of a downstream port sends a hot reset. PCIe r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can return CRS Completion Status following such a reset. Wait until the device becomes ready in that situation. Signed-off-by: Sinan Kaya Signed-off-by: Bjorn Helgaas Reviewed-by: Christoph Hellwig Thanks, Vidya Sagar diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index dde40506ffe5..0b8e8ee84bbc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4233,7 +4233,7 @@ int pci_reset_bridge_secondary_bus(struct pci_dev *dev) { pcibios_reset_secondary_bus(dev); - return 0; + return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);