From patchwork Tue Nov 16 11:20:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2640AC433EF for ; Tue, 16 Nov 2021 11:22:06 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA8F3619E3 for ; Tue, 16 Nov 2021 11:22:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EA8F3619E3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234827AbhKPLXx (ORCPT ); Tue, 16 Nov 2021 06:23:53 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:43909 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233230AbhKPLXn (ORCPT ); Tue, 16 Nov 2021 06:23:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061645; x=1668597645; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wegADxIWSHuMAOObITo7ccUCJ8XjO9VrO3nutuF9azU=; b=00xekKmbFdSA65NEAIVg0mu5nCFGu0Rw2yuHm7HkxjKB52a+9ut6uHW2 8oCmv+y0qy0r+M2fw7YqIGCEIn+OJPkryUXwY//+6Z4kzEQO3vM4p7QkS zuMQ1f/KOukWqb7GZPM4ajY9rCv0CQes7b1WFxgpN50djEv9jWr4s4KyM Z03DL33fV1t9yjOs1rqhXJ8iJHL+4shRmlUWaLBgoMQbnEBWSGvxL7puJ 12o/w+7fD1SDdfOQBw+rrIplNm7o/P/UhkoOoy6LCsYBF8aiQaW6sXljz nFTdlnJ8pBfVNyFUfK4kyCJ91z/0b93bIYVsybmhEb1bgAtcwmWSe+X58 Q==; IronPort-SDR: Bvkk+zeNVoYpl6/X08jQky86RTfzInacLNpyWnaOcY94bK/5FheoRBpt9r3hk2M471Vo8/9yCj QX0BMUJuDPl5jfYUa7eNemFUuf+Ix+xx1Vyxqulw+bQ7uoIzk6NVyvCoF5FNyOdQerTrKIEYr/ SAaLuRxQyReLCqwXvk6l7LR5GHFvaDWmJSgzJEJtIm4Ny8N+vMyfZa3RCVZivuI61IYisy+OSa jJQa+2XfcHH+7+2M+EJY34r6RXXczJxZgeAbNH+lTUw6MbrAomYCEpgUY6sAybKgOPMF6550Py riSPud519zcvY+GRDWVEpzRf X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="136715912" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:20:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:20:45 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:20:42 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 01/13] dmaengine: at_xdmac: Don't start transactions at tx_submit level Date: Tue, 16 Nov 2021 13:20:24 +0200 Message-ID: <20211116112036.96349-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org tx_submit is supposed to push the current transaction descriptor to a pending queue, waiting for issue_pending() to be called. issue_pending() must start the transfer, not tx_submit(). As the at_xdmac_start_xfer() is now called only from at_xdmac_advance_work() when !at_xdmac_chan_is_enabled(), the at_xdmac_chan_is_enabled() check is no longer needed in at_xdmac_start_xfer(), thus remove it. Clients of at_xdmac that assume that tx_submit() starts the transfer must be updated and call dma_async_issue_pending() if they miss to call it (one example is atmel_serial). Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 275a76f188ae..ccf796a3b9f3 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -385,9 +385,6 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); - if (at_xdmac_chan_is_enabled(atchan)) - return; - /* Set transfer as active to not try to start it again. */ first->active_xfer = true; @@ -479,9 +476,6 @@ static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", __func__, atchan, desc); list_add_tail(&desc->xfer_node, &atchan->xfers_list); - if (list_is_singular(&atchan->xfers_list)) - at_xdmac_start_xfer(atchan, desc); - spin_unlock_irqrestore(&atchan->lock, irqflags); return cookie; } From patchwork Tue Nov 16 11:20:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66B5AC433F5 for ; Tue, 16 Nov 2021 11:22:06 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D0F7619E3 for ; Tue, 16 Nov 2021 11:22:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3D0F7619E3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234954AbhKPLY0 (ORCPT ); Tue, 16 Nov 2021 06:24:26 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8906 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234871AbhKPLXv (ORCPT ); Tue, 16 Nov 2021 06:23:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061654; x=1668597654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xaQDP9vrd8gtsEUZVxgHa5VLGiEX80T1mW9+VkOCiK8=; b=cIhFLBS4jMYpAHFKje+Rd7Scpxotkw3b+k6y7iuGck75jNY5M8B2JT94 PxR0IWfJ3biJ4/nRPfDSVYRFUMSHrJhJULHWyzVR7bkUweJ4kd4bZI0VP Fh4IQa/opDqXqn9Ap9Fb2kxk8uf8QAlj8SE4fqm78BwY1lD+obLp1WCun fYNm89TFAjONwDOdGam8N5nH8GKsqnxjtovbs8H2M00aMGdRvYlbOq5wM 8902EHg1EKj+Ast+VfRj38EXF67oWVYwiAcZ2IuznrNaTFNKAxX30U99Q rsFpCy6eWVrEoSDvMGwjBc2i0s496MsKfk23e+M3RDquZ19gidG2c1bQk Q==; IronPort-SDR: AvLCpxdZ63WH8CN4xCAxbx9yjhF1PyUe6YemaWAxEi2Bq0ujWbW0gnjoK3O5S/HGcasdKvx77x apeh4dceBqeE27QgAp4ltVu6mvwjebZ2TfAogXZhAffZqzosAm6gVXAbE8QpZJHTCeUeWMRSWt 4VlBy64kDKrmiYVA6S56pjFSXqe8fxKCYGmSq+MUGZoOfMhnrozulvJdFMdVsBdhm6RH0CN8wr MlwiI0ah5GBDhcNo+p8swaPXQ8dr3ba3xnSs/PuPsmM92ww4NES2Pp/nVuk3TgTHL399mbjHYK OuyLDwj/SyxkZs9MOQ7p1gOP X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="144082826" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:20:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:20:49 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:20:45 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 02/13] tty: serial: atmel: Check return code of dmaengine_submit() Date: Tue, 16 Nov 2021 13:20:25 +0200 Message-ID: <20211116112036.96349-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The tx_submit() method of struct dma_async_tx_descriptor is entitled to do sanity checks and return errors if encountered. It's not the case for the DMA controller drivers that this client is using (at_h/xdmac), because they currently don't do sanity checks and always return a positive cookie at tx_submit() method. In case the controller drivers will implement sanity checks and return errors, print a message so that the client will be informed that something went wrong at tx_submit() level. Fixes: 08f738be88bb ("serial: at91: add tx dma support") Signed-off-by: Tudor Ambarus Acked-by: Richard Genoud --- drivers/tty/serial/atmel_serial.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 2c99a47a2535..376f7a9c2868 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -1004,6 +1004,11 @@ static void atmel_tx_dma(struct uart_port *port) desc->callback = atmel_complete_tx_dma; desc->callback_param = atmel_port; atmel_port->cookie_tx = dmaengine_submit(desc); + if (dma_submit_error(atmel_port->cookie_tx)) { + dev_err(port->dev, "dma_submit_error %d\n", + atmel_port->cookie_tx); + return; + } } if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) @@ -1258,6 +1263,11 @@ static int atmel_prepare_rx_dma(struct uart_port *port) desc->callback_param = port; atmel_port->desc_rx = desc; atmel_port->cookie_rx = dmaengine_submit(desc); + if (dma_submit_error(atmel_port->cookie_rx)) { + dev_err(port->dev, "dma_submit_error %d\n", + atmel_port->cookie_rx); + goto chan_err; + } return 0; From patchwork Tue Nov 16 11:20:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 316B0C433EF for ; Tue, 16 Nov 2021 11:22:11 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0757161055 for ; Tue, 16 Nov 2021 11:22:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0757161055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234798AbhKPLY2 (ORCPT ); Tue, 16 Nov 2021 06:24:28 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:9398 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234884AbhKPLXv (ORCPT ); Tue, 16 Nov 2021 06:23:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061654; x=1668597654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7030hvhk+GyvGFoZdT8hEUR+asnDYZB5TD3r6ASNYf8=; b=mphiBJUYtn6A5QqN4jYb4cvxrOwqR9tOYC8HTQMp+SxEUXvXxe6+zOqV USlYyrVV2RPdLdm78AzFRe/QFq4GR5oZJ0PCsqQO4+T0Hgwpuq4v1pDqO 31YWleFvVpaPXBsC4W/nczPKC6M2cvA5qxgZ4p+Dbmkm6LAwkFmo5aSSK SKG+jeAlbZfer7OcGr7xLB90lpe1q2n9juLcujDaQ54228dbFeEE3m6u8 R/xg6bNS0AgS8MRfmrecPykJJx1lMHBoHige7JcOSt9e78U+2WUOMdIF/ OTj4QTTYj+tBGDnPI7/MHgAuL7tUZ1ZSohpAWbDTBuFxcN67PIldFOjpW w==; IronPort-SDR: vP4IylrDmpr41BZ0h9LqOX4oYD4f/RLAgj6VzjZ+gMpavYHlc81Un63nhcsYlM2XPxcEvKsbMK i4v68XL3MUM1NfObDxUdnJoEPOBCmc/UgFYJ6paBjsxfvE7+qGuZfa51udfG+SwkaVaOU9Ff74 LlicIewnJGYIf76z2Ppjb3SYiVdDqP5DDKNlLCSjAMmBmTPf4zBr/P2METbN4Lh9MRkieXgbBh pXOYt5JhC6PT9/HxNVNkyNzn8/aCmSQME9qQqpWyIspUgJi1mZGm8hZj49GbCcfheuDceiXEt3 SWqBAexBtnZJgKADTUStv431 X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="139277971" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:20:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:20:52 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:20:49 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 03/13] tty: serial: atmel: Call dma_async_issue_pending() Date: Tue, 16 Nov 2021 13:20:26 +0200 Message-ID: <20211116112036.96349-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The driver wrongly assummed that tx_submit() will start the transfer, which is not the case, now that the at_xdmac driver is fixed. tx_submit is supposed to push the current transaction descriptor to a pending queue, waiting for issue_pending to be called. issue_pending must start the transfer, not tx_submit. While touching atmel_prepare_rx_dma(), introduce a local variable for the RX dma channel. Fixes: 34df42f59a60 ("serial: at91: add rx dma support") Fixes: 08f738be88bb ("serial: at91: add tx dma support") Signed-off-by: Tudor Ambarus --- drivers/tty/serial/atmel_serial.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 376f7a9c2868..b3e593f3c17f 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -1009,6 +1009,8 @@ static void atmel_tx_dma(struct uart_port *port) atmel_port->cookie_tx); return; } + + dma_async_issue_pending(chan); } if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) @@ -1191,6 +1193,7 @@ static void atmel_rx_from_dma(struct uart_port *port) static int atmel_prepare_rx_dma(struct uart_port *port) { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); + struct dma_chan *chan_rx; struct device *mfd_dev = port->dev->parent; struct dma_async_tx_descriptor *desc; dma_cap_mask_t mask; @@ -1203,11 +1206,13 @@ static int atmel_prepare_rx_dma(struct uart_port *port) dma_cap_zero(mask); dma_cap_set(DMA_CYCLIC, mask); - atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx"); - if (atmel_port->chan_rx == NULL) + chan_rx = dma_request_slave_channel(mfd_dev, "rx"); + if (chan_rx == NULL) goto chan_err; + atmel_port->chan_rx = chan_rx; + dev_info(port->dev, "using %s for rx DMA transfers\n", - dma_chan_name(atmel_port->chan_rx)); + dma_chan_name(chan_rx)); spin_lock_init(&atmel_port->lock_rx); sg_init_table(&atmel_port->sg_rx, 1); @@ -1239,8 +1244,7 @@ static int atmel_prepare_rx_dma(struct uart_port *port) config.src_addr = port->mapbase + ATMEL_US_RHR; config.src_maxburst = 1; - ret = dmaengine_slave_config(atmel_port->chan_rx, - &config); + ret = dmaengine_slave_config(chan_rx, &config); if (ret) { dev_err(port->dev, "DMA rx slave configuration failed\n"); goto chan_err; @@ -1249,7 +1253,7 @@ static int atmel_prepare_rx_dma(struct uart_port *port) * Prepare a cyclic dma transfer, assign 2 descriptors, * each one is half ring buffer size */ - desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, + desc = dmaengine_prep_dma_cyclic(chan_rx, sg_dma_address(&atmel_port->sg_rx), sg_dma_len(&atmel_port->sg_rx), sg_dma_len(&atmel_port->sg_rx)/2, @@ -1269,12 +1273,14 @@ static int atmel_prepare_rx_dma(struct uart_port *port) goto chan_err; } + dma_async_issue_pending(chan_rx); + return 0; chan_err: dev_err(port->dev, "RX channel not available, switch to pio\n"); atmel_port->use_dma_rx = false; - if (atmel_port->chan_rx) + if (chan_rx) atmel_release_rx_dma(port); return -EINVAL; } From patchwork Tue Nov 16 11:20:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 840A0C433EF for ; Tue, 16 Nov 2021 11:21:53 +0000 (UTC) X-Greylist: delayed 61 seconds by postgrey-1.37 at mail.kernel.org; Tue, 16 Nov 2021 11:21:52 UTC DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 45F3A619E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; 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IronPort-SDR: ptQ4ClZml3U4feFRucCBtUBeG4D6cQHb8HHbkcrn1IlLTDN/KcK6pT4Wi3j3ot6dqWZWUjNrt4 qFY95XrgSq5nnqwuT6spNUzvwjguNbOOb/zraNi0LwBvLcVt4yo7Rv9PFQKANzEz5sONIj8zm3 OhhNEpxKhrmw52vf6U01ViQ0u4si2LQElCV8/Jw1dzq9ByOQDMxGWJ58THrP33RS62c3F0fVnl ghKwNfymUoCILV+YIj42S6r/tDEoWB0hl49eBleOaeykPks2DROZvkbkig2gBUwAk6kN8EDwNe UByUwo93SLhxbXE4qFDt/GFq X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="143500766" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:20:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:20:56 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:20:53 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 04/13] dmaengine: at_xdmac: Start transfer for cyclic channels in issue_pending Date: Tue, 16 Nov 2021 13:20:27 +0200 Message-ID: <20211116112036.96349-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Cyclic channels must too call issue_pending in order to start a transfer. This wrongly worked before, because in the past the transfer was started at tx_submit level when only a desc in the transfer list. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index ccf796a3b9f3..9a5c68eda801 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1778,11 +1778,9 @@ static void at_xdmac_issue_pending(struct dma_chan *chan) dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); - if (!at_xdmac_chan_is_cyclic(atchan)) { - spin_lock_irqsave(&atchan->lock, flags); - at_xdmac_advance_work(atchan); - spin_unlock_irqrestore(&atchan->lock, flags); - } + spin_lock_irqsave(&atchan->lock, flags); + at_xdmac_advance_work(atchan); + spin_unlock_irqrestore(&atchan->lock, flags); return; } From patchwork Tue Nov 16 11:20:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3DD1C433F5 for ; Tue, 16 Nov 2021 11:21:53 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BD0561055 for ; Tue, 16 Nov 2021 11:21:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6BD0561055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234857AbhKPLYb (ORCPT ); Tue, 16 Nov 2021 06:24:31 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8935 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234902AbhKPLX5 (ORCPT ); Tue, 16 Nov 2021 06:23:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061661; x=1668597661; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e0xW+vtVjmLjsFf+6NA01ekbm3ImpiahvMaEB+GwpuM=; b=nMB8ns5RwTCa4XMS6D/o5KHwAeVHde/xR7XvcZRr55caPOy21a540Ykx KJoICsxfvZvA/YN2ayD96dtmYNpBzu/yoTAM5v13V64dz1WPAfKsHjawT bEfDayI4e6SCrId7Ps2Qjb6un5uW+s77OzWxG0DMBRec1OlcwgHKQFmoc H7mAgi2njB9IM5pP3A2PxCyQn4FEZo1G367a/y+ttp1Czp1JB98FxqqWg Gm/QLslRMaJy0dtk1pAgpK0hSVyw+64lecKr9Kh7fpszZv1iCf8exAPjs SZEmY18XO6JawNh/lDH3G414KLRtVY27/JaglapKH2FwVkSWxaJevlPx4 A==; IronPort-SDR: 26JTCN7gBgMYdZEXQI7b72/koxLIUrA+IBU2Rh29BjwXJWkJ4HldHAhu8kIzVeAFY3/mdHfInZ ALh/mOs6nsKCh4VURTMJt7om5GwtbgSpO25xRLkGCXOsGMyFSp6ZmzY1AlmRjMAca8WaymyrSn LzGJJcOuMjqijGlDuQquWZGSMZbqkC2ZP+Apvf9w8dtPo8mjlplIDQjRLwsHiiAvN3kq0xjje9 qNG2501NZt8wJ23Bm+SXuojEzY6OXradVemafDj3lLo1o32Y6r2c5xH85c0L7RICjbPWtzkrN+ lK5x2BCsTllf3+j66cB036Gt X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="144082858" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:00 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:20:56 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 05/13] dmaengine: at_xdmac: Print debug message after realeasing the lock Date: Tue, 16 Nov 2021 13:20:28 +0200 Message-ID: <20211116112036.96349-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org It is desirable to do the prints without the lock held if possible. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 9a5c68eda801..b45ae4fee9db 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -473,10 +473,12 @@ static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) spin_lock_irqsave(&atchan->lock, irqflags); cookie = dma_cookie_assign(tx); - dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", - __func__, atchan, desc); list_add_tail(&desc->xfer_node, &atchan->xfers_list); spin_unlock_irqrestore(&atchan->lock, irqflags); + + dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", + __func__, atchan, desc); + return cookie; } From patchwork Tue Nov 16 11:20:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D063CC43219 for ; Tue, 16 Nov 2021 11:21:54 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 99C8F61055 for ; Tue, 16 Nov 2021 11:21:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 99C8F61055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234914AbhKPLYc (ORCPT ); Tue, 16 Nov 2021 06:24:32 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:3771 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234908AbhKPLYB (ORCPT ); Tue, 16 Nov 2021 06:24:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061665; x=1668597665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5xHR1pSMET19iq1R2ORya7V1yqiD9c113vKBUFK5yTw=; b=U1YFmQ5AnSAKEHVmssrZAqJiNwlV3zBa3wN9FQefYFVf0OAwQiU5y+dz EYpuialrpWagzhRkibhmjSCNZ0pMTCJvBtNYX4BVrYV+jyFUzHY0lFc55 WEiEKxnrXpxtLk5FsjArHxKahDLgv1Ya2uXKaQSNvcz2rZVRFCCIMjbi9 nylsS7hzwGJw4zmjEssyWFC4fIrGvjZmI0qxUHZHYBtYlMqq2KcvqY5vx wuIujdJFnKv6dEPMohdPGJe/vPWpKanW8iZM/S4lQI5Pna4DxWdbR7gmk 1n4hMy2KeQT/aWh6au/L2gS8r9gIjpWpS8fbOAaMy9ukZ39G44/xwq813 g==; IronPort-SDR: nEaswDJg6UvN1Ak1k5snxDBueJXCkjA/TZHVY+1/T2B1dAY07tQGG1LrfRuZa9m+38lrF9XE0P lKna2Wl5adWWKHh/HCQ3jNYY7/wZmbI7calkFrXuiDctO/acd4xL3gHUMYLixQoumL3wgP3HRz i8KsDoOBZB83LdFviPxl7FyfGzE8ZSUseaKNR/ws+hrHJ+qfTCCfDzF+9W19ycXtRH/yVsQfXh mYe9HJf/p4+BhHSyqyAKvQY/Wd5pnsCAb1HE/Ua7Ir3jOAjSVIdpQugbcclg/axCOctF9ta0IR 94LEaPFwvDU5xku5ARpCm85x X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="143500780" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:03 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:00 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 06/13] dmaengine: at_xdmac: Fix concurrency over chan's completed_cookie Date: Tue, 16 Nov 2021 13:20:29 +0200 Message-ID: <20211116112036.96349-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Caller of dma_cookie_complete is expected to hold a lock to prevent concurrency over the channel's completed cookie marker. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index b45ae4fee9db..4d8476845c20 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1703,11 +1703,10 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) } txd = &desc->tx_dma_desc; - + dma_cookie_complete(txd); at_xdmac_remove_xfer(atchan, desc); spin_unlock_irq(&atchan->lock); - dma_cookie_complete(txd); if (txd->flags & DMA_PREP_INTERRUPT) dmaengine_desc_get_callback_invoke(txd, NULL); From patchwork Tue Nov 16 11:20:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F817C4167D for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D8B761055 for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2D8B761055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234980AbhKPLYe (ORCPT ); Tue, 16 Nov 2021 06:24:34 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8953 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234930AbhKPLYE (ORCPT ); Tue, 16 Nov 2021 06:24:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061667; x=1668597667; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IzKN39oOHNC3CK9tz3WGrvZQjLqHyTGav61lvPMp9Bg=; b=i/7fHNstzAYJQFeUGwIoSFbc7giAVSCYPm4epD8LKQZ7MfwjELEOuvKK kfYarJx1TOjtueGQcf7YPe897cPMA09rAp/f5yp6KRpHOBsx8EC6HtDsi BR2CXLrAhFKt+aB0l5D65CRqlvU/3QRBVFA3ZUimYxqU3UXMmtz78rmau sU1OuPAl5IeeyBNc0vNr1/bSZV/1bAOm6YVt/VieLv51H1sqL+8gJhpw6 QhHHkJBReNqjqX8ReFa5HeLrJyw32KOX1EQ5tyr/0jyk+8nLGqfFfzFxp uzQx2PgZIKm1P6uZ0d9AU3sLWBPAdH4M/OK+CpfYUIjrVbPYo+wTn8vBt Q==; IronPort-SDR: VKKuqCuyUcNCiCN80wBHip317sB00kXuRGeonrJQnv2IFvjjiUmiX6wroEunWGJ4uQfLejH19s pWplCng62sowOwenBsynkU+bqaYzu6WaQ4WFRbhCYl5vJxY/uEfFlegEucqDzwjvOI3WmrI9fY a7mnqXY2bPV8XUZXORIM/dRHxsTXE8hHnM8O+PI9bCubO4xjD047i70seAWi+UszaQSIHqH9i0 ealXSuf88TDbd9+iOHfpcnv7ETXeeuNMFhLdift3oC1Q5BdbQ0wXTh0++aMv6+Irppym7eXOnI zgPzOHC64GPtfbdtvg4YJNni X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="144082887" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:07 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:07 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:04 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 07/13] dmaengine: at_xdmac: Fix race for the tx desc callback Date: Tue, 16 Nov 2021 13:20:30 +0200 Message-ID: <20211116112036.96349-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The transfer descriptors were wrongly moved to the free descriptors list before calling the tx desc callback. As the DMA engine drivers drop any locks before calling the callback function, txd could be taken again, resulting in its callback called prematurely. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 4d8476845c20..2cc9af222681 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1582,20 +1582,6 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, return ret; } -/* Call must be protected by lock. */ -static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, - struct at_xdmac_desc *desc) -{ - dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); - - /* - * Remove the transfer from the transfer list then move the transfer - * descriptors into the free descriptors list. - */ - list_del(&desc->xfer_node); - list_splice_init(&desc->descs_list, &atchan->free_descs_list); -} - static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) { struct at_xdmac_desc *desc; @@ -1704,7 +1690,8 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) txd = &desc->tx_dma_desc; dma_cookie_complete(txd); - at_xdmac_remove_xfer(atchan, desc); + /* Remove the transfer from the transfer list. */ + list_del(&desc->xfer_node); spin_unlock_irq(&atchan->lock); if (txd->flags & DMA_PREP_INTERRUPT) @@ -1713,6 +1700,8 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) dma_run_dependencies(txd); spin_lock_irq(&atchan->lock); + /* Move the xfer descriptors into the free descriptors list. */ + list_splice_init(&desc->descs_list, &atchan->free_descs_list); at_xdmac_advance_work(atchan); spin_unlock_irq(&atchan->lock); } @@ -1859,8 +1848,10 @@ static int at_xdmac_device_terminate_all(struct dma_chan *chan) cpu_relax(); /* Cancel all pending transfers. */ - list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) - at_xdmac_remove_xfer(atchan, desc); + list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) { + list_del(&desc->xfer_node); + list_splice_init(&desc->descs_list, &atchan->free_descs_list); + } clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); From patchwork Tue Nov 16 11:20:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B26BCC433F5 for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8110261055 for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8110261055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234943AbhKPLYg (ORCPT ); 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d="scan'208";a="139278003" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:11 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:07 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 08/13] dmaengine: at_xdmac: Move the free desc to the tail of the desc list Date: Tue, 16 Nov 2021 13:20:31 +0200 Message-ID: <20211116112036.96349-9-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org So that we don't use the same desc over and over again. Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 2cc9af222681..8804a86a9bcc 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -729,7 +729,8 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (!desc) { dev_err(chan2dev(chan), "can't get descriptor\n"); if (first) - list_splice_init(&first->descs_list, &atchan->free_descs_list); + list_splice_tail_init(&first->descs_list, + &atchan->free_descs_list); goto spin_unlock; } @@ -817,7 +818,8 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, if (!desc) { dev_err(chan2dev(chan), "can't get descriptor\n"); if (first) - list_splice_init(&first->descs_list, &atchan->free_descs_list); + list_splice_tail_init(&first->descs_list, + &atchan->free_descs_list); spin_unlock_irqrestore(&atchan->lock, irqflags); return NULL; } @@ -1051,8 +1053,8 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, src_addr, dst_addr, xt, chunk); if (!desc) { - list_splice_init(&first->descs_list, - &atchan->free_descs_list); + list_splice_tail_init(&first->descs_list, + &atchan->free_descs_list); return NULL; } @@ -1132,7 +1134,8 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, if (!desc) { dev_err(chan2dev(chan), "can't get descriptor\n"); if (first) - list_splice_init(&first->descs_list, &atchan->free_descs_list); + list_splice_tail_init(&first->descs_list, + &atchan->free_descs_list); return NULL; } @@ -1308,8 +1311,8 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, sg_dma_len(sg), value); if (!desc && first) - list_splice_init(&first->descs_list, - &atchan->free_descs_list); + list_splice_tail_init(&first->descs_list, + &atchan->free_descs_list); if (!first) first = desc; @@ -1701,7 +1704,8 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) spin_lock_irq(&atchan->lock); /* Move the xfer descriptors into the free descriptors list. */ - list_splice_init(&desc->descs_list, &atchan->free_descs_list); + list_splice_tail_init(&desc->descs_list, + &atchan->free_descs_list); at_xdmac_advance_work(atchan); spin_unlock_irq(&atchan->lock); } @@ -1850,7 +1854,8 @@ static int at_xdmac_device_terminate_all(struct dma_chan *chan) /* Cancel all pending transfers. */ list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) { list_del(&desc->xfer_node); - list_splice_init(&desc->descs_list, &atchan->free_descs_list); + list_splice_tail_init(&desc->descs_list, + &atchan->free_descs_list); } clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); From patchwork Tue Nov 16 11:20:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B62FC433F5 for ; Tue, 16 Nov 2021 11:22:21 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45EDA61055 for ; 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IronPort-SDR: 5I2Vtcxo1XNNrl5JKRV9Iz2lWjTf+jEudImraPfg9kfTsmk9Gq7BpbHvQWy8Z76ZizoLZC3vZg BTGwli5YolnlP5P8j2XexhEXs6jh126hdPMjF/YfFzSBYv7O9/IYKm8QZhheb2mNtSo7qIzepI uGgKLlma30lWyEE+YiRlCY3Aj7rc0Z0V17CK3GDQBzM2niE0PCJkK6kq75eTlQsZo7rLEh8ZOI /Gr8YAacR+NXlJAbFzulHwa1LeroQuar2AXH6L9I4Bsy/tOMAubQSpE+HRiHi9X8q8NKuKtoNt R8xnXSG44ai+VvlgIeZKpKym X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="144082911" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:14 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:11 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 09/13] dmaengine: at_xdmac: Fix concurrency over xfers_list Date: Tue, 16 Nov 2021 13:20:32 +0200 Message-ID: <20211116112036.96349-10-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Since tx_submit can be called from a hard irq, xfers_list must be protected with a lock to avoid concurency on the list's elements. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 8804a86a9bcc..81f6f1357dcb 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1608,14 +1608,17 @@ static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) struct at_xdmac_desc *desc; struct dma_async_tx_descriptor *txd; - if (!list_empty(&atchan->xfers_list)) { - desc = list_first_entry(&atchan->xfers_list, - struct at_xdmac_desc, xfer_node); - txd = &desc->tx_dma_desc; - - if (txd->flags & DMA_PREP_INTERRUPT) - dmaengine_desc_get_callback_invoke(txd, NULL); + spin_lock_irq(&atchan->lock); + if (list_empty(&atchan->xfers_list)) { + spin_unlock_irq(&atchan->lock); + return; } + desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, + xfer_node); + spin_unlock_irq(&atchan->lock); + txd = &desc->tx_dma_desc; + if (txd->flags & DMA_PREP_INTERRUPT) + dmaengine_desc_get_callback_invoke(txd, NULL); } static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) From patchwork Tue Nov 16 11:20:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D837AC43219 for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A422863236 for ; Tue, 16 Nov 2021 11:21:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A422863236 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234947AbhKPLYm (ORCPT ); Tue, 16 Nov 2021 06:24:42 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:18384 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234945AbhKPLYR (ORCPT ); Tue, 16 Nov 2021 06:24:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061681; x=1668597681; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4UJToV8z1d1CSnT1DHee/do0TBGgvnsbC5y36KVHVoA=; b=beaHuCj4NPRolv7fmus05vMwvS9/ovhXI+GrWRIENdaFTPKVFLXo+cLT pyjZh1jhvZ7z/A2tyKuWUfbm4P7smxgzfirkS1UofsfbRukQDjnDAHy0u si71DZUnZl5xSur66eWCQKmV0KaCzMXxTJBnbaOnYDBChDxxb//tTorrj aV5vSOZIsy0ymSmwCa/K9Ix7ythtg8ERwSjupo3e7pNp1fxYd3EhYpF6C WcV4LbYFFODl+kA251am7O3WgYTgCYmSHlZEPHrBpY31/nZ02mNReAw67 qKofZrJvT1ItV6/wHoJTfTRNtSKdl5MHnVI4wLqoXMyPuJY9VyH82+FVQ w==; IronPort-SDR: brqGcVkMu6p19txpv00wUnn71TVfCG/Ak3bOmAroJqg/zfSScjECH7yB/aGDZOqn11UT/OC+/Y ZjM9fxrvI+xa1qDd65NyoMUrh6YWfWdMAmOdRX1cwD0HWmGyKTZ2z2srUmjGY6ny/Ev1i80htW f0Xl/cmjWuPozpNSyhYy2tnnp92N7d2fuU05mZWpsnE8QpKQToEoA3YjoJs2oBpnZjvOONrd6R 6lfSaoibxWsFaXg7ycpXfs5u5XuqtiEB+NFA/e9Ziq6KXqKNp4SXVIDpJ99PWH89R5D96hS4E5 QcnZftuxmykH0PAmGLSC8s0t X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="152085416" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:19 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:18 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:15 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 10/13] dmaengine: at_xdmac: Remove a level of indentation in at_xdmac_advance_work() Date: Tue, 16 Nov 2021 13:20:33 +0200 Message-ID: <20211116112036.96349-11-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org It's easier to read code with fewer levels of indentation. Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 81f6f1357dcb..89d0fc229d68 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1593,14 +1593,14 @@ static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) * If channel is enabled, do nothing, advance_work will be triggered * after the interruption. */ - if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { - desc = list_first_entry(&atchan->xfers_list, - struct at_xdmac_desc, - xfer_node); - dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); - if (!desc->active_xfer) - at_xdmac_start_xfer(atchan, desc); - } + if (at_xdmac_chan_is_enabled(atchan) || list_empty(&atchan->xfers_list)) + return; + + desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, + xfer_node); + dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + if (!desc->active_xfer) + at_xdmac_start_xfer(atchan, desc); } static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) From patchwork Tue Nov 16 11:20:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D36C43219 for ; Tue, 16 Nov 2021 11:22:23 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6811E61994 for ; Tue, 16 Nov 2021 11:22:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6811E61994 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235072AbhKPLZK (ORCPT ); Tue, 16 Nov 2021 06:25:10 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:18426 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234882AbhKPLY0 (ORCPT ); Tue, 16 Nov 2021 06:24:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061689; x=1668597689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WIpbBPu+LDILnDfRZxv4mO7fUQqnAghfChRhfJnCk4s=; b=qf5qY/GIbLzigIcQW/Fs/U7DdRvziok5U5LtBU/FMu64LC12WAYhGIl8 fdRY8zwlW/h83fdNn05bAxaihgdxQamSoyohWw/8eE9t3k/JnUNpZv73e 8c1JgDiqQdvt1AgWaVlL+UiaDqDpgXpdJTA7eO7sORaMe1gnLK4we/yuj OeVQSOtS3TryxcsK6P8p4pEudWjy+OTun0faTZidFW3KP3+43v78YAKxe p/L6aG5KntbFyryMTz3+4aGC5ueIhAlB3AGQY9dJJoZJxrdYBjaSqBdi2 XOcWzAc/TdhNUUh3QSPeVFqWPWqqExsM6nyDMAHNp/ukZkZtnHGy/CCrd w==; IronPort-SDR: UJTd3fqXcByB4684k5Xcsv1qqUyJGo9NJsIK5Ns6PXs1zkKvKFpIzlkMPqCh3Urt1ctD/I8QCR wc9Wkc0fuVKzAwd+2oxGAoYd2sPV6ENaCg2aOEp4YoloplUsu6K/tNFSjFUz3yVmRMuVAaXc2+ X0oYi3La+NuzJYO2lOWgB9Zcczvbwa6FywPfEyFsff7bJ8dSrrQXNjuynbPW6uoLO3qFxFDewD /sJU1TPrfL5kIP7itZjd9w2+O8pE/LBvG2g3AvWQf67RzNSMM7tw2oZseu7dXc7AKzgNcdAyl3 WL2a3tDBKzuhoDAM7aE6PTJG X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="152085434" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:21 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:18 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 11/13] dmaengine: at_xdmac: Fix lld view setting Date: Tue, 16 Nov 2021 13:20:34 +0200 Message-ID: <20211116112036.96349-12-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org AT_XDMAC_CNDC_NDVIEW_NDV3 was set even for AT_XDMAC_MBR_UBC_NDV2, because of the wrong bit handling. Fix it. Fixes: ee0fe35c8dcd ("dmaengine: xdmac: Handle descriptor's view 3 registers") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 89d0fc229d68..ba2fe383fa5e 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -99,6 +99,7 @@ #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ +#define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27) #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ @@ -402,7 +403,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, */ if (at_xdmac_chan_is_cyclic(atchan)) reg = AT_XDMAC_CNDC_NDVIEW_NDV1; - else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) + else if ((first->lld.mbr_ubc & + AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3) reg = AT_XDMAC_CNDC_NDVIEW_NDV3; else reg = AT_XDMAC_CNDC_NDVIEW_NDV2; From patchwork Tue Nov 16 11:20:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF85DC43217 for ; Tue, 16 Nov 2021 11:21:57 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D6C861055 for ; Tue, 16 Nov 2021 11:21:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9D6C861055 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235014AbhKPLYw (ORCPT ); Tue, 16 Nov 2021 06:24:52 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:9441 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234876AbhKPLYY (ORCPT ); Tue, 16 Nov 2021 06:24:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061687; x=1668597687; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9cKQ8DLE+KtiJG/oBAobTtHTIQZeH+YXTokO734xUTw=; b=r9ucFM20OtXXrUpnO87TnNSGTxqx4IIju26qOpE5NHggrxnmen5Nr33u 5mpFVHUqvpYOhHrK2c9gvbNeJX8hQETuQa31SdKx56dur3eO9JwX8+AMT d+2YqXq5SQXO7ebmIy9jv09w4qpWqPUoOnGrLs77/Kk1/bmc0a4jFHQl5 0WYXfdLiTCtkJMLewr/xPDG+62h0IFCPhhRkeRMIGUqGct79RBSs0fT78 h/BfQzHQd42Xfd9C2nsGMh97HmuGVg3JRi6T1+S8Yu6kukxsZWMi4PPaI 0Xw32Ag0WonmjFxO9f7Q7xfN7y0J7HVgsFLURcAAksi9TOpU4H2KVyaYp w==; IronPort-SDR: YbAApsWQeRxOCI3wgOMxDyDDfskDzjL/SsnFWmWm9ppDJ/xZkCCvkPmfIVqn1+bTDJaqQFaBux Cu6f3YZwNmxcPHgqKzBQv/bA/Akz3pmi+Ky4MGP8NO7q0psMB+tJRC0vb/eIwey841NUsRgnGQ vZGp57Oo+zj7bAngS96MK5GmNTW7oWFrj2h09yCjZECI5G/s1wNbWS9lGPvVLPP3az1GT/ufJa HoSo/cHxJpNwPodask0Jr1F6VHo3R1H+OQKsb/vy8T68i4llqciAMQC5abkcGhV87Q1CgCr6nQ efTizVsPZH1O8g0ubRO0nynR X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="139278017" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:25 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:22 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 12/13] dmaengine: at_xdmac: Fix at_xdmac_lld struct definition Date: Tue, 16 Nov 2021 13:20:35 +0200 Message-ID: <20211116112036.96349-13-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The hardware channel next descriptor view structure contains just fields of 32 bits, while dma_addr_t can be of type u64 or u32 depending on CONFIG_ARCH_DMA_ADDR_T_64BIT. Force u32 to comply with what the hardware expects. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index ba2fe383fa5e..ccd6ddb12b83 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -253,15 +253,15 @@ struct at_xdmac { /* Linked List Descriptor */ struct at_xdmac_lld { - dma_addr_t mbr_nda; /* Next Descriptor Member */ - u32 mbr_ubc; /* Microblock Control Member */ - dma_addr_t mbr_sa; /* Source Address Member */ - dma_addr_t mbr_da; /* Destination Address Member */ - u32 mbr_cfg; /* Configuration Register */ - u32 mbr_bc; /* Block Control Register */ - u32 mbr_ds; /* Data Stride Register */ - u32 mbr_sus; /* Source Microblock Stride Register */ - u32 mbr_dus; /* Destination Microblock Stride Register */ + u32 mbr_nda; /* Next Descriptor Member */ + u32 mbr_ubc; /* Microblock Control Member */ + u32 mbr_sa; /* Source Address Member */ + u32 mbr_da; /* Destination Address Member */ + u32 mbr_cfg; /* Configuration Register */ + u32 mbr_bc; /* Block Control Register */ + u32 mbr_ds; /* Data Stride Register */ + u32 mbr_sus; /* Source Microblock Stride Register */ + u32 mbr_dus; /* Destination Microblock Stride Register */ }; /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */ From patchwork Tue Nov 16 11:20:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12622051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95DE9C433FE for ; Tue, 16 Nov 2021 11:22:22 +0000 (UTC) Received: from vger.kernel.org (unknown [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67EF8619E8 for ; Tue, 16 Nov 2021 11:22:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 67EF8619E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235056AbhKPLZE (ORCPT ); Tue, 16 Nov 2021 06:25:04 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8935 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234894AbhKPLYa (ORCPT ); Tue, 16 Nov 2021 06:24:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637061693; x=1668597693; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wxTxrAyDEObrB+6U2ISe3JfymaOVc1XxubqpmlFsG4s=; b=kXYLc/l1Jw8i4Mc574yLMUEFhVX1EQ0lCcS81UBiOIiC7lOpBPaj9MwW 1ix/SZJ64CfIpM/uCY24MobeWlyiONcvGEumC/3pf64AfOPSXyT2SeIIf rWiiLEUDRY8LhPhstuueJ4bNfDBy4YmLA4NvYkxVM5T6LfosaHqqp+Oxz /HVxiR/YIsra051Q6AF8l4sRptnqU/XQcM25uOw2ngSOtHezCoo4xZFVF jps+liwgDN9QxWNaSRzRy5Un3pb8OUrtNFUA28Qdq71I3HcCbqUR71nl4 G1QCVrDqwVVFJYo43Wbil2QIm7luVQKR2VVB4H76h+qz7ZInBjrGysM2h w==; IronPort-SDR: +klTsaNsJRHc5UsqIf+tQaaWFIm16NfFRFpzoUyBGO6O8OEvukF0O4L96+arZyMRX/SkdOQZJq LmzV75PpBvQTEWYooZM4m0WhyAVvSX7ZNWmXmr+q4suV3MU1bCUE6nyt6yf64mgqT0KMHKxWwN KKjQb/yrF8f9Zv+CJYrNPTvJX5DqlNaWCPgQV5qsRpQqGKRkcQyztyE8Gf7w75iPNXivAbFyWl eE2xhg6sJAugeXUTCobhUPlR6mdTOoIXy788ooEG3NMAsQ7g25Bd7rCKCm61nnh08OHzlOBHzq ASmeDMtMKdzp1PHkvTd4Ep7J X-IronPort-AV: E=Sophos;i="5.87,239,1631602800"; d="scan'208";a="144082954" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2021 04:21:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 16 Nov 2021 04:21:29 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 16 Nov 2021 04:21:25 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 13/13] dmaengine: at_xdmac: Fix race over irq_status Date: Tue, 16 Nov 2021 13:20:36 +0200 Message-ID: <20211116112036.96349-14-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211116112036.96349-1-tudor.ambarus@microchip.com> References: <20211116112036.96349-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Tasklets run with interrupts enabled, so we need to protect atchan->irq_status with spin_lock_irq() otherwise the tasklet can be interrupted by the IRQ that modifies irq_status. While at this, rewrite at_xdmac_tasklet() so that we get rid of a level of indentation. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 80 +++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 43 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index ccd6ddb12b83..082c18d45188 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -1623,6 +1623,7 @@ static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) dmaengine_desc_get_callback_invoke(txd, NULL); } +/* Called with atchan->lock held. */ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) { struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); @@ -1641,8 +1642,6 @@ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) if (atchan->irq_status & AT_XDMAC_CIS_ROIS) dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); - spin_lock_irq(&atchan->lock); - /* Channel must be disabled first as it's not done automatically */ at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) @@ -1652,10 +1651,8 @@ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) struct at_xdmac_desc, xfer_node); - spin_unlock_irq(&atchan->lock); - /* Print bad descriptor's details if needed */ - dev_dbg(chan2dev(&atchan->chan), + dev_err(chan2dev(&atchan->chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da, bad_desc->lld.mbr_ubc); @@ -1665,55 +1662,52 @@ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) static void at_xdmac_tasklet(struct tasklet_struct *t) { + struct dma_async_tx_descriptor *txd; struct at_xdmac_chan *atchan = from_tasklet(atchan, t, tasklet); struct at_xdmac_desc *desc; u32 error_mask; + if (at_xdmac_chan_is_cyclic(atchan)) + return at_xdmac_handle_cyclic(atchan); + + error_mask = AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS | + AT_XDMAC_CIS_ROIS; + + spin_lock_irq(&atchan->lock); dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n", __func__, atchan->irq_status); + if (!(atchan->irq_status & AT_XDMAC_CIS_LIS) && + !(atchan->irq_status & error_mask)) { + return spin_unlock_irq(&atchan->lock); + } - error_mask = AT_XDMAC_CIS_RBEIS - | AT_XDMAC_CIS_WBEIS - | AT_XDMAC_CIS_ROIS; - - if (at_xdmac_chan_is_cyclic(atchan)) { - at_xdmac_handle_cyclic(atchan); - } else if ((atchan->irq_status & AT_XDMAC_CIS_LIS) - || (atchan->irq_status & error_mask)) { - struct dma_async_tx_descriptor *txd; - - if (atchan->irq_status & error_mask) - at_xdmac_handle_error(atchan); - - spin_lock_irq(&atchan->lock); - desc = list_first_entry(&atchan->xfers_list, - struct at_xdmac_desc, - xfer_node); - dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); - if (!desc->active_xfer) { - dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting"); - spin_unlock_irq(&atchan->lock); - return; - } + if (atchan->irq_status & error_mask) + at_xdmac_handle_error(atchan); - txd = &desc->tx_dma_desc; - dma_cookie_complete(txd); - /* Remove the transfer from the transfer list. */ - list_del(&desc->xfer_node); - spin_unlock_irq(&atchan->lock); + desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, + xfer_node); + dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + if (!desc->active_xfer) { + dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting"); + return spin_unlock_irq(&atchan->lock); + } - if (txd->flags & DMA_PREP_INTERRUPT) - dmaengine_desc_get_callback_invoke(txd, NULL); + txd = &desc->tx_dma_desc; + dma_cookie_complete(txd); + /* Remove the transfer from the transfer list. */ + list_del(&desc->xfer_node); + spin_unlock_irq(&atchan->lock); - dma_run_dependencies(txd); + if (txd->flags & DMA_PREP_INTERRUPT) + dmaengine_desc_get_callback_invoke(txd, NULL); - spin_lock_irq(&atchan->lock); - /* Move the xfer descriptors into the free descriptors list. */ - list_splice_tail_init(&desc->descs_list, - &atchan->free_descs_list); - at_xdmac_advance_work(atchan); - spin_unlock_irq(&atchan->lock); - } + dma_run_dependencies(txd); + + spin_lock_irq(&atchan->lock); + /* Move the xfer descriptors into the free descriptors list. */ + list_splice_tail_init(&desc->descs_list, &atchan->free_descs_list); + at_xdmac_advance_work(atchan); + spin_unlock_irq(&atchan->lock); } static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)