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[210.10.213.150]) by smtp.gmail.com with ESMTPSA id p19sm22517713pfo.92.2021.11.16.17.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Nov 2021 17:01:57 -0800 (PST) From: Joel Stanley To: Jeremy Kerr , Oskar Senft Subject: [PATCH] drm/aspeed: Fix vga_pw sysfs output Date: Wed, 17 Nov 2021 09:01:45 +0800 Message-Id: <20211117010145.297253-1-joel@jms.id.au> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, David Airlie , dri-devel@lists.freedesktop.org, Andrew Jeffery , Ali El-Haj-Mahmoud Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Before the drm driver had support for this file there was a driver that exposed the contents of the vga password register to userspace. It would present the entire register instead of interpreting it. The drm implementation chose to mask of the lower bit, without explaining why. This breaks the existing userspace, which is looking for 0xa8 in the lower byte. Change our implementation to expose the entire register. Fixes: 696029eb36c0 ("drm/aspeed: Add sysfs for output settings") Reported-by: Oskar Senft Signed-off-by: Joel Stanley Tested-by: Oskar Senft Reviewed-by: Jeremy Kerr --- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index b53fee6f1c17..65f172807a0d 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -291,7 +291,7 @@ vga_pw_show(struct device *dev, struct device_attribute *attr, char *buf) if (rc) return rc; - return sprintf(buf, "%u\n", reg & 1); + return sprintf(buf, "%u\n", reg); } static DEVICE_ATTR_RO(vga_pw);