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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:12 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 1/7] media: hantro: add support for reset lines Date: Mon, 22 Nov 2021 19:46:56 +0100 Message-Id: <20211122184702.768341-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add support for them. Signed-off-by: Jernej Skrabec --- drivers/staging/media/hantro/hantro.h | 3 +++ drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 7da23f7f207a..33eb3e092cc1 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev) * @dev: Pointer to device for convenient logging using * dev_ macros. * @clocks: Array of clock handles. + * @resets: Array of reset handles. * @reg_bases: Mapped addresses of VPU registers. * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. @@ -190,6 +192,7 @@ struct hantro_dev { struct platform_device *pdev; struct device *dev; struct clk_bulk_data *clocks; + struct reset_control *resets; void __iomem **reg_bases; void __iomem *enc_base; void __iomem *dec_base; diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ab2467998d29..8c3de31f51b3 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev) return PTR_ERR(vpu->clocks[0].clk); } + vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); + if (IS_ERR(vpu->resets)) + return PTR_ERR(vpu->resets); + num_bases = vpu->variant->num_regs ?: 1; vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, sizeof(*vpu->reg_bases), GFP_KERNEL); @@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(vpu->dev); pm_runtime_enable(vpu->dev); + ret = reset_control_deassert(vpu->resets); + if (ret) { + dev_err(&pdev->dev, "Failed to deassert resets\n"); + return ret; + } + ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); if (ret) { dev_err(&pdev->dev, "Failed to prepare clocks\n"); - return ret; + goto err_rst_assert; } ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); @@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev) v4l2_device_unregister(&vpu->v4l2_dev); err_clk_unprepare: clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); +err_rst_assert: + reset_control_assert(vpu->resets); pm_runtime_dont_use_autosuspend(vpu->dev); pm_runtime_disable(vpu->dev); return ret; @@ -1055,6 +1067,7 @@ static int hantro_remove(struct platform_device *pdev) v4l2_m2m_release(vpu->m2m_dev); v4l2_device_unregister(&vpu->v4l2_dev); clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); + reset_control_assert(vpu->resets); pm_runtime_dont_use_autosuspend(vpu->dev); pm_runtime_disable(vpu->dev); return 0; From patchwork Mon Nov 22 18:46:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12632651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2B9FC433F5 for ; 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:14 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 2/7] media: hantro: vp9: use double buffering if needed Date: Mon, 22 Nov 2021 19:46:57 +0100 Message-Id: <20211122184702.768341-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some G2 variants need double buffering to be enabled in order to work correctly, like that found in Allwinner H6 SoC. Add platform quirk for that. Signed-off-by: Jernej Skrabec Reviewed-by: Andrzej Pietrasiewicz --- drivers/staging/media/hantro/hantro.h | 2 ++ drivers/staging/media/hantro/hantro_g2_regs.h | 1 + drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index 33eb3e092cc1..d03824fa3222 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -73,6 +73,7 @@ struct hantro_irq { * @num_clocks: number of clocks in the array * @reg_names: array of register range names * @num_regs: number of register range names in the array + * @double_buffer: core needs double buffering */ struct hantro_variant { unsigned int enc_offset; @@ -94,6 +95,7 @@ struct hantro_variant { int num_clocks; const char * const *reg_names; int num_regs; + unsigned int double_buffer : 1; }; /** diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h index 9c857dd1ad9b..15a391a4650e 100644 --- a/drivers/staging/media/hantro/hantro_g2_regs.h +++ b/drivers/staging/media/hantro/hantro_g2_regs.h @@ -270,6 +270,7 @@ #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) +#define g2_double_buffer_e G2_DEC_REG(58, 15, 0x1) #define g2_buswidth G2_DEC_REG(58, 8, 0x7) #define g2_max_burst G2_DEC_REG(58, 0, 0xff) diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c index e04242d10fa2..d4fc649a4da1 100644 --- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c @@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); + if (ctx->dev->variant->double_buffer) + hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1); config_output(ctx, dst, dec_params); From patchwork Mon Nov 22 18:46:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12632655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11D1AC433EF for ; Mon, 22 Nov 2021 18:47:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240475AbhKVSuf (ORCPT ); Mon, 22 Nov 2021 13:50:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240434AbhKVSu3 (ORCPT ); Mon, 22 Nov 2021 13:50:29 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33000C061758; Mon, 22 Nov 2021 10:47:17 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id o20so36756515eds.10; Mon, 22 Nov 2021 10:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nalJ8d2MHcM+R02RYF78HUSQhkR2zBWDAb5KHoAUJbI=; b=ehTgB1SFcsIS/zpqTAfU1uxVBIhZsYse0R68xNECBKXGQNb4+Du+yrI80J+1ynCcQg IIvtUy1h0NfAOg8NV9xQk56IZHDb0ia8u/Md0qsqg6oG1GErhSIXHj8/GTyc3EjKKZb0 D9ZPb1kOqayx1Y3muaJdxetbYbQeuJXImtvhLvBaUH3yxtlwgpNHCidCcZWjh7OjGUQ+ I67Wl1ikL24VgPTykZ5xlSYVuH+BHLAun5paSG3E/UgK0HBjpC9rEtsZLZA8q4UZJLuA lGbdsjJagzVcrYpTZORdNu2QDwjeNbTzZqfoIhM6cOvbyPH4PJ1tDVbZ4BzZtojgYJFK 3bnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nalJ8d2MHcM+R02RYF78HUSQhkR2zBWDAb5KHoAUJbI=; b=UaP25aIsxyzdSNura8Fs/7PoCr2CsLKWT6dk9pmZFDNSr3DD+b3ld3nmtf4vtQ/mJK HTmXbHD0tNFweBPcMJzWgT6G5stFwU19AHZF505VMD7AVly5OWNuIvxUB8bibw8XVrwK ZsOLuNnKnOrSWDykw3QLVL+tYTPKnR4e6w6HedKlvek+56OXyeL2fBtWVzKsHHoywyLT Xp3q/Dy3pXmXRPZl/9kayWpTGmkQ9esgAoJ9fL+ESYI5LIUPK1njZxI65Ol4qAg2+lO3 8WDok9xjvVB46b0Ir3ZC1VWsorNAq+z8UvyCTLbCLoIDtUanC/13j2e/Y5upcvlQ84Lc 8aAQ== X-Gm-Message-State: AOAM533WT+aSlGRWrR37ffy6H9FpHalVNIhdnxS5NzEE/UHXqZpLCBYO IRMKAcfandDXYmX7tgH2EQcCMCuS2+RkOw== X-Google-Smtp-Source: ABdhPJxUspiLtrBWt9/CmjP/cHudxPIUfGgCgiFz7MOWIPuNUq6LVwx0b57KhKoPKJGjSKLRopSrOA== X-Received: by 2002:aa7:d512:: with SMTP id y18mr67118503edq.163.1637606835709; Mon, 22 Nov 2021 10:47:15 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:15 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 3/7] media: hantro: vp9: add support for legacy register set Date: Mon, 22 Nov 2021 19:46:58 +0100 Message-Id: <20211122184702.768341-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some older G2 cores uses slightly different register set for HEVC and VP9. Since vast majority of registers and logic is the same, it doesn't make sense to introduce another drivers. Add legacy_regs quirk and implement only VP9 changes for now. HEVC changes will be introduced later, if needed. Signed-off-by: Jernej Skrabec --- drivers/staging/media/hantro/hantro.h | 2 + drivers/staging/media/hantro/hantro_g2_regs.h | 19 +++++ .../staging/media/hantro/hantro_g2_vp9_dec.c | 74 ++++++++++++++----- 3 files changed, 78 insertions(+), 17 deletions(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index d03824fa3222..83ed25d9657b 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -74,6 +74,7 @@ struct hantro_irq { * @reg_names: array of register range names * @num_regs: number of register range names in the array * @double_buffer: core needs double buffering + * @legacy_regs: core uses legacy register set */ struct hantro_variant { unsigned int enc_offset; @@ -96,6 +97,7 @@ struct hantro_variant { const char * const *reg_names; int num_regs; unsigned int double_buffer : 1; + unsigned int legacy_regs : 1; }; /** diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h index 15a391a4650e..d7c2ff05208e 100644 --- a/drivers/staging/media/hantro/hantro_g2_regs.h +++ b/drivers/staging/media/hantro/hantro_g2_regs.h @@ -37,6 +37,13 @@ #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) +/* used on older variants */ +#define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f) +#define g2_pic_swap G2_DEC_REG(2, 22, 0x1f) +#define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f) +#define g2_tab0_swap G2_DEC_REG(2, 12, 0x1f) +#define g2_tab1_swap G2_DEC_REG(2, 7, 0x1f) +#define g2_tab2_swap G2_DEC_REG(2, 2, 0x1f) #define g2_mode G2_DEC_REG(3, 27, 0x1f) #define g2_compress_swap G2_DEC_REG(3, 20, 0xf) @@ -45,6 +52,8 @@ #define g2_out_dis G2_DEC_REG(3, 15, 0x1) #define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1) #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1) +#define g2_tab3_swap G2_DEC_REG(3, 7, 0x1f) +#define g2_rscan_swap G2_DEC_REG(3, 2, 0x1f) #define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff) #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) @@ -58,6 +67,7 @@ #define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1) #define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f) #define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1) +#define g2_pix_shift G2_DEC_REG(5, 0, 0xf) #define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff) @@ -80,6 +90,8 @@ #define g2_const_intra_e G2_DEC_REG(8, 31, 0x1) #define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1) +#define g2_bit_depth_y G2_DEC_REG(8, 21, 0xf) +#define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf) #define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1) #define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf) #define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf) @@ -87,6 +99,9 @@ #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) #define g2_output_format G2_DEC_REG(8, 0, 0x7) +/* used on older variants */ +#define g2_rs_out_bit_depth G2_DEC_REG(8, 4, 0xf) +#define g2_pp_pix_shift G2_DEC_REG(8, 0, 0xf) #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) @@ -98,6 +113,10 @@ #define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f) #define g2_tile_e G2_DEC_REG(10, 1, 0x1) #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) +/* used on older variants */ +#define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f) +#define g2_num_tile_cols_old G2_DEC_REG(10, 20, 0x1f) +#define g2_num_tile_rows_old G2_DEC_REG(10, 15, 0x1f) #define vp9_transform_mode G2_DEC_REG(11, 27, 0x7) #define vp9_filt_sharpness G2_DEC_REG(11, 21, 0x7) diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c index d4fc649a4da1..5aac32700cd0 100644 --- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c @@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx, dma_addr_t luma_addr, chroma_addr, mv_addr; hantro_reg_write(ctx->dev, &g2_out_dis, 0); - hantro_reg_write(ctx->dev, &g2_output_format, 0); + if (!ctx->dev->variant->legacy_regs) + hantro_reg_write(ctx->dev, &g2_output_format, 0); luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); @@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx, struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; dma_addr_t addr; unsigned short *tile_mem; + unsigned int rows, cols; addr = misc->dma + vp9_ctx->tile_info_offset; hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); @@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx, fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); + cols = tile_c; + rows = tile_r; hantro_reg_write(ctx->dev, &g2_tile_e, 1); - hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); - hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); - } else { tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); + cols = 1; + rows = 1; hantro_reg_write(ctx->dev, &g2_tile_e, 0); - hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); - hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); + } + + if (ctx->dev->variant->legacy_regs) { + hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols); + hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows); + } else { + hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols); + hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows); } /* provide aux buffers even if no tiles are used */ @@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco static void config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) { - hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); - hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); + if (ctx->dev->variant->legacy_regs) { + u8 pp_shift = 0; + + hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); + hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); + hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth); + + if (dec_params->bit_depth > 8) + pp_shift = 16 - dec_params->bit_depth; + + hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); + hantro_reg_write(ctx->dev, &g2_pix_shift, 0); + } else { + hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); + hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); + } } static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) @@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para + dec_params->compressed_header_size; stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); - hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); tmp_addr = stream_base + headres_size; + if (ctx->dev->variant->legacy_regs) + hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf)); + else + hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); + start_bit = (tmp_addr & 0xf) * 8; hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); @@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para src_len += start_bit / 8 - headres_size; hantro_reg_write(ctx->dev, &g2_stream_len, src_len); - tmp_addr &= ~0xf; - hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); - src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); - hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); + if (!ctx->dev->variant->legacy_regs) { + tmp_addr &= ~0xf; + hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); + src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); + hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); + } } static void @@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p /* configure basic registers */ hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); - hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); - hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); - hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); + if (!ctx->dev->variant->legacy_regs) { + hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); + hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); + } else { + hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f); + hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10); + hantro_reg_write(ctx->dev, &g2_tab0_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_tab1_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_tab2_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_tab3_swap, 0x10); + hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10); + } hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); hantro_reg_write(ctx->dev, &g2_max_burst, 16); hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); - hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); From patchwork Mon Nov 22 18:46:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12632665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31132C433EF for ; Mon, 22 Nov 2021 18:47:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240480AbhKVSun (ORCPT ); Mon, 22 Nov 2021 13:50:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239444AbhKVSu3 (ORCPT ); Mon, 22 Nov 2021 13:50:29 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C008C061759; 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:16 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 4/7] media: hantro: move postproc enablement for old cores Date: Mon, 22 Nov 2021 19:46:59 +0100 Message-Id: <20211122184702.768341-5-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Older G2 cores, like that in Allwinner H6, seem to have issue with latching postproc register values if this is first thing done in job. Moving that to the end solves the issue. Signed-off-by: Jernej Skrabec Reviewed-by: Andrzej Pietrasiewicz --- drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index 8c3de31f51b3..530994ab3024 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx) v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, &ctx->ctrl_handler); - if (!ctx->is_encoder) { + if (!ctx->is_encoder && !ctx->dev->variant->legacy_regs) { if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) hantro_postproc_enable(ctx); else @@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx) { struct vb2_v4l2_buffer *src_buf; + if (ctx->dev->variant->legacy_regs && !ctx->is_encoder) { + if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) + hantro_postproc_enable(ctx); + else + hantro_postproc_disable(ctx); + } + src_buf = hantro_get_src_buf(ctx); v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, &ctx->ctrl_handler); From patchwork Mon Nov 22 18:47:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12632661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 363A5C433F5 for ; Mon, 22 Nov 2021 18:47:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240496AbhKVSuk (ORCPT ); Mon, 22 Nov 2021 13:50:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240440AbhKVSu3 (ORCPT ); Mon, 22 Nov 2021 13:50:29 -0500 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B911AC06175B; Mon, 22 Nov 2021 10:47:19 -0800 (PST) Received: by mail-ed1-x529.google.com with SMTP id y13so81051382edd.13; Mon, 22 Nov 2021 10:47:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A4ae5Bs5ryByKDn+40799WBBmSQ5YSDOpHEJ7DwRPhk=; b=aQKe1zew8KzTyZPDYHDfRldGju4RXm6N/NULLgQUkFXJmsrVQcqZvRgy/13a3L9JIV +7Q7KC3Wa8f3eXxuQrDQUNPOQtNvQjxp9QKilSv/J1dM0yAIsN4gT3ZTAsu2bxTTdi5m psPbelagUacq1NI/ChW2igDsMQuEk3iteOO7wIkiFodt3Yi6pO1IOMCG9KpnkCg89PpE KPqvtXM0Ub6Kkd94Z3TenRNYGALPQXl3o36mHSCl3s7L2w0CySaePfM1Ut4f0oaIqZbV /8D1j/4jsU3CU8YyXvM3p8zrHK8veTHYEfx4AX22xhL+Baf4ZA0DihRiIK7TvInBUUAD KoVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A4ae5Bs5ryByKDn+40799WBBmSQ5YSDOpHEJ7DwRPhk=; b=KD7A7fCV1FtFwQlvuHigtJqbLhVz4l+JCs6uatVg0JF21N+VYphgbnmWs78qd8NWQh iNpnDwcb8/VNhL7crHmA65t6msAB8DhUcpT0zRTinX7yeUe+0b/scdm1usVa8Q8qdryV usHADZzMMfgeoVdmvbzznVPsvoH1yWMhYiwKf3AUAJHUSVAG8XxuITyFR8Gn0YtHph7n luNaVNgguRIz6SmV+u9Qk1S4Qk2ggNadWGRf+rP7x7e9/LXFx7QG7EWHk8url8/Jrau4 Pwl+bBdJzF9948ZgTJswSWOWubjsRH3CEFfJdO/qrsy71ccWVa52yauvTeSTuOfiG+li r9/w== X-Gm-Message-State: AOAM530julLzdkPNE/Y42HTRdCxOB8XTiY8F8gIU963vzoXscWeH7k43 XOqgbq+3XPizVv6UVfT/0NJE/1FqU8XO2w== X-Google-Smtp-Source: ABdhPJw234qk+H8u1V4KKQN7BY00PJiFvcfrfhoLFVaBXHGpDNuMEOKtFIDgZuJomIdStFViYyWcuQ== X-Received: by 2002:a05:6402:169a:: with SMTP id a26mr69251064edv.292.1637606838118; Mon, 22 Nov 2021 10:47:18 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:17 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 5/7] media: dt-bindings: allwinner: document H6 Hantro G2 binding Date: Mon, 22 Nov 2021 19:47:00 +0100 Message-Id: <20211122184702.768341-6-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Allwinner H6 contains older Hantro G2 core, primarly used for VP9 video decoding. It's unclear for now if HEVC is also supported. Describe it's binding. Signed-off-by: Jernej Skrabec --- .../media/allwinner,sun50i-h6-vpu-g2.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml diff --git a/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml new file mode 100644 index 000000000000..24d7bf21499e --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun50i-h6-vpu-g2.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Hantro G2 VPU codec implemented on Allwinner H6 SoC + +maintainers: + - Jernej Skrabec + +description: + Hantro G2 video decode accelerator present on Allwinner H6 SoC. + +properties: + compatible: + const: allwinner,sun50i-h6-vpu-g2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + +... 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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:19 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 6/7] media: hantro: Add support for Allwinner H6 Date: Mon, 22 Nov 2021 19:47:01 +0100 Message-Id: <20211122184702.768341-7-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Allwinner H6 has a Hantro G2 core used for VP9 decoding. It's not clear at this time if HEVC is also supported or not. Signed-off-by: Jernej Skrabec --- drivers/staging/media/hantro/Kconfig | 10 +- drivers/staging/media/hantro/Makefile | 3 + drivers/staging/media/hantro/hantro_drv.c | 3 + drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/sunxi_vpu_hw.c | 104 ++++++++++++++++++++ 5 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/hantro/sunxi_vpu_hw.c diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig index 00a57d88c92e..3c5d833322c8 100644 --- a/drivers/staging/media/hantro/Kconfig +++ b/drivers/staging/media/hantro/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST depends on VIDEO_DEV && VIDEO_V4L2 select MEDIA_CONTROLLER select MEDIA_CONTROLLER_REQUEST_API @@ -40,3 +40,11 @@ config VIDEO_HANTRO_ROCKCHIP default y help Enable support for RK3288, RK3328, and RK3399 SoCs. + +config VIDEO_HANTRO_SUNXI + bool "Hantro VPU Allwinner support" + depends on VIDEO_HANTRO + depends on ARCH_SUNXI || COMPILE_TEST + default y + help + Enable support for H6 SoC. diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 28af0a1ee4bf..ebd5ede7bef7 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -33,3 +33,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ rockchip_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ + sunxi_vpu_hw.o diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index 530994ab3024..54f34644ecdf 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -620,6 +620,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_SUNXI + { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index dbe51303724b..0676989b986b 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -308,6 +308,7 @@ extern const struct hantro_variant rk3288_vpu_variant; extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3399_vpu_variant; extern const struct hantro_variant sama5d4_vdec_variant; +extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/staging/media/hantro/sunxi_vpu_hw.c b/drivers/staging/media/hantro/sunxi_vpu_hw.c new file mode 100644 index 000000000000..05e964dc0499 --- /dev/null +++ b/drivers/staging/media/hantro/sunxi_vpu_hw.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner Hantro G2 VPU codec driver + * + * Copyright (C) 2021 Jernej Skrabec + */ + +#include + +#include "hantro.h" +#include "hantro_g2_regs.h" + +static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .postprocessed = true, + }, +}; + +static const struct hantro_fmt sunxi_vpu_dec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12_4L4, + .codec_mode = HANTRO_MODE_NONE, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, + .codec_mode = HANTRO_MODE_VP9_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 3840, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 2160, + .step_height = MB_DIM, + }, + }, +}; + +static irqreturn_t sunxi_vpu_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vdpu_read(vpu, G2_REG_INTERRUPT); + state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vdpu_write(vpu, 0, G2_REG_INTERRUPT); + vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static int sunxi_vpu_hw_init(struct hantro_dev *vpu) +{ + clk_set_rate(vpu->clocks[0].clk, 300000000); + + return 0; +} + +static void sunxi_vpu_reset(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + + reset_control_reset(vpu->resets); +} + +static const struct hantro_codec_ops sunxi_vpu_codec_ops[] = { + [HANTRO_MODE_VP9_DEC] = { + .run = hantro_g2_vp9_dec_run, + .done = hantro_g2_vp9_dec_done, + .reset = sunxi_vpu_reset, + .init = hantro_vp9_dec_init, + .exit = hantro_vp9_dec_exit, + }, +}; + +static const struct hantro_irq sunxi_irqs[] = { + { NULL, sunxi_vpu_irq }, +}; + +static const char * const sunxi_clk_names[] = { "mod", "bus" }; + +const struct hantro_variant sunxi_vpu_variant = { + .dec_fmts = sunxi_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(sunxi_vpu_dec_fmts), + .postproc_fmts = sunxi_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(sunxi_vpu_postproc_fmts), + .postproc_ops = &hantro_g2_postproc_ops, + .codec = HANTRO_VP9_DECODER, + .codec_ops = sunxi_vpu_codec_ops, + .init = sunxi_vpu_hw_init, + .irqs = sunxi_irqs, + .num_irqs = ARRAY_SIZE(sunxi_irqs), + .clk_names = sunxi_clk_names, + .num_clocks = ARRAY_SIZE(sunxi_clk_names), + .double_buffer = 1, + .legacy_regs = 1, +}; From patchwork Mon Nov 22 18:47:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 12632659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5B46C4332F for ; Mon, 22 Nov 2021 18:47:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240488AbhKVSuj (ORCPT ); Mon, 22 Nov 2021 13:50:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240442AbhKVSu3 (ORCPT ); Mon, 22 Nov 2021 13:50:29 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26279C06175D; Mon, 22 Nov 2021 10:47:22 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id r11so81199452edd.9; Mon, 22 Nov 2021 10:47:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OrAz2qSS0v6VrYhP03ydDVHSa28f05qdX2rEWeofBjI=; b=aBwbTm8os5gysOh9BjYaJ/KuTUKCj4tXn/KHFS6T5lt1KoTatn8M9t0R2mpFXh+Qzl AvxgkKXym1AXPSo+sKCLQ3UsO2JpJM41A8QwTZ5/EyTSXp3Y4jYQ5x05xaJZvqTO+gcM ifWoqay6i2F4ozO7jdpQoPMP41qsfmFfIGvmL52JNhlJLQKMejXeAM1o3C0KFxpByBgQ M4Mt+Fq4OhK6GkQ+TaJkGO54CRtZ9zo+Pq71HtYX/8paiwt+MogdOkxQ7o9P/c+cGvO0 V6V3/HSuVa7Yw8+xjpHCwKbk6gwffex9wM8peWGyzt4ycSCxuanD2j68W65bFzNgNd7v GzYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OrAz2qSS0v6VrYhP03ydDVHSa28f05qdX2rEWeofBjI=; b=KqTbbXd0BnC+R4GEizYHJpUea1+Ri0W+z82u+xQYXBB42Md2XQsNH90AKZ2vyNPfKX +dUCJQ+5rqtXgv/cEDRu5Ix6ceru3Vsy/ZW/mD+7I2vy7gsQxi7OUXoIzrSNcdTL99OO QEXP4u2lqtjmPWShSZmZdA0EvuI2dFkAGk/vY0BoeyuOCrZuTa60j4rl2c59KQbN4N5G TIfdof9eeBgvJv63QllbFkNYLmYj182q3pSxCw5gHibNs5i8zQV7uz4Qxyt2RSnvDyph uNVzjfBmFzGu8hCud1tJle9BTu5MWNSUIdtL93X59pLgQcbZFrbWZDU8nLUI+Jehs9lN bBKg== X-Gm-Message-State: AOAM533FlQ8ahQ7T50yl1zSB6WFZDZzsc1LWV8ruc0woW0silj6jtSRz K+/tXRVtfYV1qNkXjFBLio9BHOYA48BaIA== X-Google-Smtp-Source: ABdhPJzTkCP49CfK8OCN7Yj69H529JSNBRlwwEGGRuoxwaPQq1w+6+n7Bo+zSmFqF8zimlUpwdtfmg== X-Received: by 2002:a05:6402:5194:: with SMTP id q20mr58077323edd.250.1637606840774; Mon, 22 Nov 2021 10:47:20 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id h10sm4512312edr.95.2021.11.22.10.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Nov 2021 10:47:20 -0800 (PST) From: Jernej Skrabec To: linux-media@vger.kernel.org Cc: ezequiel@vanguardiasur.com.ar, nicolas.dufresne@collabora.com, mchehab@kernel.org, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, p.zabel@pengutronix.de, andrzej.p@collabora.com, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Jernej Skrabec Subject: [PATCH 7/7] arm64: dts: allwinner: h6: Add Hantro G2 node Date: Mon, 22 Nov 2021 19:47:02 +0100 Message-Id: <20211122184702.768341-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211122184702.768341-1-jernej.skrabec@gmail.com> References: <20211122184702.768341-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 4c4547f7d0c7..878061e75098 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -153,6 +153,15 @@ mixer0_out_tcon_top_mixer0: endpoint { }; }; + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + video-codec@1c0e000 { compatible = "allwinner,sun50i-h6-video-engine"; reg = <0x01c0e000 0x2000>;