From patchwork Tue Dec 18 18:32:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736143 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 70F9B14E2 for ; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61FDE2ACDA for ; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 558192AD9F; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 05C072AD66 for ; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727767AbeLRScu (ORCPT ); Tue, 18 Dec 2018 13:32:50 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41852 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727479AbeLRSct (ORCPT ); Tue, 18 Dec 2018 13:32:49 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B13DB6095E; Tue, 18 Dec 2018 18:32:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157968; bh=IKifwKjkPGN+iMabdaykxzQB6k0XEHLfxMrwblThn4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=btSkN4oAdgvwCTaAnHAuQOBQzQt/aMfayaat76dwtpEf7GIQ37YEKSC2aYUjMG65h tSAUm2Z1eSuXELlNQjKZ1jO+Q6IPeXf3jtnZQMqWwH2ksUAkXnaiNp/mQUVZpK3oH6 bj9Ba7SijH+1BZVjH37vuhBRiyBar/kMv2HfRCqk= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4B3F860593; Tue, 18 Dec 2018 18:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157967; bh=IKifwKjkPGN+iMabdaykxzQB6k0XEHLfxMrwblThn4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bIfktvCarwzGz4GclRgWBxdPJUprKRYOtAuyivu2dDtxx55B3x4HERwEhqbah0XnH IGolUJcpIYSGBsZPVPIBAvmVe4jzP8Mp/VUDOXKCA0kfYX4iEob5OIiz3vB216cJS/ 4afuPiE8ANyL8XE3ufmVmCm7UF0+8zeQ57Cr6h00= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4B3F860593 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name Date: Tue, 18 Dec 2018 11:32:36 -0700 Message-Id: <20181218183241.12830-2-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Every GPU core only has one interrupt so there isn't any value in looking up the interrupt by name. Remove the name (which is legacy anyway) and use platform_get_irq() instead. Signed-off-by: Jordan Crouse Reviewed-by: Douglas Anderson --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 93d70f4a2154..bfeea50fca8a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -713,7 +713,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->rev = config->rev; adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; - adreno_gpu_config.irqname = "kgsl_3d0_irq"; adreno_gpu_config.va_start = SZ_16M; adreno_gpu_config.va_end = 0xffffffff; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 11aac8337066..f9de09d14344 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -868,7 +868,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, } /* Get Interrupt: */ - gpu->irq = platform_get_irq_byname(pdev, config->irqname); + gpu->irq = platform_get_irq(pdev, 0); if (gpu->irq < 0) { ret = gpu->irq; dev_err(drm->dev, "failed to get irq: %d\n", ret); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index f82bac086666..fc4040e24a6b 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -31,7 +31,6 @@ struct msm_gpu_state; struct msm_gpu_config { const char *ioname; - const char *irqname; uint64_t va_start; uint64_t va_end; unsigned int nr_rings; From patchwork Tue Dec 18 18:32:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C3CB13B5 for ; Tue, 18 Dec 2018 18:32:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C5862ACDA for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 2/6] drm/msm: drop interrupt-names Date: Tue, 18 Dec 2018 11:32:37 -0700 Message-Id: <20181218183241.12830-3-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/gpu.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe09bb..4ad5e70e5c3e 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -25,7 +25,6 @@ Example: reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; - interrupt-names = "kgsl_3d0_irq"; clock-names = "core", "iface", From patchwork Tue Dec 18 18:32:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736151 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0B5014E2 for ; Tue, 18 Dec 2018 18:32:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B11672ACDA for ; Tue, 18 Dec 2018 18:32:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4EC22AD9C; Tue, 18 Dec 2018 18:32:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B3702ACDA for ; Tue, 18 Dec 2018 18:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727768AbeLRScx (ORCPT ); Tue, 18 Dec 2018 13:32:53 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42146 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbeLRScx (ORCPT ); Tue, 18 Dec 2018 13:32:53 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6BBA160A00; Tue, 18 Dec 2018 18:32:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157972; bh=gt3J4qcxB1NPTcmug6XE2wr/P3ia2VK4eblTfEVxR8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nzxK8FpGCJKl+fec3mAZv+XuAYVC048OKhsrOz5FWVKTWhuq5RBOpHhaYIKeKs0AV KkqZOq63LG8x6rCkzaEIg2UK4eAbF5hfgKN+gwvpIMuZoP6r35EkR2hn+UoAba8DIj yciolc9j6kADT/UVmLcahWW9Rk2i34FrBHDMRBAM= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B925460988; Tue, 18 Dec 2018 18:32:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157969; bh=gt3J4qcxB1NPTcmug6XE2wr/P3ia2VK4eblTfEVxR8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hZgW6HDUzD08IG8R4h1iWzPaZkRM0wWqHx3TirirEJ+RQhW6Bb4lQKA1n9rV6As9I TKkTB8M7PpRkcA3cfFYHST0xZQbpVMS6l0Pl7fphyfDL+pAvlpwS+amBPnLfi0n/MO auJM2/zB9cqEDpdpwJyj2cwbJkmr7euOxnUSXDI4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B925460988 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node Date: Tue, 18 Dec 2018 11:32:38 -0700 Message-Id: <20181218183241.12830-4-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver. Signed-off-by: Jordan Crouse --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf427610..0a9862729c80 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1186,7 +1186,6 @@ reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; - interrupt-names = "kgsl_3d0_irq"; clock-names = "core_clk", "iface_clk", From patchwork Tue Dec 18 18:32:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736157 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FCCA13B5 for ; Tue, 18 Dec 2018 18:32:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DE962ACDA for ; Tue, 18 Dec 2018 18:32:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21B442ACB4; Tue, 18 Dec 2018 18:32:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C76EF2ACB4 for ; Tue, 18 Dec 2018 18:32:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbeLRScz (ORCPT ); Tue, 18 Dec 2018 13:32:55 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42246 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbeLRScy (ORCPT ); Tue, 18 Dec 2018 13:32:54 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 11491609FD; Tue, 18 Dec 2018 18:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157974; bh=FKtdT+t1O5qh2QaBJ0LIE8c5gDcqKJMfSwN6B5oWbl0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Rk7a3aZQp2t6L1LRnEAba0LHDh/to6J1G54iGFtLkq5ErqE5MJzON6NcbNxuVXr9b T+mJNZADHx02L/CigRuRcsbuM8j40KFRr4mDagPQ0rMth31+1DnOrcgA4jXy6GDXAL zpt/Qo3FU8Ds8i6EeecO4QkA9kxq31ask63eIOTM= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2C293609D4; Tue, 18 Dec 2018 18:32:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157971; bh=FKtdT+t1O5qh2QaBJ0LIE8c5gDcqKJMfSwN6B5oWbl0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IwAawjvl7ewMQws8Jfx1FMcUKr+MlH9moAfqS1JVM1GIytJP2lH1HkahnmLITfdNs hvDeQZjyx0jkhUKhvI5HjSLNOwGnx/8sEPgWGWaLCR8gaaZtBE2+gZyFkgT7oNNd2F NTrKJq78XBtG+aQNFIyHmp5/AYXDqlJxy3suPLZI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2C293609D4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU Date: Tue, 18 Dec 2018 11:32:39 -0700 Message-Id: <20181218183241.12830-5-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver. Signed-off-by: Jordan Crouse Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c5348c3da5a2..846de1043e4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -880,7 +880,6 @@ reg = <0x01c00000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; - interrupt-names = "kgsl_3d0_irq"; clock-names = "core", "iface", From patchwork Tue Dec 18 18:32:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736167 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF44513B5 for ; Tue, 18 Dec 2018 18:33:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0AD72ACB4 for ; Tue, 18 Dec 2018 18:33:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B49402AD8B; Tue, 18 Dec 2018 18:33:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48A122ACB4 for ; Tue, 18 Dec 2018 18:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727777AbeLRSc7 (ORCPT ); Tue, 18 Dec 2018 13:32:59 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42476 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbeLRSc7 (ORCPT ); Tue, 18 Dec 2018 13:32:59 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7FE5C60A0B; Tue, 18 Dec 2018 18:32:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157977; bh=2xZrjzhUxRf/8UD41Jynjt7ClDDaGXK825tdD93w/2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FF4NEpDFyemRF23nPS97Up8IkjpKUwm3tKCRMp+Yp3kUUkYinw4qlj3loVoh25i/5 ji5D/id/ziim/h7qXFb6v7HU61lbnm3ruklm9/qKKqaQb6/AQVNw2NUfvqyIm6V2Nw M8m7HgWopz3WUJkCA1HJL/jTN8unIwbyFdswk5zY= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 82A96609C4; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157972; bh=2xZrjzhUxRf/8UD41Jynjt7ClDDaGXK825tdD93w/2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SsldPM2I5M/cTFAYDt2JzM60lI3tCVzXbH0BLr7aFGde6iNGthabeW3xyuZLrhopU t5uwp7brLMBTdZmcG7FWI2CWVPFkMI8QIqjFm2GcRPBdLr8mku3c0i9cTt7pyl4OEi OuWUbR2ra75UpiL2v/jxj2BNqSx91Jm6Q64BzNbE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 82A96609C4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Date: Tue, 18 Dec 2018 11:32:40 -0700 Message-Id: <20181218183241.12830-6-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring --- v7: Updated the GMU compatible string and clarified details about when clocks can be optional on the GPU .../devicetree/bindings/display/msm/gmu.txt | 59 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 42 ++++++++++++- 2 files changed, 98 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt new file mode 100644 index 000000000000..59e6865898f2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -0,0 +1,59 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" + for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" + Note that you need to list the less specific "qcom,adreno-gmu" + for generic matches and the more specific identifier to identify + the specific device. +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" + * "gmu_pdc_seg" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 4ad5e70e5c3e..9c89f4fdb8ca 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -8,14 +8,23 @@ Required properties: with the chip-id. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. -- clocks: device clocks +- clocks: device clocks (if applicable) See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: +- clock-names: the following clocks are required by a3xx, a4xx and a5xx + cores: * "core" * "iface" * "mem_iface" + For GMU attached devices the GPU clocks are not used and are not required. The + following devices should not list clocks: + - qcom,adreno-630.2 +- iommus: optional phandle to an adreno iommu instance +- operating-points-v2: optional phandle to the OPP operating points +- qcom,gmu: For GMU attached devices a phandle to the GMU device that will + control the power for the GPU. Applicable targets: + - qcom,adreno-630.2 -Example: +Example 3xx/4xx/a5xx: / { ... @@ -35,3 +44,30 @@ Example: <&mmcc MMSS_IMEM_AHB_CLK>; }; }; + +Example a6xx (with GMU): + +/ { + ... + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + }; +}; From patchwork Tue Dec 18 18:32:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB5846C2 for ; Tue, 18 Dec 2018 18:33:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ACE022AD9C for ; Tue, 18 Dec 2018 18:33:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A00FB2AD8B; Tue, 18 Dec 2018 18:33:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C84D2ACDA for ; Tue, 18 Dec 2018 18:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726649AbeLRSdA (ORCPT ); Tue, 18 Dec 2018 13:33:00 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42540 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727486AbeLRSc7 (ORCPT ); Tue, 18 Dec 2018 13:32:59 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1E09360A9B; Tue, 18 Dec 2018 18:32:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157978; bh=nFY1qTEU5oJHMPFCaUE8wFs6vqjJqe+jQm8wSw6Oq+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NVMQhoGwojtKrOD+4kt6S5u/jVBokVmwoiPZwPumwqnIkUSTwQW+bA9Iedk8uXdx4 2TGjpPI5J3WLX4iBqRNYIdmpQzYiNcShTbcpyaQAJGPoMgvtlAQnwT2eqo2M2551BG 1OGlqOlhj8dy008f3t5quqFJx6r2Fg9j7s1E0ZGc= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BA583609C3; Tue, 18 Dec 2018 18:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157974; bh=nFY1qTEU5oJHMPFCaUE8wFs6vqjJqe+jQm8wSw6Oq+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X/lzBw/yUxnEFpasz4LYcKftpI319lZfeTlVdJwY0kyXDsr76m0CRQ/bHnJQyKXja Mr00yCHzYXvTc4vGCbHf+nkb8NxM6FccU4851Z1J9PoHUbxN3SBwBT6Oe+Pni2wWnJ ZU0W2myfKsGKBSVqFZLVPoXDWS/Lpb/xvmJqt29A= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BA583609C3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes Date: Tue, 18 Dec 2018 11:32:41 -0700 Message-Id: <20181218183241.12830-7-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- v7: Updated the GMU compatible string and removed interrupt-names arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 233a5898ebc2..4779014e4a05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1349,6 +1350,127 @@ }; }; + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = ; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = ; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = ; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = ; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = ; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = ; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = ; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0x5090000 0x9000>;