From patchwork Wed Nov 24 03:50:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 12635915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E39B9C43217 for ; Wed, 24 Nov 2021 03:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240896AbhKXDxf (ORCPT ); Tue, 23 Nov 2021 22:53:35 -0500 Received: from mail.loongson.cn ([114.242.206.163]:58056 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240891AbhKXDxd (ORCPT ); Tue, 23 Nov 2021 22:53:33 -0500 Received: from localhost.localdomain (unknown [111.9.175.10]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxeNJ3tp1hx9oAAA--.1299S3; Wed, 24 Nov 2021 11:50:21 +0800 (CST) From: Huang Pei To: netdev@vger.kernel.org, ambrosehua@gmail.com Cc: linux-arch@vger.kernel.org Subject: [PATCH 1/4] MIPS: rework local_t operation on MIPS64 Date: Wed, 24 Nov 2021 11:50:01 +0800 Message-Id: <20211124035004.7871-2-huangpei@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211124035004.7871-1-huangpei@loongson.cn> References: <20211124035004.7871-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxeNJ3tp1hx9oAAA--.1299S3 X-Coremail-Antispam: 1UD129KBjvJXoWxZr1ktrW5Ww4UArWrCFW7Arb_yoWrurWrpF srCan7KrWqvF4fA3Z7ZF4Svr13Wr4fGrWYkF1qvrWvy3W8t3W8ZrZ3KanYyrykZFZ8X3W8 XFW7ur15X3ZrA3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBFb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_Jrv_JF4l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv 6xkF7I0E14v26F4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S 6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxkIecxEwVAFwVW8GwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07brkucUUUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org +. use "daddu/dsubu" for long int on MIPS64 instead of "addu/subu" +. remove "asm/war.h" since R10000_LLSC_WAR became a config option +. clean up Suggested-by: "Maciej W. Rozycki" Signed-off-by: Huang Pei --- arch/mips/include/asm/asm.h | 18 ++++++++++ arch/mips/include/asm/local.h | 62 +++++++++-------------------------- 2 files changed, 33 insertions(+), 47 deletions(-) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 2f8ce94ebaaf..f3302b13d3e0 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -19,6 +19,7 @@ #include #include +#include #ifndef __VDSO__ /* @@ -211,6 +212,8 @@ symbol = value #define LONG_SUB sub #define LONG_SUBU subu #define LONG_L lw +#define LONG_LL ll +#define LONG_SC sc #define LONG_S sw #define LONG_SP swp #define LONG_SLL sll @@ -236,6 +239,8 @@ symbol = value #define LONG_SUB dsub #define LONG_SUBU dsubu #define LONG_L ld +#define LONG_LL lld +#define LONG_SC scd #define LONG_S sd #define LONG_SP sdp #define LONG_SLL dsll @@ -320,6 +325,19 @@ symbol = value #define SSNOP sll zero, zero, 1 +/* + * Using a branch-likely instruction to check the result of an sc instruction + * works around a bug present in R10000 CPUs prior to revision 3.0 that could + * cause ll-sc sequences to execute non-atomically. + */ +#ifdef CONFIG_WAR_R10000_LLSC +# define SC_BEQZ beqzl +#elif MIPS_ISA_REV >= 6 +# define SC_BEQZ beqzc +#else +# define SC_BEQZ beqz +#endif + #ifdef CONFIG_SGI_IP28 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ #include diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h index ecda7295ddcd..c1e109357110 100644 --- a/arch/mips/include/asm/local.h +++ b/arch/mips/include/asm/local.h @@ -7,7 +7,7 @@ #include #include #include -#include +#include typedef struct { @@ -31,34 +31,18 @@ static __inline__ long local_add_return(long i, local_t * l) { unsigned long result; - if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set arch=r4000 \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" - " .set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (kernel_uses_llsc) { + if (kernel_uses_llsc) { unsigned long temp; __asm__ __volatile__( " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " addu %0, %1, %3 \n" + __SYNC(full, loongson3_war) " \n" + "1:" __stringify(LONG_LL) " %1, %2 \n" + " "__stringify(LONG_ADDU) " %0, %1, %3 \n" + " "__stringify(LONG_SC) " %0, %2 \n" + " "__stringify(SC_BEQZ) " %0, 1b \n" + " "__stringify(LONG_ADDU) " %0, %1, %3 \n" " .set pop \n" : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) : "Ir" (i), "m" (l->a.counter) @@ -80,34 +64,18 @@ static __inline__ long local_sub_return(long i, local_t * l) { unsigned long result; - if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set arch=r4000 \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (kernel_uses_llsc) { + if (kernel_uses_llsc) { unsigned long temp; __asm__ __volatile__( " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" - __SYNC(full, loongson3_war) " \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " subu %0, %1, %3 \n" + __SYNC(full, loongson3_war) " \n" + "1:" __stringify(LONG_LL) " %1, %2 \n" + " "__stringify(LONG_SUBU) " %0, %1, %3 \n" + " "__stringify(LONG_SC) " %0, %2 \n" + " "__stringify(SC_BEQZ) " %0, 1b \n" + " "__stringify(LONG_SUBU) " %0, %1, %3 \n" " .set pop \n" : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) : "Ir" (i), "m" (l->a.counter) From patchwork Wed Nov 24 03:50:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 12635919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 461C0C43219 for ; Wed, 24 Nov 2021 03:50:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240903AbhKXDxg (ORCPT ); Tue, 23 Nov 2021 22:53:36 -0500 Received: from mail.loongson.cn ([114.242.206.163]:58064 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240875AbhKXDxe (ORCPT ); Tue, 23 Nov 2021 22:53:34 -0500 Received: from localhost.localdomain (unknown [111.9.175.10]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxeNJ3tp1hx9oAAA--.1299S4; Wed, 24 Nov 2021 11:50:23 +0800 (CST) From: Huang Pei To: netdev@vger.kernel.org, ambrosehua@gmail.com Cc: linux-arch@vger.kernel.org Subject: [PATCH 2/4] MIPS: tx39: fix tx39_flush_cache_page Date: Wed, 24 Nov 2021 11:50:02 +0800 Message-Id: <20211124035004.7871-3-huangpei@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211124035004.7871-1-huangpei@loongson.cn> References: <20211124035004.7871-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxeNJ3tp1hx9oAAA--.1299S4 X-Coremail-Antispam: 1UD129KBjvJXoW7Kr4kuFWUZr15CF4xWFy8Xwb_yoW8Gw1xp3 y2kan8J3y0g3WruFyfAw4qyr1Sg3srKFWIva17K34Y934YqF1UKrn3Krn0gF15ArZYyay7 uFWjyF15Zw4qv3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBFb7Iv0xC_KF4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUXwA2048vs2IY020Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv 6xkF7I0E14v26F4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S 6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxkIecxEwVAFwVW8GwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j4OJ5UUUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Indexed cache operation need KSEG0 address for safety and assume that no dcache alias nor high memory, since indexed cache instrcution CAN NOT handle cache alias Signed-off-by: Huang Pei --- arch/mips/mm/c-tx39.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 03dfbb40ec73..c7c3dbfe7756 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -170,6 +170,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page struct mm_struct *mm = vma->vm_mm; pmd_t *pmdp; pte_t *ptep; + unsigned long vaddr = phys_to_virt(pfn_to_phys(pfn)); /* * If ownes no valid ASID yet, cannot possibly have gotten @@ -207,11 +208,14 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page /* * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. + * + * Assuming that tx39 family do not support high memory, nor has + * dcache alias, vaddr can index dcache directly and correctly */ - if (cpu_has_dc_aliases || exec) - tx39_blast_dcache_page_indexed(page); - if (exec) - tx39_blast_icache_page_indexed(page); + if (exec) { + tx39_blast_dcache_page_indexed(vaddr); + tx39_blast_icache_page_indexed(vaddr); + } } static void local_tx39_flush_data_cache_page(void * addr) From patchwork Wed Nov 24 03:50:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 12635913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95DD7C433F5 for ; Wed, 24 Nov 2021 03:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240899AbhKXDxf (ORCPT ); Tue, 23 Nov 2021 22:53:35 -0500 Received: from mail.loongson.cn ([114.242.206.163]:58070 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240892AbhKXDxe (ORCPT ); Tue, 23 Nov 2021 22:53:34 -0500 Received: from localhost.localdomain (unknown [111.9.175.10]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxeNJ3tp1hx9oAAA--.1299S5; Wed, 24 Nov 2021 11:50:23 +0800 (CST) From: Huang Pei To: netdev@vger.kernel.org, ambrosehua@gmail.com Cc: linux-arch@vger.kernel.org Subject: [PATCH 3/4] MIPS: use 3-level pgtable for 64KB page size on MIPS_VA_BITS_48 Date: Wed, 24 Nov 2021 11:50:03 +0800 Message-Id: <20211124035004.7871-4-huangpei@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211124035004.7871-1-huangpei@loongson.cn> References: <20211124035004.7871-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxeNJ3tp1hx9oAAA--.1299S5 X-Coremail-Antispam: 1UD129KBjvdXoWrZFy7JF4DWryrGF15Ar45trb_yoWfCFb_JF 1UtrWfGr1rGrW8u34aqrWrtF1a93WUWryfCr12gr15u3yS9F13ta1UXa1DZr13Cayq9rWf XrWrAry3Cr4ayjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbfAYjsxI4VWkKwAYFVCjjxCrM7AC8VAFwI0_Xr0_Wr1l1xkIjI8I 6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7 IE14v26r1rM28IrcIa0xkI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CE w4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6x kF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_Cr1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c 02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE 4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc2xSY4AK67AK6r48MxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU5_8n5UUUUU== X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org It hangup when booting Loongson 3A1000 with BOTH CONFIG_PAGE_SIZE_64KB and CONFIG_MIPS_VA_BITS_48, that it turn out to use 2-level pgtable instead of 3-level. 64KB page size with 2-level pgtable only cover 42 bits VA, use 3-level pgtable to cover all 48 bits VA(55 bits) Fixes: 1e321fa917fb ("MIPS64: Support of at least 48 bits of SEGBITS) Signed-off-by: Huang Pei --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index de60ad190057..0215dc1529e9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3097,7 +3097,7 @@ config STACKTRACE_SUPPORT config PGTABLE_LEVELS int default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48 - default 3 if 64BIT && !PAGE_SIZE_64KB + default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48) default 2 config MIPS_AUTO_PFN_OFFSET From patchwork Wed Nov 24 03:50:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 12635917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C31BC4167B for ; Wed, 24 Nov 2021 03:50:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240905AbhKXDxh (ORCPT ); Tue, 23 Nov 2021 22:53:37 -0500 Received: from mail.loongson.cn ([114.242.206.163]:58092 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240893AbhKXDxf (ORCPT ); Tue, 23 Nov 2021 22:53:35 -0500 Received: from localhost.localdomain (unknown [111.9.175.10]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxeNJ3tp1hx9oAAA--.1299S6; Wed, 24 Nov 2021 11:50:24 +0800 (CST) From: Huang Pei To: netdev@vger.kernel.org, ambrosehua@gmail.com Cc: linux-arch@vger.kernel.org Subject: [PATCH 4/4] MIPS: loongson64: fix FTLB configuration Date: Wed, 24 Nov 2021 11:50:04 +0800 Message-Id: <20211124035004.7871-5-huangpei@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211124035004.7871-1-huangpei@loongson.cn> References: <20211124035004.7871-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxeNJ3tp1hx9oAAA--.1299S6 X-Coremail-Antispam: 1UD129KBjvJXoW7Gry8WFyDJF1UCrW8Kw4Durg_yoW8Jr17pr 1qya17Kr4UAFy2yayDJFZ5Wry3ZFyDWFZxWFW29rWYv3ZxZr1UXF97Xa13JrsrZryI93Wr Wa9agFW5KFs7Cr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBab7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUAVCq3wA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28C jxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI 8IcVCY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E 87Iv6xkF7I0E14v26F4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0V AKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1l Ox8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxkIecxEwVAFwVW8GwCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07b43ktUUUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Commit "da1bd29742b1" ("MIPS: Loongson64: Probe CPU features via CPUCFG") makes 'set_ftlb_enable' called under c->cputype unset, which leaves FTLB disabled on BOTH 3A2000 and 3A3000 Fixes: da1bd29742b1 ("MIPS: Loongson64: Probe CPU features via CPUCFG") Signed-off-by: Huang Pei --- arch/mips/kernel/cpu-probe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ac0e2cfc6d57..24a529c6c4be 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1734,8 +1734,6 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c) static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { - decode_configs(c); - /* All Loongson processors covered here define ExcCode 16 as GSExc. */ c->options |= MIPS_CPU_GSEXCEX; @@ -1796,6 +1794,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) panic("Unknown Loongson Processor ID!"); break; } + + decode_configs(c); } #else static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }