From patchwork Tue Dec 18 21:28:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 10736349 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF42E1399 for ; Tue, 18 Dec 2018 21:30:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF4432AF0E for ; Tue, 18 Dec 2018 21:30:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D16F22AF10; Tue, 18 Dec 2018 21:30:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 52A2B2AF11 for ; Tue, 18 Dec 2018 21:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=5gGSvybvobo+8SYYeIDI9jkIRdZMzwVnJcpv3gwWIKg=; b=D9LOboUAyvmUCyqx3GZLG4Bkvd drKysWsTn8BTthVhe6ZWkVdZl9vMhlbsdrWaPTU6tiaZutM/4jsON3X7DvlQvJ44fXddxXDmC1s0f 3Smh/N/7adVPBsSKfV2mh/b23nOSRVQGry6XEezdJ7SpwrO2WYjJ8SYNRQOfhdlhmq8Luz+lNDOz6 7wFeAc0BhidmZMs0knEaV4u66BkY0Wm8vuVdNdpny4Z11H/zQ+ouq7TNmUzzgk2BrH0opPAY05X8y BqX/NvEFBIapWHcByh++IRWGfl7nx0DqLjrJfapN61c/fg4VXxOG5/wV0m5vfaqsswiZOAd47ctPM gLop5ijA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZMwm-0003C4-D3; Tue, 18 Dec 2018 21:30:36 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZMvi-0000rW-8P for linux-amlogic@lists.infradead.org; Tue, 18 Dec 2018 21:29:39 +0000 Received: by mail-wm1-x341.google.com with SMTP id y185so8086556wmd.1 for ; Tue, 18 Dec 2018 13:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AThSIIFr1MNxei6GzfPPmaTqIlS3Gkxg7bofXJUPBLQ=; b=Xuuc6c3Am0E7BW1mAxndCishUpk7F/3ellKRyWJ60Hqb0Ilw8EspLunAVKiphs7Ilt rfYUSl/KTHJf1K8nYbJQsRT5yKW7+EpXirivoVidQ+KaybG+awYy6FtANxiJJzioXvxd yDqbD+dFdDgdbak1lon3SwCvI1hBGlX82lFWU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AThSIIFr1MNxei6GzfPPmaTqIlS3Gkxg7bofXJUPBLQ=; b=Pwf3KnkAi7RwatGoPNB0fas4ZJbCrwvFjEuJwhC9sIkDb04r2v1H7/jUW7Q+83sjOo r39jwtXkfNkBhO95cT+fwQ/WGS4NBpslZoQ2f8IAaH2GyMCPtyfHcW5NzSLk5BVsoj/h xGEXiBiBJjavq59YG7rf8ZVZG3S7cmJBZbamTjKludUB5+OHDEw1Nv33CJCpDPaIyDcB FKy9QjX2DaQlTgaV94gzC8zx5CpKjjcRnwij0gV8iMdaFvMVL1yVCwf/d0Ov2xLabpLw poLuhDKswnMbOAy06GmvODHjPIEHaHGYn8IVZUx7z8yjEcBIOylRJoZuVBa3eV/ulBjT ZCeA== X-Gm-Message-State: AA+aEWbHbOhGN7b68aZE6prXmXnQzVkgso0l17HkEu4aWoKW96cLNgmp gh7MwRBBPyyoCG7KjYfXQhLXJQ== X-Google-Smtp-Source: AFSGD/XlJFMb8pCOldKf4yp8Gv1pJSXtxZVgStptL9MrboBXq1sRY+Vndrz6294rueUwqD5NzS6udQ== X-Received: by 2002:a1c:f605:: with SMTP id w5mr4863537wmc.116.1545168558247; Tue, 18 Dec 2018 13:29:18 -0800 (PST) Received: from localhost.localdomain (105.50.92.92.rev.sfr.net. [92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:17 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Subject: [PATCH 06/25] clocksource/drivers/meson6_timer: Use register names from the datasheet Date: Tue, 18 Dec 2018 22:28:24 +0100 Message-Id: <20181218212844.30445-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_132930_685275_6B18D895 X-CRM114-Status: GOOD ( 15.20 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , Kevin Hilman , linux-kernel@vger.kernel.org, Carlo Caione , "open list:ARM/Amlogic Meson SoC support" , "moderated list:ARM/Amlogic Meson SoC support" MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Martin Blumenstingl This makes the driver use the names from S805 datasheet for the preprocessor #defines. This makes it easier to spot that the driver currently only supports Timer A (as clockevent with interrupt support) and Timer E (as clocksource without interrupts). Timer B, C and D (which are similar to Timer A) are currently not supported by the driver. While here, this also removes the internal "CED_ID" and "CSD_ID" defines which are used to identify the timer. These IDs are not described in the datasheet and thus make it harder to compare the code to what's written in the datasheet. Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 108 +++++++++++++++++------------ 1 file changed, 64 insertions(+), 44 deletions(-) diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 92f20991a937..23c7638e2bb3 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -10,6 +10,8 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include #include @@ -20,80 +22,96 @@ #include #include -#define CED_ID 0 -#define CSD_ID 4 - -#define TIMER_ISA_MUX 0 -#define TIMER_ISA_VAL(t) (((t) + 1) << 2) - -#define TIMER_INPUT_BIT(t) (2 * (t)) -#define TIMER_ENABLE_BIT(t) (16 + (t)) -#define TIMER_PERIODIC_BIT(t) (12 + (t)) - -#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID)) -#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID)) - -#define TIMER_CED_UNIT_1US 0 -#define TIMER_CSD_UNIT_1US 1 +#define MESON_ISA_TIMER_MUX 0x00 +#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) +#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) +#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) +#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) +#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) +#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) +#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) +#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4 +#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6) +#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4) +#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2) +#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0) +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3 + +#define MESON_ISA_TIMERA 0x04 +#define MESON_ISA_TIMERB 0x08 +#define MESON_ISA_TIMERC 0x0c +#define MESON_ISA_TIMERD 0x10 +#define MESON_ISA_TIMERE 0x14 static void __iomem *timer_base; static u64 notrace meson6_timer_sched_read(void) { - return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID)); + return (u64)readl(timer_base + MESON_ISA_TIMERE); } -static void meson6_clkevt_time_stop(unsigned char timer) +static void meson6_clkevt_time_stop(void) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); - writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } -static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay) +static void meson6_clkevt_time_setup(unsigned long delay) { - writel(delay, timer_base + TIMER_ISA_VAL(timer)); + writel(delay, timer_base + MESON_ISA_TIMERA); } -static void meson6_clkevt_time_start(unsigned char timer, bool periodic) +static void meson6_clkevt_time_start(bool periodic) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); if (periodic) - val |= TIMER_PERIODIC_BIT(timer); + val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; else - val &= ~TIMER_PERIODIC_BIT(timer); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; - writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } static int meson6_shutdown(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); return 0; } static int meson6_set_oneshot(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_start(false); return 0; } static int meson6_set_periodic(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, USEC_PER_SEC / HZ - 1); - meson6_clkevt_time_start(CED_ID, true); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1); + meson6_clkevt_time_start(true); return 0; } static int meson6_clkevt_next_event(unsigned long evt, struct clock_event_device *unused) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, evt); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(evt); + meson6_clkevt_time_start(false); return 0; } @@ -144,22 +162,24 @@ static int __init meson6_timer_init(struct device_node *node) } /* Set 1us for timer E */ - val = readl(timer_base + TIMER_ISA_MUX); - val &= ~TIMER_CSD_INPUT_MASK; - val |= TIMER_CSD_UNIT_1US << TIMER_INPUT_BIT(CSD_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val = readl(timer_base + MESON_ISA_TIMER_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC); - clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name, + clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name, 1000 * 1000, 300, 32, clocksource_mmio_readl_up); /* Timer A base 1us */ - val &= ~TIMER_CED_INPUT_MASK; - val |= TIMER_CED_UNIT_1US << TIMER_INPUT_BIT(CED_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); /* Stop the timer A */ - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); ret = setup_irq(irq, &meson6_timer_irq); if (ret) { From patchwork Tue Dec 18 21:28:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 10736351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38BF21399 for ; Tue, 18 Dec 2018 21:30:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 279B72AF06 for ; Tue, 18 Dec 2018 21:30:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24F372AF20; Tue, 18 Dec 2018 21:30:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B057C2AF1C for ; Tue, 18 Dec 2018 21:30:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ma5bAIidHSb/HRld8b+TCJyP9yx4yIxbav1QYkmIyZg=; b=S8T/aMvJuxFwuthMCnmyW/GpIn 6Tqgd8d07A5y7Lwj/zAZDcw2J+TvD80NZJcxE/qb0jt9G8q0yxjQ9oIR3N2t3ncwHvSPA+f+l61Bi T6NkPkK7PsFA46YYGD1KsF4LMnGObEhvCIXavvFtU80iUv4rC06cRMnB7c6i2NRPjnNHAx0YzJ2vW 0d+kzsVf663VJoodNPwIG0mMdb0s8M9DOmBIInCOrvZ0V3p/tL06Cy3B49g9ZhW5f5WxW6hoZxKu1 pOc4BdSYNDRZuHbahiWs+CbTbsyz24dxWFe2jpTInhLklnl7HHD71xb4fe3WSoOfjT8Lk/y3G5Sw1 CQSdum4w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZMwr-0003Gz-KQ; Tue, 18 Dec 2018 21:30:41 +0000 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZMvj-0000sS-Ly for linux-amlogic@lists.infradead.org; Tue, 18 Dec 2018 21:29:48 +0000 Received: by mail-wm1-x343.google.com with SMTP id m1so4098453wml.2 for ; Tue, 18 Dec 2018 13:29:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+kk49u2E8Mo1JNxE8BrR9oOARp9WmK1DmRN/2CO3j/8=; b=JT/ZsqfQLVVSX+jbMOMwvdmTraAUh2j/2iIoSl0jGXgA15MSLhzzoSfM9jCn+rNy9i k0FnfddkVZjRaa3CS8Q2P9eoYYMhlpkT6CslTRnZ7GLniqwBtx4ehL/B93ISFzEMf//6 fG7g3U/ReKJQHa6S/EMTgVhtGkPbKfd0r9bC4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+kk49u2E8Mo1JNxE8BrR9oOARp9WmK1DmRN/2CO3j/8=; b=jaZtzQCnnWqHdmWfnSTV1nLp/TxPh7MLbaHdVOWXrlYarUnNxhY/ScTCpSZEZbYr94 uYXNubchZO5VVP+BLUZ+FHttT2Nsh1LpGE02sdeMQnMPi2ZsRTMNb9hCcJxmWY1xCaIO tyefcw/71Hr1hBuvwmCE2ioy7vNtoOeKMiGty5UgVHZuKLN9+pDJYjcK/n9yDUJJ0AE5 oVWm1XhRwP+soq8HOYhCG/3pPs8Kv2aAge3uCex1pWkP02srqbk250neZ0syvNJ1RrKg GU55H7xSvHTfmEkJ+nnqjc8w/a0VIpqoimmNenBmC77hl0tZSHVfzWx+XFGbwUQdLZuF RJpg== X-Gm-Message-State: AA+aEWa2YJtUHOyhtgpTGMpqhAhPqFee9F2wsZVab57g5BLvzQitYfM5 sZnv80dDV6zHSrypxO8JDI2kgg== X-Google-Smtp-Source: AFSGD/XiEeq+vDeKGNZkt57dLzm/xXk4gUU9JTvpHHo4mRvG7y+KrZgN/UlfX6m1Ak8NNfX0sYi5hg== X-Received: by 2002:a1c:ae88:: with SMTP id x130mr4442834wme.91.1545168559808; Tue, 18 Dec 2018 13:29:19 -0800 (PST) Received: from localhost.localdomain (105.50.92.92.rev.sfr.net. [92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:19 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Subject: [PATCH 07/25] clocksource/drivers/meson6_timer: Implement the ARM delay timer Date: Tue, 18 Dec 2018 22:28:25 +0100 Message-Id: <20181218212844.30445-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_132932_284515_39DA3EE7 X-CRM114-Status: GOOD ( 11.65 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , Kevin Hilman , linux-kernel@vger.kernel.org, Carlo Caione , "open list:ARM/Amlogic Meson SoC support" , "moderated list:ARM/Amlogic Meson SoC support" MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Martin Blumenstingl Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 23c7638e2bb3..84bd9479c3f8 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_ARM +#include +#endif + #define MESON_ISA_TIMER_MUX 0x00 #define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) #define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) @@ -54,6 +58,18 @@ static void __iomem *timer_base; +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + static u64 notrace meson6_timer_sched_read(void) { return (u64)readl(timer_base + MESON_ISA_TIMERE); @@ -192,6 +208,12 @@ static int __init meson6_timer_init(struct device_node *node) clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + return 0; } TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",