From patchwork Fri Nov 26 08:31:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12640239 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8687CC433EF for ; Fri, 26 Nov 2021 08:33:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359569AbhKZIgy (ORCPT ); Fri, 26 Nov 2021 03:36:54 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43544 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359454AbhKZIex (ORCPT ); Fri, 26 Nov 2021 03:34:53 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VS84027124; Fri, 26 Nov 2021 02:31:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1637915488; bh=6LE8hBzXpp4wq4b9Z3ImFEHagMdc47MSMzKE/9w0Qw4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kVHAZx6nJVKkrqDvP4gV8HG1cmbhaJn26j0fFg3uqx7AezbSdLBuHvmqN22vg3+yS S2jaxVqvzXh8SDgBt6i2FuSfGhghED/MFy+gz4x0RhdAsY+kWSfCt0b6ud5Q6pYYla kGv0JOJKbES2hNVsaNlFgwEkTWTuPZRJ201d8toc= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AQ8VSgr074507 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 26 Nov 2021 02:31:28 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 26 Nov 2021 02:31:27 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 26 Nov 2021 02:31:28 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VKEl127547; Fri, 26 Nov 2021 02:31:24 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I , Subject: [PATCH v2 1/5] dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument Date: Fri, 26 Nov 2021 14:01:15 +0530 Message-ID: <20211126083119.16570-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126083119.16570-1-kishon@ti.com> References: <20211126083119.16570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Fix binding documentation of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" to take phandle with argument. The argument is the register offset within "syscon" used to configure PCIe controller. Similar change for j721e is discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,am65-pci-ep.yaml | 8 ++++++-- .../bindings/pci/ti,am65-pci-host.yaml | 16 ++++++++++++---- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml index 78c217d362a7..98d933b792e7 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -32,8 +32,12 @@ properties: maxItems: 1 ti,syscon-pcie-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. - $ref: /schemas/types.yaml#/definitions/phandle interrupts: minItems: 1 @@ -65,7 +69,7 @@ examples: <0x5506000 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 834dc1c1743c..f909e262f593 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -33,12 +33,20 @@ properties: maxItems: 1 ti,syscon-pcie-id: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_device_id register offset within SYSCON description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID - $ref: /schemas/types.yaml#/definitions/phandle ti,syscon-pcie-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. - $ref: /schemas/types.yaml#/definitions/phandle msi-map: true @@ -84,8 +92,8 @@ examples: #size-cells = <2>; ranges = <0x81000000 0 0 0x10020000 0 0x00010000>, <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-id = <&scm_conf 0x0210>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; From patchwork Fri Nov 26 08:31:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12640237 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D509BC433F5 for ; Fri, 26 Nov 2021 08:33:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359557AbhKZIgx (ORCPT ); Fri, 26 Nov 2021 03:36:53 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44708 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345287AbhKZIex (ORCPT ); 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Fri, 26 Nov 2021 02:31:31 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VKEm127547; Fri, 26 Nov 2021 02:31:28 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I , Subject: [PATCH v2 2/5] PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" Date: Fri, 26 Nov 2021 14:01:16 +0530 Message-ID: <20211126083119.16570-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126083119.16570-1-kishon@ti.com> References: <20211126083119.16570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Get "syscon" pcie_mode and pcie_id offset from the argument of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle respectively. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_mode and pcie_id but now the offset of pcie_mode and pcie_id within "syscon" is now being passed as argument to "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle. If the offset is not provided in "ti,syscon-pcie-id"/"ti,syscon-pcie-mode", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. Similar change for J721E is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 ++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 865258d8c53c..13f03a97714c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -775,12 +775,19 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct of_phandle_args args; + unsigned int offset = 0; devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); if (IS_ERR(devctrl_regs)) return PTR_ERR(devctrl_regs); - ret = regmap_read(devctrl_regs, 0, &id); + /* Do not error out to maintain old DT compatibility */ + ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); + if (!ret) + offset = args.args[0]; + + ret = regmap_read(devctrl_regs, offset, &id); if (ret) return ret; @@ -989,6 +996,8 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) static int ks_pcie_set_mode(struct device *dev) { struct device_node *np = dev->of_node; + struct of_phandle_args args; + unsigned int offset = 0; struct regmap *syscon; u32 val; u32 mask; @@ -998,10 +1007,15 @@ static int ks_pcie_set_mode(struct device *dev) if (IS_ERR(syscon)) return 0; + /* Do not error out to maintain old DT compatibility */ + ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); + if (!ret) + offset = args.args[0]; + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; - ret = regmap_update_bits(syscon, 0, mask, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) { dev_err(dev, "failed to set pcie mode\n"); return ret; @@ -1014,6 +1028,8 @@ static int ks_pcie_am654_set_mode(struct device *dev, enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; + struct of_phandle_args args; + unsigned int offset = 0; struct regmap *syscon; u32 val; u32 mask; @@ -1023,6 +1039,11 @@ static int ks_pcie_am654_set_mode(struct device *dev, if (IS_ERR(syscon)) return 0; + /* Do not error out to maintain old DT compatibility */ + ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); + if (!ret) + offset = args.args[0]; + mask = AM654_PCIE_DEV_TYPE_MASK; switch (mode) { @@ -1037,7 +1058,7 @@ static int ks_pcie_am654_set_mode(struct device *dev, return -EINVAL; } - ret = regmap_update_bits(syscon, 0, mask, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) { dev_err(dev, "failed to set pcie mode\n"); return ret; From patchwork Fri Nov 26 08:31:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12640241 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E752C433EF for ; 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Fri, 26 Nov 2021 02:31:36 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 26 Nov 2021 02:31:35 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 26 Nov 2021 02:31:35 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VKEn127547; Fri, 26 Nov 2021 02:31:32 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I , Subject: [PATCH v2 3/5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Date: Fri, 26 Nov 2021 14:01:17 +0530 Message-ID: <20211126083119.16570-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126083119.16570-1-kishon@ti.com> References: <20211126083119.16570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D–July 2018–Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452f/sprz452f.pdf Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 13f03a97714c..52d20fe17ee9 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -35,6 +35,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -105,6 +110,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -528,7 +535,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, @@ -540,6 +551,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -565,6 +581,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 bytes. Force the MRRS to + * 128 bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); From patchwork Fri Nov 26 08:31:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12640245 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1067EC433F5 for ; Fri, 26 Nov 2021 08:33:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359690AbhKZIhG (ORCPT ); Fri, 26 Nov 2021 03:37:06 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:45010 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353255AbhKZIfF (ORCPT ); Fri, 26 Nov 2021 03:35:05 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8Vd4S091368; Fri, 26 Nov 2021 02:31:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1637915499; bh=g2rQ1mMO32HDUsjYDmMgPUbjxQTL8iGUWukhF+UH/Ng=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iMQoFKr3UMXrqa6ROWP7D/h7chmlOUfRjqsjusuL4eAROikTHSjaqqMfwQlkRBfEp 2eH6nSmhSusbuVernqksgeT3/dubP6oKzyUtJ8+80DI/VM6q9uHOjJ8ovKOzjKNK9d mYoATUpXyGOC6o5SUEuvYb/10+6SP7zWoAhWyMYI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AQ8VdkQ039546 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 26 Nov 2021 02:31:39 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 26 Nov 2021 02:31:39 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 26 Nov 2021 02:31:39 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VKEo127547; Fri, 26 Nov 2021 02:31:36 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I , Subject: [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET Date: Fri, 26 Nov 2021 14:01:18 +0530 Message-ID: <20211126083119.16570-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126083119.16570-1-kishon@ti.com> References: <20211126083119.16570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org AM654 RootComplex has a hard coded 64 bit BAR of size 1MB and also has both MSI and MSI-X capability in it's config space. If PCIEPORTBUS is enabled, it tries to configure MSI-X and msix_mask_all() adds about 10 Second boot up delay when it tries to write to undefined location. Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET so that msix_map_region() returns NULL for Root Complex and avoid un-desirable writes to MSI-X table. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 52d20fe17ee9..73e6626a0d8f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -557,8 +557,14 @@ static void ks_pcie_quirk(struct pci_dev *dev) { 0, }, }; - if (pci_is_root_bus(bus)) + if (pci_is_root_bus(bus)) { bridge = dev; + if (pci_match_id(am6_pci_devids, bridge)) { + struct resource *r = &dev->resource[0]; + + r->flags |= IORESOURCE_UNSET; + } + } /* look for the host bridge */ while (!pci_is_root_bus(bus)) { From patchwork Fri Nov 26 08:31:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12640243 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 556D4C4332F for ; Fri, 26 Nov 2021 08:33:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359652AbhKZIhC (ORCPT ); Fri, 26 Nov 2021 03:37:02 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44072 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353051AbhKZIfB (ORCPT ); Fri, 26 Nov 2021 03:35:01 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VhD1038136; Fri, 26 Nov 2021 02:31:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1637915503; bh=rfSsCVruqpaxxllAnn66mkt6kvzxK7REyk9p1WoT/Sk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vWcAILyOWp9sSgjEeszqJwIgevUxF7Y9ASckfQaKvbG6x1WI/Lv2gb8+RPLa6ORnR KYAgoa4ir56qfySNGAipPDw2599hNpludrXmwdstyJ2/UqSzM6U9hPfl0W1GxyDkek 4Q+5qTqKhGEOh1lQ5OQbP0M9lpVk7iUnZd9HtJXM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AQ8Vhfe035383 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 26 Nov 2021 02:31:43 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 26 Nov 2021 02:31:43 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 26 Nov 2021 02:31:43 -0600 Received: from a0393678-lt.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AQ8VKEp127547; Fri, 26 Nov 2021 02:31:39 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , Kishon Vijay Abraham I , Subject: [PATCH v2 5/5] PCI: keystone: Set DMA mask and coherent DMA mask Date: Fri, 26 Nov 2021 14:01:19 +0530 Message-ID: <20211126083119.16570-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126083119.16570-1-kishon@ti.com> References: <20211126083119.16570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set DMA mask and coherent DMA mask such to indicate the device can address the entire address space (32-bit in the case of K2G and 48-bit in the case of AM654). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 73e6626a0d8f..80dbab267f7b 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1224,6 +1224,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48))) { + dev_err(dev, "Cannot set DMA mask\n"); + return -EINVAL; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1;