From patchwork Wed Dec 1 07:29:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05573C433FE for ; Wed, 1 Dec 2021 07:29:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347464AbhLAHcv (ORCPT ); Wed, 1 Dec 2021 02:32:51 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:55172 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232254AbhLAHcu (ORCPT ); Wed, 1 Dec 2021 02:32:50 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 28B4DCE1D73; Wed, 1 Dec 2021 07:29:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0ABE2C53FCE; Wed, 1 Dec 2021 07:29:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343766; bh=V1TJkX0Mv8NmFefTXv3/JgtPii8IaGT4gjWuDhvPxKU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tv7Qm6wOHTEUl+NSpe+lsUEhrzpRsMGwCs/Mg1yu0/Zg/uorByVb1x/7L6rtwYrOx cE7Z5ljXqpGzZv4yvJCAS9mfPAXC0H2miEdvgPOGciNl4dnYZ0d+aXCZMlsqCMGJMv 0vmovXJEBoOUzUaRVqHwwUK4SCkbrdqWJ5+9rCXO3H5Vow9gywW8y3E6higmVwGlZF doqkhJFAEuRtYqx6NiVqXTbRwW2/djnpsS2UPe9qu/RNAQzVqxkru9jpNs1DV1payz gJwHkq92oVwpbwC+eYnrlhD48RInZ0ZBPDw6FNwEDLFRx0viwCFQLX9PftEGsTJl/L EslH/rJnAJ69A== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/15] arm64: dts: qcom: Add base SM8450 DTSI Date: Wed, 1 Dec 2021 12:59:01 +0530 Message-Id: <20211201072915.3969178-2-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add based DTSI for SM8450 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to shell with console on boards with this SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 476 +++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi new file mode 100644 index 000000000000..d838283bde4b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <327>; + exit-latency-us = <1502>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-off"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + local-timer-stop; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8450", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17423000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17425000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17427000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17429000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x1742b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x1742d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>, + <0x0 0x17a30000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8450-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From patchwork Wed Dec 1 07:29:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72ADFC433EF for ; Wed, 1 Dec 2021 07:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347525AbhLAHc5 (ORCPT ); Wed, 1 Dec 2021 02:32:57 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:55196 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347483AbhLAHcw (ORCPT ); Wed, 1 Dec 2021 02:32:52 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 17319CE1D75; Wed, 1 Dec 2021 07:29:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE44BC53FAD; Wed, 1 Dec 2021 07:29:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343769; bh=qUBCqTkVk67waMd2M9a6Vqzm6ZXAqVe1PfEqjwIDh4M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CkYFN9R/d1jtPIkncUI0kUQv0o6XdO7QEo0FaWdkk3lbTcjTUH+TB2ZAmMpq1twQK EXfYLv8RYj3HKljky8DtxwWH6GHBmh1KjNpebZy9LaQoyeVD0I9b3KFFd/etl4Vuec K6CE8u/r94ywTNCLLP1X8pBRd3wWNoodL0Ok9OBsavixctqQnRmtey3h3/Cp0w16e8 6EGfNHgh6HUym+IJnvC65kJbJWvOXt9ZcgdFw2RK8YbYsxghD5QVx6lNREKhjKsqBD jIbTGXjOsY5llRg0FuwoOvcCc9KRzeQxWzJCFwTm7XDlIHtTLcHyyGDY/MEVf2ttXf I0u4gnXr42AMA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/15] arm64: dts: qcom: Add base SM8450 QRD DTS Date: Wed, 1 Dec 2021 12:59:02 +0530 Message-Id: <20211201072915.3969178-3-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DTS for Qualcomm QRD platform which uses SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6b816eb33309..9b37261484cf 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -107,3 +107,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts new file mode 100644 index 000000000000..127d32502555 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 QRD"; + compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; From patchwork Wed Dec 1 07:29:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1676FC4332F for ; Wed, 1 Dec 2021 07:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347535AbhLAHc6 (ORCPT ); Wed, 1 Dec 2021 02:32:58 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:60028 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347488AbhLAHcz (ORCPT ); Wed, 1 Dec 2021 02:32:55 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7BC38B81DB4; Wed, 1 Dec 2021 07:29:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD803C53FD0; Wed, 1 Dec 2021 07:29:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343772; bh=/0+0OMCO4Ol9mRu+prhPrggfUn9DX4muACmDlOVzmUI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F8iMNfkxOgYaYW4QvefD1Ie562FmK+VjqL1TPSQqr9481tjBlgofHclTAU6gMpUDH wQp4sDO3nnxWfiKIIvlX71uG/ivWTLadL4BhrZrx585Ss7nG7C7b+Weiz3Q+ciwmpJ uuNAmLLWG0m3Ef+Z4paG2xvsnyVh/p1o3GkYTikuVehXLaA9svtbfXNUEWCVSRwz/l ldnX+rtQUumy+Qyr0YjBNv2yFQYK5PuqtYB5TeA1eVbrihUpr2iUTpkgByaCLqqcsN BX5qQDzOueUxlZ9tOLr6HkILQJw6PeXnV8qmTyYGohF9xZ1pxaiAGQxyQ0UK4UYQma upnIM8XrgEB1g== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/15] arm64: dts: qcom: sm8450: Add tlmm nodes Date: Wed, 1 Dec 2021 12:59:03 +0530 Message-Id: <20211201072915.3969178-4-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tlmm node found in SM8450 SoC and uart pin configuration Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d838283bde4b..f0b9e80238a2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,8 @@ uart7: serial@99c000 { reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default_state>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +368,33 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + qup_uart7_default_state: qup-uart3-default-state { + rx { + pins = "gpio26"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + tx { + pins = "gpio27"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Dec 1 07:29:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDCB0C4167B for ; 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d=kernel.org; s=k20201202; t=1638343775; bh=W8Ba4kmb3j3MnIYQM59/7uqCDcqW2uCLi9GncnBGpcE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X3bzsrqMBKyY/Ewfhko+QOUCzm6KR4t/I8R80nv/W/ALM09Qd71kS2qKWb/cjlNjm suO57BOgco5W8xzJZD15CA/nOWI8Cm+9aRYI1GU8cWo+pPTyyed65YuiREq3D9yfFX 9x9SykKt2BCb83tq9f6PUjJ4P/Kkx9RCQtYfUsVvHFhURl7visQjtGKhoxtDxr7T0m U+XRU1b+Co6gW2XDKNPY0Ca/HUxK0CdnjBYxRzCsqPhFeOhtcDLItwBDoKYjtcXt0Q ThugDTxpu8N2jlL50mCrrEPIx/v5hAfDOvG0G92/jVEyZ+DEhdNuPbXiL8WF5DNv+3 oh/88qUkdwDeg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/15] arm64: dts: qcom: sm8450-qrd: Add reserved gpio range for QRD Date: Wed, 1 Dec 2021 12:59:04 +0530 Message-Id: <20211201072915.3969178-5-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some tlmm gpios are reserved, so mark them as such in QRD DTS Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 127d32502555..8dcd41c4e5ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -24,6 +24,10 @@ &qupv3_id_0 { status = "okay"; }; +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + &uart7 { status = "okay"; }; From patchwork Wed Dec 1 07:29:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD7FFC433F5 for ; Wed, 1 Dec 2021 07:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347585AbhLAHdH (ORCPT ); Wed, 1 Dec 2021 02:33:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347544AbhLAHdC (ORCPT ); Wed, 1 Dec 2021 02:33:02 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96EA6C06175E; Tue, 30 Nov 2021 23:29:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id E401CCE1D7A; Wed, 1 Dec 2021 07:29:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C64F5C53FCC; Wed, 1 Dec 2021 07:29:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343778; bh=9qt85WhT7cSNlY+anGt2ZH9cEOEi0wyaFiJhYqL/NO8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bkeRd1cSrOEFfoHxay6BDAnNT3Cn2KxM4RaAF+m/DOCUj0Et9r1ylIykSxRnKoB4v lKOmH2i9ldlpdzfcOjhUeH6R+y2Fqv/WexIvxGsDsEKkMNIEwHaq8qOAoEbZbwhEIW aMSAso0hPQJRJZarCRx543gkjeydZKQtzyx+dfsQ8EY9UMJ4/gWkj/te4ThHFexXo1 xSi4kM4MyFbLE9PfWVQ+mn3uokA1dqymgGzWTtMcJ98obo8LWGZe6eV/rgDu2cXQyJ N7ocfPTEwF6ZC6IHApvt1Bg7tnp/YD4pwxXpA1/4exveMwPskLCoC97YSvf8Bgd8HE vkNPd7PYZeBww== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/15] arm64: dts: qcom: sm8450: Add reserved memory nodes Date: Wed, 1 Dec 2021 12:59:05 +0530 Message-Id: <20211201072915.3969178-6-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the reserved memory nodes for SM8450. This is based on the downstream documentation. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 221 +++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f0b9e80238a2..79aead4cba66 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -310,6 +310,227 @@ CLUSTER_PD: cpu-cluster0 { }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dt_log_mem: memory@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: memory@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x180000>; + }; + + xbl_sc_mem: memory@807c0000 { + no-map; + reg = <0x0 0x807c0000 0x0 0x40000>; + }; + + aop_image_mem: memory@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: memory@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: memory@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: memory@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: memory@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + /* secdata region can be reused by apps */ + smem: memory@80900000 { + compatible = "qcom,smem"; + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: memory@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap: memory@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + camera_mem: memory@85200000 { + no-map; + reg = <0x0 0x85200000 0x0 0x500000>; + }; + + video_mem: memory@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x700000>; + }; + + adsp_mem: memory@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x2100000>; + }; + + slpi_mem: memory@88000000 { + no-map; + reg = <0x0 0x88000000 0x0 0x1900000>; + }; + + cdsp_mem: memory@89900000 { + no-map; + reg = <0x0 0x89900000 0x0 0x2000000>; + }; + + ipa_fw_mem: memory@8b900000 { + no-map; + reg = <0x0 0x8b900000 0x0 0x10000>; + }; + + ipa_gsi_mem: memory@8b910000 { + no-map; + reg = <0x0 0x8b910000 0x0 0xa000>; + }; + + gpu_micro_code_mem: memory@8b91a000 { + no-map; + reg = <0x0 0x8b91a000 0x0 0x2000>; + }; + + spss_region_mem: memory@8ba00000 { + no-map; + reg = <0x0 0x8ba00000 0x0 0x180000>; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: memory@8bb80000 { + no-map; + reg = <0x0 0x8bb80000 0x0 0x60000>; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: memory@8bbe0000 { + no-map; + reg = <0x0 0x8bbe0000 0x0 0x20000>; + }; + + mpss_mem: memory@8bc00000 { + no-map; + reg = <0x0 0x8bc00000 0x0 0x13200000>; + }; + + cvp_mem: memory@9ee00000 { + no-map; + reg = <0x0 0x9ee00000 0x0 0x700000>; + }; + + global_sync_mem: memory@a6f00000 { + no-map; + reg = <0x0 0xa6f00000 0x0 0x100000>; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa0000000 */ + + oem_vm_mem: memory@bb000000 { + no-map; + reg = <0x0 0xbb000000 0x0 0x5000000>; + }; + + mte_mem: memory@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x20000000>; + }; + + qheebsp_reserved_mem: memory@e0000000 { + no-map; + reg = <0x0 0xe0000000 0x0 0x600000>; + }; + + cpusys_vm_mem: memory@e0600000 { + no-map; + reg = <0x0 0xe0600000 0x0 0x400000>; + }; + + hyp_reserved_mem: memory@e0a00000 { + no-map; + reg = <0x0 0xe0a00000 0x0 0x100000>; + }; + + trust_ui_vm_mem: memory@e0b00000 { + no-map; + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + }; + + trust_ui_vm_qrtr: memory@e55f3000 { + no-map; + reg = <0x0 0xe55f3000 0x0 0x9000>; + }; + + trust_ui_vm_vblk0_ring: memory@e55fc000 { + no-map; + reg = <0x0 0xe55fc000 0x0 0x4000>; + }; + + trust_ui_vm_swiotlb: memory@e5600000 { + no-map; + reg = <0x0 0xe5600000 0x0 0x100000>; + }; + + tz_stat_mem: memory@e8800000 { + no-map; + reg = <0x0 0xe8800000 0x0 0x100000>; + }; + + tags_mem: memory@e8900000 { + no-map; + reg = <0x0 0xe8900000 0x0 0x1200000>; + }; + + qtee_mem: memory@e9b00000 { + no-map; + reg = <0x0 0xe9b00000 0x0 0x500000>; + }; + + trusted_apps_mem: memory@ea000000 { + no-map; + reg = <0x0 0xea000000 0x0 0x3900000>; + }; + + trusted_apps_ext_mem: memory@ed900000 { + no-map; + reg = <0x0 0xed900000 0x0 0x3b00000>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; From patchwork Wed Dec 1 07:29:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6FF7C433FE for ; Wed, 1 Dec 2021 07:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233556AbhLAHdL (ORCPT ); Wed, 1 Dec 2021 02:33:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347575AbhLAHdF (ORCPT ); Wed, 1 Dec 2021 02:33:05 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 868DDC061759; Tue, 30 Nov 2021 23:29:44 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id D4160CE1759; Wed, 1 Dec 2021 07:29:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5F75C53FD0; Wed, 1 Dec 2021 07:29:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343781; bh=s8qEk1HK0t6PsaG1jQLTOHouIh3JdaX+ehSo1B9dxfM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ot7qo4Jhydns0dhy/K1Ec51bspYFnLpEuq+AL49QhNUE+5Im1VQ7sdxbqu+R5ADWJ nKx0e5VHpc7I3YbqCO6BIoHFkkmUJkt5sIavUkTbE9WAtZhp4aHb2WQEKrWnAQsAjx DFhyRdSoWD6bLs6wLrZZyJNTwDRpW/+4PX8yzOIVCcBq1AgxvlD/ZjwD+Ua/XMBJ4R EXFsOIwmJPhvhUSvrSDcBEEqdrHosICC7574y2mvl4b+Qz82AmF51oIIdcqBRNGH9Y rC14MBY0HUEpGYhzry35+8BIftmU9xEtMYYqOvnIoy0fZmGQ95a8TB9c2lZP0h/d3w iQIHoTSHxpkng== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/15] arm64: dts: qcom: sm8450: add smmu nodes Date: Wed, 1 Dec 2021 12:59:06 +0530 Message-Id: <20211201072915.3969178-7-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the apps smmu node as found in the SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 79aead4cba66..53a6f2275621 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -616,6 +616,109 @@ tx { }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Dec 1 07:29:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C2D1C433EF for ; Wed, 1 Dec 2021 07:29:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347597AbhLAHdN (ORCPT ); Wed, 1 Dec 2021 02:33:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347593AbhLAHdI (ORCPT ); Wed, 1 Dec 2021 02:33:08 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABFD7C06175E; Tue, 30 Nov 2021 23:29:47 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id C3BBCCE1759; Wed, 1 Dec 2021 07:29:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A58FCC53FAD; Wed, 1 Dec 2021 07:29:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343784; bh=dSc9yPVr+4tJCAClU8yVk/GcVNpi70CHm53GOLY2KfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZCJKJYQiw94fKaAj+/tmP1GaXEC0qziOX8ag7XpWiuJyjR9j4quF5KJ17ACuwZc2k 13tErAbR2a0nOU3Y2oO204xiliDndPy/8D8UMwJkcuf6I8z7SzUnm9Kfe8YI+bd9E9 oc9zJOiHwJaopFHQ9UKo+UiKOvGRqrw4yCDPTLa35CoQtqilKU6OmPpSDfak0wR+r7 EF/quoQnCV0YksvkFCb99m/rBnPqLLhdUm3/jYpjwyS1qDMqy08uvZelBJ0L8wuw3f 9GXxXS9fkw4BgTXOq7tYKw+Nc3OfpTQF6gxPMEgDoO6MhyrX5PzUk2u7y8t8lZ4PzR X2yMXk4JTTt/A== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/15] arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes Date: Wed, 1 Dec 2021 12:59:07 +0530 Message-Id: <20211201072915.3969178-8-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the RPMH regulators found in QRD-SM8450 platform Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 322 ++++++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8dcd41c4e5ab..218eb3ce1ee5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm8450.dtsi" / { @@ -18,6 +19,327 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; }; &qupv3_id_0 { From patchwork Wed Dec 1 07:29:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B99BC43217 for ; Wed, 1 Dec 2021 07:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347572AbhLAHdN (ORCPT ); Wed, 1 Dec 2021 02:33:13 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:60256 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347503AbhLAHdI (ORCPT ); Wed, 1 Dec 2021 02:33:08 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 25BD7B81691 for ; Wed, 1 Dec 2021 07:29:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94ECCC53FCE; Wed, 1 Dec 2021 07:29:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343785; bh=7kdQ8mpRBuZQda5p6bM99JD00jvrgAjeSWAOBWeN7Co=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pjo8cPrMwduDi5rk/ECcv2SvWwvaarJt/hTA7NxSNu/xFqzAlYq1nfX/URznZEWPG UAchVkJrLTAMcDFGUYgWkg6zoJLSvdMGw4Gu/fpANw/MtNx3Lj6ZbWYPZxdSp90fRz Rewm/qGB1OvwwBrfk7XQ8+it+jeNii4Qf01/rUrY7CzPkynfHZXLs6cx6xF2Y5QIhS 1UN7Tj7DtBTMyvdAAWeceG8ltXOu9z6gbVjNdGMpxOim3RMbdC+h6FiBCCj3t0lzBt wd0+HMvwYzsZwgOdfu98BNhah3zYu9xJjJp+vQ7nFeaaUvqxUIpuORo0fcUq7O/clm UvSGRm+twMBYQ== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul Subject: [PATCH 08/15] arm64: dts: qcom: sm8450: add ufs nodes Date: Wed, 1 Dec 2021 12:59:08 +0530 Message-Id: <20211201072915.3969178-9-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the UFS and QMP PHY node for SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 53a6f2275621..75827bbfb3ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -816,6 +816,78 @@ rpmhcc: clock-controller { clocks = <&xo_board>; }; }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8450-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", "ref_aux", "qref"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + #clock-cells = <0>; + }; + }; }; timer { From patchwork Wed Dec 1 07:29:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 658C9C433F5 for ; Wed, 1 Dec 2021 07:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347598AbhLAHd1 (ORCPT ); Wed, 1 Dec 2021 02:33:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347570AbhLAHdU (ORCPT ); Wed, 1 Dec 2021 02:33:20 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43447C061759; Tue, 30 Nov 2021 23:29:51 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0D13FB81DCD; Wed, 1 Dec 2021 07:29:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7772EC53FD2; Wed, 1 Dec 2021 07:29:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343788; bh=U1j7MvbU2HWqoZabRFMM4z5W710RB/aXOuL9G6hwghc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NleVHZuxHvpbHZ1OazLK4Q/TEeW0mOMBhhaYPU8OeyXULrnyX8MUTKCd/BymJsgL9 ubfxbgF5H59Bw1hYYhzo58BP6KQSWMUhH5y9BYCK5sGbFGaKv/gzG5V8TI6OdVcGDI di+LCtSykcDuH/bReiYQ4sBFR36Ks2EVyVMng5sBnfu/kfVGuiAPRKizDHNmCcNrre tMLNtl76HRMxCffAzZ+7r7K87ZY/qBRwiptBo2sOIN4IWEodbDlV0sYPhV/jR3uhra AR2VX4EsSlSe2zgOsGjcFUjXT2HGaUk1Oosv7qs3SzYrPGtrN+gv/ebhSZodAjzsZw LtJKe+bu+D9BQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/15] arm64: dts: qcom: sm8450-qrd: enable ufs nodes Date: Wed, 1 Dec 2021 12:59:09 +0530 Message-Id: <20211201072915.3969178-10-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the UFS and phy node and add the regulators used by them. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 218eb3ce1ee5..3e65d662ab8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "sm8450.dtsi" @@ -353,3 +354,23 @@ &tlmm { &uart7 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; From patchwork Wed Dec 1 07:29:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE19C433FE for ; Wed, 1 Dec 2021 07:30:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347611AbhLAHd3 (ORCPT ); Wed, 1 Dec 2021 02:33:29 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:60332 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347594AbhLAHdU (ORCPT ); Wed, 1 Dec 2021 02:33:20 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EF46FB81DB4; Wed, 1 Dec 2021 07:29:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6622BC53FCE; Wed, 1 Dec 2021 07:29:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343791; bh=JXRzfFY7RW+lpnD0P5F80pjzcfss6AovJmixExX2ThY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GehYp/GKoWWGbJaAsurHxyAUyiFa4jvhem+FwWTROsjS/IHXZU0l/Aw6+HLM709mQ 1Jl7edT1ir1mUG8BRCNS7WE9e3yUendvTKIQqEzxAJ0gIzaeNMs/rPdEtHZroRbTcX n1sBIx24qX6mDWkLeQ9UCLBuLDQTMcubJuP3vu/Gls1kyVY4wRJXca5pfx54oDbw/p 2ISF/Mrxd/odhJ81A36owycdiHKZgvpJv4iojOU8WYNohrgdKxiBiCGKC9TtJ+Pxcl Gtlzr8vJ4tEtmsKhAaJef+RS0OwooGKljBRdwmu7SNJm53tkIH8dFk/h3GrBOj+GgE irUKFuJcPbjPA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/15] arm64: dts: qcom: sm8450: add interconnect nodes Date: Wed, 1 Dec 2021 12:59:10 +0530 Message-Id: <20211201072915.3969178-11-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org And the various interconnect nodes found in SM8450 SoC and use it for UFS controller. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 80 ++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 75827bbfb3ad..4c7cdcea33fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include / { @@ -573,6 +574,61 @@ uart7: serial@99c000 { }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm8450-config-noc"; + reg = <0 0x01500000 0 0x1c000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1580000 { + compatible = "qcom,sm8450-mc-virt"; + reg = <0 0x01580000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + reg = <0 0x01680000 0 0x1e200>; + compatible = "qcom,sm8450-system-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + reg = <0 0x016c0000 0 0xe280>; + compatible = "qcom,sm8450-pcie-anoc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0 0x016e0000 0 0x1c080>; + compatible = "qcom,sm8450-aggre1-noc"; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0 0x01700000 0 0x31080>; + compatible = "qcom,sm8450-aggre2-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0 0x01740000 0 0x1f080>; + compatible = "qcom,sm8450-mmss-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -817,6 +873,13 @@ rpmhcc: clock-controller { }; }; + gem_noc: interconnect@19100000 { + reg = <0 0x19100000 0 0xbb800>; + compatible = "qcom,sm8450-gem-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -833,6 +896,9 @@ ufs_mem_hc: ufshc@1d84000 { iommus = <&apps_smmu 0xe0 0x0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", "bus_aggr_clk", @@ -888,6 +954,20 @@ ufs_mem_phy_lanes: lanes@1d87400 { #clock-cells = <0>; }; }; + + nsp_noc: interconnect@320c0000 { + reg = <0 0x320c0000 0 0x10000>; + compatible = "qcom,sm8450-nsp-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3c40000 { + reg = <0 0x3c40000 0 0x17200>; + compatible = "qcom,sm8450-lpass-ag-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; }; timer { From patchwork Wed Dec 1 07:29:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0875C4332F for ; Wed, 1 Dec 2021 07:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232422AbhLAHd1 (ORCPT ); Wed, 1 Dec 2021 02:33:27 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:60416 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347637AbhLAHdU (ORCPT ); Wed, 1 Dec 2021 02:33:20 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E71D2B81DBE; Wed, 1 Dec 2021 07:29:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55C0BC53FAD; Wed, 1 Dec 2021 07:29:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343794; bh=FC8+NrK3g3u21XVQNMSt0ZiUgeoVa8SH0bDWkvPD2Mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HWo8UmiH7IM1HNshrnWXuSljft9WpQPJ+NujjHMDUvhS9jpcldmcnGO0Y9L0LUPAM Bvc2eubLc7xqb83uayvPKowneH90xLOGAKcUI7JQ0BbRN3y5jyoV0A2fieNOw2E2eb TdpyT/uHIJTFifRN7VWA1owUy7kk5uy81b/9Mw78ahAoEac/0LZnmvy+r22E5Yz7eG arS1fE+BdarRenlCSNwrBAKTI71iOEn/r9JSSL0tu89AJC5+OBDOKkthBNcS1MEwPY EGIhJQykkAbngrx3fl0FPf7aZwMHI0pDQbrrEDqbWOwL9Ltbyg3EzqpxceHfZdh7KN vx03zkjKxIJcw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/15] arm64: dts: qcom: sm8450: add spmi node Date: Wed, 1 Dec 2021 12:59:11 +0530 Message-Id: <20211201072915.3969178-12-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the spmi bus as found in the SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4c7cdcea33fa..25d93a51ac19 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -645,6 +645,24 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + spmi_bus: spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x00003000>, + <0x0 0x0c500000 0x0 0x00400000>, + <0x0 0x0c440000 0x0 0x00080000>, + <0x0 0x0c4c0000 0x0 0x00010000>, + <0x0 0x0c42d000 0x0 0x00010000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm8450-tlmm"; reg = <0 0x0f100000 0 0x300000>; From patchwork Wed Dec 1 07:29:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 906DCC433EF for ; Wed, 1 Dec 2021 07:30:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347604AbhLAHd2 (ORCPT ); Wed, 1 Dec 2021 02:33:28 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:60456 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347621AbhLAHdU (ORCPT ); Wed, 1 Dec 2021 02:33:20 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CB83AB81DE8; Wed, 1 Dec 2021 07:29:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 454DEC53FCE; Wed, 1 Dec 2021 07:29:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343797; bh=UecTKToUF3fuoVqhV5HcpAyYCXlW6vF0oJOewbWkneY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aMRMyYU0CLjVNQn4TcWiQzRneNvTeQOFHWgu7gLOQBrTEL/JFX1etQm0RPcwZfCjb Or12JRHlXHvzVIJd8W5RQoY3htsGOhPzkNB5NAL92q8Yem1lwFY+NQuZoC7k4jT0IP Y619K3hRz0xBJ1LF9rbPlm2j36ut1l9xGnFhiA13B6p8e2JbAyVQXfbKbXeJb28XNK Q4kPWVtydANGUUqX30eo1AxI6ukHE0kX8eKS3JQYmAkkgR2RdEYnZwA9FubS8eHw4p VIcvUOfIc7aJaX/V8CM3dlhWBK+BV3mQa/081CKkOUrVxLzEInL157EnkZ1NXZ9J/u lxRHF7ItfiWdg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/15] arm64: dts: qcom: sm8450-qrd: include pmic files Date: Wed, 1 Dec 2021 12:59:12 +0530 Message-Id: <20211201072915.3969178-13-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8450 QRD platform has bunch of PMICs, include the common ones PM8350, PM8350b and PMR735b Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 3e65d662ab8c..48228888f500 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -8,6 +8,9 @@ #include #include #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; From patchwork Wed Dec 1 07:29:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 747C2C433FE for ; Wed, 1 Dec 2021 07:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347708AbhLAHdg (ORCPT ); Wed, 1 Dec 2021 02:33:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347537AbhLAHdZ (ORCPT ); Wed, 1 Dec 2021 02:33:25 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5376FC06175C; Tue, 30 Nov 2021 23:30:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 9FCE3CE1D67; Wed, 1 Dec 2021 07:30:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33C7FC53FD2; Wed, 1 Dec 2021 07:29:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343800; bh=O3yKs0vj19W5/BZ/Tdv8ra+JxyZYiCDB3WZbbopGoNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CKfWPz/ywrjiFAqe+TH4KwsnbY7lON0wrCdS1J/EFEfmoC0Cmne5FJ5TvtKL4Rc4m c6iQwTbR7vR/aY4mEsjiET5CG1mL18l75+jeaeRQEb6BQJPV7bcRCIWfShfmIIwZ3y CMv0+llIQIKRndOZyJu+xGHHAXF04mx7Uo8t2RHmPbkHIz1/zGr2epAU//djG4lvpt 1ApFj5VtsbcpGvRZ32cFHXesb9KmVU2L5/ob9YQuTrSVSkqjDdcJ2598bW1Lvv/r/Z j0knfwdviW7eGqVCaRI4GLI/BLj2AjtehOzeWD2vyAh5hhOBE1O2I9moGsk4kn2qcX UfF9ib3Q8If2w== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH 13/15] arm64: dts: qcom: sm8450: Add rpmhpd node Date: Wed, 1 Dec 2021 12:59:13 +0530 Message-Id: <20211201072915.3969178-14-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov This adds RPMH power domain found in SM8450 SoC Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 25d93a51ac19..8f0819df8039 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -889,6 +890,57 @@ rpmhcc: clock-controller { clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8450-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; gem_noc: interconnect@19100000 { From patchwork Wed Dec 1 07:29:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1199C433F5 for ; Wed, 1 Dec 2021 07:30:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347578AbhLAHdc (ORCPT ); Wed, 1 Dec 2021 02:33:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347613AbhLAHd1 (ORCPT ); Wed, 1 Dec 2021 02:33:27 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 747D8C06175E for ; Tue, 30 Nov 2021 23:30:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id C206ACE1759 for ; Wed, 1 Dec 2021 07:30:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F67FC53FCC; Wed, 1 Dec 2021 07:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343803; bh=H/dTdR1cSXRx+8KP5/7NW7SGJuPWfxGPG0s/mP3JcNI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qu6HI3BJQx5iYoq16IWR+A02qi6fmB0wxR0iA4qt4awh4dUriLfNh7tqP8oLKZLEF e/1vsrGHhmDhkUY0VRjuVLSYmcRmqSRydgX7tthJBN7zoIE3vFylPRb5jvZA67eqnw aMCOui8iTrSvCMaVwx09tox0KbtC7wnA9iGQtadCabMIq2n98rMcFYpsjELNsVulyK HReo5dd3RomBkSN4cokFJ22qFaNzGcAB81Bdi+Z+mjZBar/eHYf8NpMBL64dKruh60 pb1d9CNIOyVAbdyo8ktPE/KNjiJXEfrrJHSXe39Q1sDY0bdqzz+R3puUwd/q2EyCeU QvlWaQnlt21ZA== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vladimir Zapolskiy , Vinod Koul Subject: [PATCH 14/15] arm64: dts: qcom: sm8450: add cpufreq support Date: Wed, 1 Dec 2021 12:59:14 +0530 Message-Id: <20211201072915.3969178-15-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vladimir Zapolskiy The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8f0819df8039..29c5abcfa074 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -45,6 +45,7 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -62,6 +63,7 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -76,6 +78,7 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -90,6 +93,7 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -104,6 +108,7 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -118,6 +123,7 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -133,6 +139,7 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -147,6 +154,7 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -170,7 +178,9 @@ core2 { core3 { cpu = <&CPU3>; }; + }; + cluster1 { core4 { cpu = <&CPU4>; }; @@ -182,7 +192,9 @@ core5 { core6 { cpu = <&CPU6>; }; + }; + cluster2 { core7 { cpu = <&CPU7>; }; @@ -943,6 +955,21 @@ rpmhpd_opp_turbo_l1: opp10 { }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + gem_noc: interconnect@19100000 { reg = <0 0x19100000 0 0xbb800>; compatible = "qcom,sm8450-gem-noc"; From patchwork Wed Dec 1 07:29:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12649353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47785C433FE for ; Wed, 1 Dec 2021 07:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347663AbhLAHde (ORCPT ); Wed, 1 Dec 2021 02:33:34 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:55602 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347664AbhLAHd2 (ORCPT ); Wed, 1 Dec 2021 02:33:28 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id E65D5CE1D76 for ; Wed, 1 Dec 2021 07:30:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94376C53FD0; Wed, 1 Dec 2021 07:30:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638343805; bh=fOecN1+zYsm6d7VARL+K91hTDCpiK30taxsF9RNJCIs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zm/IauwsG7f2K0HZWHzC6WMGGlR626m26E+qpb68NZXEAGbsrCHLoZZ78GtP/++zb 4xtybBJO7asIVTF7v95U4o1kW4hCqSkyS7RnjpahYYiqBrsdevN8GD5lpE8Oby9+84 0lfOkMWMuKddCUnJNpOCd2BnFQkW36GF3PaLu3NO0l5E8Xl4geCN6TaSTdxk3xTOH2 xD1Q4ejSQmSIFMcuODQDgPPrHC8PG392gr5/p8Pc7oeV5mPBTIJ4ZfqLthXzbMRn8y /BzREmlbe9Oc6w7TY1lhcuDXc6HR4sL9hcvsea0mfuC345lh7v0E+YVdV5ch4X9kEe TFYN2gehCOnyQ== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Dmitry Baryshkov , Vinod Koul Subject: [PATCH 15/15] arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes Date: Wed, 1 Dec 2021 12:59:15 +0530 Message-Id: <20211201072915.3969178-16-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org> References: <20211201072915.3969178-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov Add device tree nodes for two i2c blocks: i2c13 and i2c14. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 29c5abcfa074..40c739b842ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -587,6 +587,44 @@ uart7: serial@99c000 { }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default_state>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default_state>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; @@ -687,6 +725,32 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + qup_i2c13_default_state: qup-i2c13-default-state { + mux { + pins = "gpio48", "gpio49"; + function = "qup13"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c14_default_state: qup-i2c14-default-state { + mux { + pins = "gpio52", "gpio53"; + function = "qup14"; + }; + + config { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_uart7_default_state: qup-uart3-default-state { rx { pins = "gpio26";