From patchwork Sun Dec 5 18:16:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12657205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A4EAC433FE for ; Sun, 5 Dec 2021 18:16:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237151AbhLESUK (ORCPT ); Sun, 5 Dec 2021 13:20:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237125AbhLESUF (ORCPT ); Sun, 5 Dec 2021 13:20:05 -0500 Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 404B1C061714; Sun, 5 Dec 2021 10:16:38 -0800 (PST) Received: by mail-il1-x12d.google.com with SMTP id r2so8062273ilb.10; Sun, 05 Dec 2021 10:16:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=25U6Yhax0BXTLLFHy75HSeiByRDthooJoTH4u1dV5LA=; b=Rvj12MBSzB80e3ODwTCnzkmAw4RhufBgyW4U+R2JP4L0wojyAi/SRkDQxFRsGsZsgG Ot1xrmKFqypAotr9EhCSrd6SGtNYYEi0dqk18FKHD4OGc2kCOQJwP0wgqJK4BZCn+gx1 dpA4FViXSM0f/Dhodlfxnh5j0hdMEWQ2ytdDJPRl9rbtqnLshuSS3x/pdjrH62Ce1WXU A06czOMCtxrssoeWrhD88ZAk8ykMUU1M+1mXofIWbJRSv+zbse0scYbzB+jocTnDccwm 3woQ5qQtcWMWGjrWwOd7+pXIMYz0mguxX/ZKCkaWkDADGQbXvavU25dkjk58jzmhqVb0 ml7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=25U6Yhax0BXTLLFHy75HSeiByRDthooJoTH4u1dV5LA=; b=rn+DVttchGRBCRm5/0Q1ptFrXBms2d7s8NaF1ToKIPX6dz3/rAGhNQciILQe6wjS10 aTQ98X5cFIWWOUvOGy7NCYPgOnThSxkX/ACPZ4sCxIiqJK1+SdLiEi+2qEiMHdjmjB0O hKSpyGG8exAy0OWobhjtYsSpnu/Fxxq6EAGNMtfF/m8nBHk55rNdWnC6NBNjkZNy6Ari MjmUVcz7er8mGjr6C8W3JKnPOvdgdxSKDLTv84Tgn5OJugbNXbRNaReuxYgvHEQvXCJT X+qKrxccUcCZzlfRgP04GkWsyXn1AZ9oX01ABE6ycYXce/dtOjTFhuBsk/U6yHw6G4n3 NYKA== X-Gm-Message-State: AOAM531Zqmz2OlUeLlj/A3MnL9offdL/GeOyAiyediS0G1tVULbnW/Qo /cTwaDYB4YrU59CDPDjeMrFRP3DRHRC0Nw== X-Google-Smtp-Source: ABdhPJx+8/AenvnBcExwEZRf0KhljG3vKx+5WKg5qzFjex7s64VgpSRc9LncTEdDstvRNWWR9oaMUw== X-Received: by 2002:a05:6e02:2144:: with SMTP id d4mr30553751ilv.11.1638728197216; Sun, 05 Dec 2021 10:16:37 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:9ea0:bb99:b16a:6159]) by smtp.gmail.com with ESMTPSA id z12sm5808164ilu.27.2021.12.05.10.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Dec 2021 10:16:36 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, nicolas@ndufresne.ca, Lucas Stach , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC 1/5] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Date: Sun, 5 Dec 2021 12:16:14 -0600 Message-Id: <20211205181618.1041699-2-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211205181618.1041699-1-aford173@gmail.com> References: <20211205181618.1041699-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the defines for the power domains provided by the VPU blk-ctrl on the i.MX8MQ. Signed-off-by: Lucas Stach --- include/dt-bindings/power/imx8mq-power.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h index 8a513bd9166e..9f7d0f1e7c32 100644 --- a/include/dt-bindings/power/imx8mq-power.h +++ b/include/dt-bindings/power/imx8mq-power.h @@ -18,4 +18,7 @@ #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 #define IMX8M_POWER_DOMAIN_PCIE2 10 +#define IMX8MQ_VPUBLK_PD_G1 0 +#define IMX8MQ_VPUBLK_PD_G2 1 + #endif From patchwork Sun Dec 5 18:16:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12657207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6F72C433F5 for ; Sun, 5 Dec 2021 18:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237164AbhLESUN (ORCPT ); Sun, 5 Dec 2021 13:20:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237133AbhLESUH (ORCPT ); Sun, 5 Dec 2021 13:20:07 -0500 Received: from mail-io1-xd2b.google.com (mail-io1-xd2b.google.com [IPv6:2607:f8b0:4864:20::d2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FF33C061714; Sun, 5 Dec 2021 10:16:40 -0800 (PST) Received: by mail-io1-xd2b.google.com with SMTP id m9so10467645iop.0; Sun, 05 Dec 2021 10:16:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tWudG/7p9Ihv/RchD2aqdeBvOMPxR3CBPXRYkrOCQIc=; b=Rta/hbYaQyn4KIRTC5NZcb5EmJDBuP6DlcpgmudYGUBaIaREtTQBqKrTNTn9EdCscp RfL3YWIiXlrjpuXAUBtJ8we2gJw3n++XYvGM5hTmZNX0svu1uFiz0aWSSOM/MdiYja4U nnMXsutHRNwAmklhoAjvPca1pY/f0crCHzG11+d8nVKy8yJFwczULj3qVVsmm143wxyb mIoXFuWvHVfVcXERBth0LxuPg+Skx0Oz2GIpNIBrHyaxIjK0LIvdRbvaeh+i7P1nzF0x xXRjG6mLrwk+nZUH3jVP8uwqCWDPSVDumz5a8LSdUQBPmZkvbfMwKQIBWOVzfKBuvfcB fIWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tWudG/7p9Ihv/RchD2aqdeBvOMPxR3CBPXRYkrOCQIc=; b=a9yBETayUhROMTZVbz+jZWnB6YqQ4W/o95JMHpcVHN4u2kA2FHI9x3JTMLcVv19UKw vVBGcq3lZ5g6o8ZAK3Ce+QewscjxzSBopSHAzRNYehZiUKSHK9uBBPRnmKd0QU4xUPpy xgFwZk5GsN4jGG22YUaX9I47xK0omzUYPtZN24NbrZvmFLfqgBJCfodCYp5rRYeo0Q/C DPB55O42vViVz6DX5Y6qf0i8+d9pB4rjlHT6q4KBJqUeSnq7d4htIJPI+zawrRJASHcv mmjmtG+NqPCf+Hfgu6S11yEHNon/eIrWJF1+hSJXUkBdIsUTPy3bMOejmge+segB7DwP MoXw== X-Gm-Message-State: AOAM533Y7if7nWoXZmqtm1/or0EGMYNKou5q1n3zbLLhANcY/ZT1UsQh K4vjl9xOXv1tI+GzX907dMe7j9tTchxOHw== X-Google-Smtp-Source: ABdhPJz76yYAqHOJ31ePlq8l+eSKZz2b7PQOgx+R+/rE+pERvqgyrdRgmvhM0sqqeHT5SBKrzvSo3A== X-Received: by 2002:a05:6638:2bb:: with SMTP id d27mr39777646jaq.66.1638728199307; Sun, 05 Dec 2021 10:16:39 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:9ea0:bb99:b16a:6159]) by smtp.gmail.com with ESMTPSA id z12sm5808164ilu.27.2021.12.05.10.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Dec 2021 10:16:38 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, nicolas@ndufresne.ca, Lucas Stach , Adam Ford , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC 2/5] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Date: Sun, 5 Dec 2021 12:16:15 -0600 Message-Id: <20211205181618.1041699-3-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211205181618.1041699-1-aford173@gmail.com> References: <20211205181618.1041699-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the DT binding for the i.MX8MQ VPU blk-ctrl. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- .../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..b8cfad0d7a1e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MQ VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-blk-ctrl + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 3 + maxItems: 3 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: g1 + - const: g2 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl", "syscon"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; + }; From patchwork Sun Dec 5 18:16:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12657209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A2E7C433EF for ; Sun, 5 Dec 2021 18:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237194AbhLESUQ (ORCPT ); Sun, 5 Dec 2021 13:20:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237149AbhLESUK (ORCPT ); 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Sun, 05 Dec 2021 10:16:41 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, nicolas@ndufresne.ca, Lucas Stach , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC 3/5] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl Date: Sun, 5 Dec 2021 12:16:16 -0600 Message-Id: <20211205181618.1041699-4-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211205181618.1041699-1-aford173@gmail.com> References: <20211205181618.1041699-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach --- drivers/soc/imx/imx8m-blk-ctrl.c | 67 ++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d9..66c879bcc66b 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -14,6 +14,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -498,6 +499,69 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), }; +static int imx8mq_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated and reset together with the VPUs. The + * reset and clock enable inputs to the ADB is a logical OR of the + * VPU bits. To avoid putting a improperly reset decoder on the bus + * while making the ADB work, we release G2 from reset, but only + * enable clocks to G1. + */ + regmap_update_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1), BIT(0)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(1)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { + [IMX8MQ_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MQ_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { + .max_reg = 0x14, + .power_notifier_fn = imx8mq_vpu_power_notifier, + .domains = imx8mq_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -505,6 +569,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mm-disp-blk-ctrl", .data = &imx8mm_disp_blk_ctl_dev_data + } ,{ + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data } ,{ /* Sentinel */ } From patchwork Sun Dec 5 18:16:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12657213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07B1FC433FE for ; Sun, 5 Dec 2021 18:16:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237271AbhLESUX (ORCPT ); Sun, 5 Dec 2021 13:20:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237160AbhLESUM (ORCPT ); Sun, 5 Dec 2021 13:20:12 -0500 Received: from mail-il1-x129.google.com (mail-il1-x129.google.com [IPv6:2607:f8b0:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBB48C0613F8; Sun, 5 Dec 2021 10:16:44 -0800 (PST) Received: by mail-il1-x129.google.com with SMTP id t8so8076222ilu.8; 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Sun, 05 Dec 2021 10:16:43 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:9ea0:bb99:b16a:6159]) by smtp.gmail.com with ESMTPSA id z12sm5808164ilu.27.2021.12.05.10.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Dec 2021 10:16:43 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, nicolas@ndufresne.ca, Adam Ford , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , Lucas Stach , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC 4/5] media: hantro: split i.MX8MQ G1 and G2 code Date: Sun, 5 Dec 2021 12:16:17 -0600 Message-Id: <20211205181618.1041699-5-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211205181618.1041699-1-aford173@gmail.com> References: <20211205181618.1041699-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The VPU in the i.MX8MQ is really the combination of Hantro G1 and Hantro G2. With the updated vpu-blk-ctrl, the power domains system can enable and disable them separately as well as pull them out of reset. This simplifies the code and lets them run independently. Signed-off-by: Adam Ford --- drivers/staging/media/hantro/hantro_drv.c | 4 +- drivers/staging/media/hantro/hantro_hw.h | 2 +- drivers/staging/media/hantro/imx8m_vpu_hw.c | 119 +++----------------- 3 files changed, 19 insertions(+), 106 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ab2467998d29..d803252a5aba 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -608,8 +608,8 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M - { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, - { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant, }, + { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index cff817ca8d22..122b83a16663 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -299,8 +299,8 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; -extern const struct hantro_variant imx8mq_vpu_variant; extern const struct hantro_variant px30_vpu_variant; extern const struct hantro_variant rk3036_vpu_variant; extern const struct hantro_variant rk3066_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index 1a43f6fceef9..c9f6e8472258 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -13,67 +13,6 @@ #include "hantro_g1_regs.h" #include "hantro_g2_regs.h" -#define CTRL_SOFT_RESET 0x00 -#define RESET_G1 BIT(1) -#define RESET_G2 BIT(0) - -#define CTRL_CLOCK_ENABLE 0x04 -#define CLOCK_G1 BIT(1) -#define CLOCK_G2 BIT(0) - -#define CTRL_G1_DEC_FUSE 0x08 -#define CTRL_G1_PP_FUSE 0x0c -#define CTRL_G2_DEC_FUSE 0x10 - -static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) -{ - u32 val; - - /* Assert */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val &= ~reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); - - udelay(2); - - /* Release */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val |= reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); -} - -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) -{ - u32 val; - - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); - val |= clock_bits; - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); -} - -static int imx8mq_runtime_resume(struct hantro_dev *vpu) -{ - int ret; - - ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); - if (ret) { - dev_err(vpu->dev, "Failed to enable clocks\n"); - return ret; - } - - imx8m_soft_reset(vpu, RESET_G1 | RESET_G2); - imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); - - /* Set values of the fuse registers */ - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); - - clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); - - return 0; -} - /* * Supported formats. */ @@ -209,27 +148,6 @@ static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) -{ - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; - - return 0; -} - -static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G1); -} - -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G2); -} - /* * Supported codec ops. */ @@ -237,19 +155,16 @@ static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { [HANTRO_MODE_MPEG2_DEC] = { .run = hantro_g1_mpeg2_dec_run, - .reset = imx8m_vpu_g1_reset, .init = hantro_mpeg2_dec_init, .exit = hantro_mpeg2_dec_exit, }, [HANTRO_MODE_VP8_DEC] = { .run = hantro_g1_vp8_dec_run, - .reset = imx8m_vpu_g1_reset, .init = hantro_vp8_dec_init, .exit = hantro_vp8_dec_exit, }, [HANTRO_MODE_H264_DEC] = { .run = hantro_g1_h264_dec_run, - .reset = imx8m_vpu_g1_reset, .init = hantro_h264_dec_init, .exit = hantro_h264_dec_exit, }, @@ -258,14 +173,12 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { [HANTRO_MODE_HEVC_DEC] = { .run = hantro_g2_hevc_dec_run, - .reset = imx8m_vpu_g2_reset, .init = hantro_hevc_dec_init, .exit = hantro_hevc_dec_exit, }, [HANTRO_MODE_VP9_DEC] = { .run = hantro_g2_vp9_dec_run, .done = hantro_g2_vp9_dec_done, - .reset = imx8m_vpu_g2_reset, .init = hantro_vp9_dec_init, .exit = hantro_vp9_dec_exit, }, @@ -275,7 +188,7 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { * VPU variants. */ -static const struct hantro_irq imx8mq_irqs[] = { +static const struct hantro_irq imx8mq_g1_irqs[] = { { "g1", imx8m_vpu_g1_irq }, }; @@ -283,10 +196,12 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { { "g2", imx8m_vpu_g2_irq }, }; -static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; -static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; +static const char * const imx8mq_g1_clk_names[] = { "g1" }; +static const char * const imx8mq_g1_reg_names[] = { "g1" }; +static const char * const imx8mq_g2_clk_names[] = { "g2" }; +static const char * const imx8mq_g2_reg_names[] = { "g2" }; -const struct hantro_variant imx8mq_vpu_variant = { +const struct hantro_variant imx8mq_vpu_g1_variant = { .dec_fmts = imx8m_vpu_dec_fmts, .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), .postproc_fmts = imx8m_vpu_postproc_fmts, @@ -295,14 +210,12 @@ const struct hantro_variant imx8mq_vpu_variant = { .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | HANTRO_H264_DECODER, .codec_ops = imx8mq_vpu_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, - .irqs = imx8mq_irqs, - .num_irqs = ARRAY_SIZE(imx8mq_irqs), - .clk_names = imx8mq_clk_names, - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), - .reg_names = imx8mq_reg_names, - .num_regs = ARRAY_SIZE(imx8mq_reg_names) + .irqs = imx8mq_g1_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_g1_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), + .reg_names = imx8mq_g1_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g1_reg_names), }; const struct hantro_variant imx8mq_vpu_g2_variant = { @@ -314,10 +227,10 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .postproc_ops = &hantro_g2_postproc_ops, .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, .irqs = imx8mq_g2_irqs, .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), - .clk_names = imx8mq_clk_names, - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + .reg_names = imx8mq_g2_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names), }; From patchwork Sun Dec 5 18:16:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12657211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F2D5C433EF for ; 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Sun, 05 Dec 2021 10:16:45 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, nicolas@ndufresne.ca, Adam Ford , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , Lucas Stach , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [RFC 5/5] arm64: dts: imx8mq: Split i.MX8MQ G1 and G2 with vpu-blk-ctrl Date: Sun, 5 Dec 2021 12:16:18 -0600 Message-Id: <20211205181618.1041699-6-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211205181618.1041699-1-aford173@gmail.com> References: <20211205181618.1041699-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org With the Hantro G1 and G2 now setup to run independently, update the device tree to enable it again. This requires the vpu-blk-ctrl node to be configured, and the clock-parents and clock-rates for the various VPU's to be moved into the pgc_vpu because they cannot get re-parented once enabled, and the pgc_vpu is the highest in the chain. Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 69 +++++++++++++++-------- 1 file changed, 45 insertions(+), 24 deletions(-) This clock rates and parents were moved to the pgc_vpu node because the vpu-blk-ctrl is expecting certain clocks to be operational, and they cannot be re-parented once they are runing. The datasheet and the TRM both show different potential clock rates for the G2 CODEC. It could be as low as 300MHZ or as high as 650 depending on what document is read, and the operating voltage of the hardware. Because of the uncertainty, the clock rates proposed here match those in NXP's 5.10 Release. https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8mq.dtsi?h=lf-5.10.y diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..0d3053bbfb2c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -711,7 +711,21 @@ pgc_gpu: power-domain@5 { pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <0>; }; pgc_disp: power-domain@7 { @@ -1432,30 +1446,37 @@ usb3_phy1: usb-phy@382f0040 { status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl", "syscon"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; }; pcie0: pcie@33800000 {