From patchwork Thu Dec 9 17:40:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8820C433EF for ; Thu, 9 Dec 2021 17:40:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234374AbhLIRo1 (ORCPT ); Thu, 9 Dec 2021 12:44:27 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:45749 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232038AbhLIRo1 (ORCPT ); Thu, 9 Dec 2021 12:44:27 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 2105A24000E; Thu, 9 Dec 2021 17:40:51 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 01/12] mtd: nand: mxic-ecc: Support SPI pipelined mode Date: Thu, 9 Dec 2021 18:40:35 +0100 Message-Id: <20211209174046.535229-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Introduce the support for another possible configuration: the ECC engine may work as DMA master (pipelined) and move itself the data to/from the NAND chip into the buffer, applying the necessary corrections/computations on the fly. This driver offers an ECC engine implementation that must be instatiated from a SPI controller driver. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/ecc-mxic.c | 210 +++++++++++++++++++++++++++++- include/linux/mtd/nand-ecc-mxic.h | 49 +++++++ 2 files changed, 258 insertions(+), 1 deletion(-) create mode 100644 include/linux/mtd/nand-ecc-mxic.h diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c index ea88a411ed70..8eacddfa8ac6 100644 --- a/drivers/mtd/nand/ecc-mxic.c +++ b/drivers/mtd/nand/ecc-mxic.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -40,7 +41,9 @@ #define INTRPT_SIG_EN 0x0C /* Host Controller Configuration */ #define HC_CONFIG 0x10 +#define DEV2MEM 0 /* TRANS_TYP_DMA in the spec */ #define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */ +#define MAPPING BIT(5) /* TRANS_TYP_MAPPING in the spec */ #define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */ #define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */ #define BURST_TYP_FIXED 0 @@ -87,6 +90,7 @@ struct mxic_ecc_engine { int irq; struct completion complete; struct nand_ecc_engine external_engine; + struct nand_ecc_engine pipelined_engine; struct mutex lock; }; @@ -104,6 +108,7 @@ struct mxic_ecc_ctx { u8 *oobwithstat; struct scatterlist sg[2]; struct nand_page_io_req *req; + unsigned int pageoffs; }; static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng) @@ -111,11 +116,19 @@ static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng) return container_of(eng, struct mxic_ecc_engine, external_engine); } +static struct mxic_ecc_engine *pip_ecc_eng_to_mxic(struct nand_ecc_engine *eng) +{ + return container_of(eng, struct mxic_ecc_engine, pipelined_engine); +} + static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand) { struct nand_ecc_engine *eng = nand->ecc.engine; - return ext_ecc_eng_to_mxic(eng); + if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL) + return ext_ecc_eng_to_mxic(eng); + else + return pip_ecc_eng_to_mxic(eng); } static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section, @@ -203,6 +216,31 @@ static irqreturn_t mxic_ecc_isr(int irq, void *dev_id) return IRQ_HANDLED; } +static struct device *mxic_ecc_get_engine_dev(struct device *dev) +{ + struct platform_device *eccpdev; + struct device_node *np; + + /* + * If the device node contains this property, it means the device does + * not represent the actual ECC engine. + */ + np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); + if (!np) + return dev; + + eccpdev = of_find_device_by_node(np); + if (!eccpdev) { + of_node_put(np); + return NULL; + } + + platform_device_put(eccpdev); + of_node_put(np); + + return &eccpdev->dev; +} + static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev) { struct mxic_ecc_engine *mxic = nand_to_mxic(nand); @@ -364,6 +402,42 @@ static int mxic_ecc_init_ctx_external(struct nand_device *nand) return 0; } +static int mxic_ecc_init_ctx_pipelined(struct nand_device *nand) +{ + struct mxic_ecc_engine *mxic = nand_to_mxic(nand); + struct mxic_ecc_ctx *ctx; + struct device *dev; + int ret; + + /* + * In the case of a pipelined engine, the device registering the ECC + * engine is not the actual ECC engine device but the host controller. + */ + dev = mxic_ecc_get_engine_dev(nand->ecc.engine->dev); + if (!dev) + return -EINVAL; + + dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n"); + + ret = mxic_ecc_init_ctx(nand, dev); + if (ret) + return ret; + + ctx = nand_to_ecc_ctx(nand); + + /* All steps should be handled in one go directly by the internal DMA */ + writel(ctx->steps, mxic->regs + CHUNK_CNT); + + /* + * Interleaved ECC scheme cannot be used otherwise factory bad block + * markers would be lost. A packed layout is mandatory. + */ + writel(BURST_TYP_INCREASING | ECC_PACKED | MAPPING, + mxic->regs + HC_CONFIG); + + return 0; +} + static void mxic_ecc_cleanup_ctx(struct nand_device *nand) { struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand); @@ -419,6 +493,18 @@ static int mxic_ecc_process_data(struct mxic_ecc_engine *mxic, return ret; } +int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng, + unsigned int direction, dma_addr_t dirmap) +{ + struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng); + + if (dirmap) + writel(dirmap, mxic->regs + HC_SLV_ADDR); + + return mxic_ecc_process_data(mxic, direction); +} +EXPORT_SYMBOL_GPL(mxic_ecc_process_data_pipelined); + static void mxic_ecc_extract_status_bytes(struct mxic_ecc_ctx *ctx) { u8 *buf = ctx->oobwithstat; @@ -598,6 +684,65 @@ static int mxic_ecc_finish_io_req_external(struct nand_device *nand, return mxic_ecc_count_biterrs(mxic, nand); } +/* Pipelined ECC engine helpers */ +static int mxic_ecc_prepare_io_req_pipelined(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct mxic_ecc_engine *mxic = nand_to_mxic(nand); + struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand); + int nents; + + if (req->mode == MTD_OPS_RAW) + return 0; + + nand_ecc_tweak_req(&ctx->req_ctx, req); + ctx->req = req; + + /* Copy the OOB buffer and add room for the ECC engine status bytes */ + mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in); + + sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen); + sg_set_buf(&ctx->sg[1], ctx->oobwithstat, + req->ooblen + (ctx->steps * STAT_BYTES)); + + nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL); + if (!nents) + return -EINVAL; + + mutex_lock(&mxic->lock); + + writel(sg_dma_address(&ctx->sg[0]), mxic->regs + SDMA_MAIN_ADDR); + writel(sg_dma_address(&ctx->sg[1]), mxic->regs + SDMA_SPARE_ADDR); + + return 0; +} + +static int mxic_ecc_finish_io_req_pipelined(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct mxic_ecc_engine *mxic = nand_to_mxic(nand); + struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand); + int ret = 0; + + if (req->mode == MTD_OPS_RAW) + return 0; + + mutex_unlock(&mxic->lock); + + dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL); + + if (req->type == NAND_PAGE_READ) { + mxic_ecc_extract_status_bytes(ctx); + mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in, + ctx->oobwithstat); + ret = mxic_ecc_count_biterrs(mxic, nand); + } + + nand_ecc_restore_req(&ctx->req_ctx, req); + + return ret; +} + static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = { .init_ctx = mxic_ecc_init_ctx_external, .cleanup_ctx = mxic_ecc_cleanup_ctx, @@ -605,6 +750,69 @@ static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = { .finish_io_req = mxic_ecc_finish_io_req_external, }; +static struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = { + .init_ctx = mxic_ecc_init_ctx_pipelined, + .cleanup_ctx = mxic_ecc_cleanup_ctx, + .prepare_io_req = mxic_ecc_prepare_io_req_pipelined, + .finish_io_req = mxic_ecc_finish_io_req_pipelined, +}; + +struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void) +{ + return &mxic_ecc_engine_pipelined_ops; +} +EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_ops); + +static struct platform_device * +mxic_ecc_get_pdev(struct platform_device *spi_pdev) +{ + struct platform_device *eng_pdev; + struct device_node *np; + + /* Retrieve the nand-ecc-engine phandle */ + np = of_parse_phandle(spi_pdev->dev.of_node, "nand-ecc-engine", 0); + if (!np) + return NULL; + + /* Jump to the engine's device node */ + eng_pdev = of_find_device_by_node(np); + of_node_put(np); + + return eng_pdev; +} + +void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng) +{ + struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng); + + platform_device_put(to_platform_device(mxic->dev)); +} +EXPORT_SYMBOL_GPL(mxic_ecc_put_pipelined_engine); + +struct nand_ecc_engine * +mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev) +{ + struct platform_device *eng_pdev; + struct mxic_ecc_engine *mxic; + + eng_pdev = mxic_ecc_get_pdev(spi_pdev); + if (!eng_pdev) + return ERR_PTR(-ENODEV); + + mxic = platform_get_drvdata(eng_pdev); + if (!mxic) { + platform_device_put(eng_pdev); + return ERR_PTR(-EPROBE_DEFER); + } + + return &mxic->pipelined_engine; +} +EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_engine); + +/* + * Only the external ECC engine is exported as the pipelined is SoC specific, so + * it is registered directly by the drivers that wrap it. + */ static int mxic_ecc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; diff --git a/include/linux/mtd/nand-ecc-mxic.h b/include/linux/mtd/nand-ecc-mxic.h new file mode 100644 index 000000000000..f3aa1ac82aed --- /dev/null +++ b/include/linux/mtd/nand-ecc-mxic.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright © 2019 Macronix + * Author: Miquèl Raynal + * + * Header for the Macronix external ECC engine. + */ + +#ifndef __MTD_NAND_ECC_MXIC_H__ +#define __MTD_NAND_ECC_MXIC_H__ + +#include +#include + +struct mxic_ecc_engine; + +#if IS_ENABLED(CONFIG_MTD_NAND_ECC_MXIC) + +struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void); +struct nand_ecc_engine *mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev); +void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng); +int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng, + unsigned int direction, dma_addr_t dirmap); + +#else /* !CONFIG_MTD_NAND_ECC_MXIC */ + +static inline struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void) +{ + return NULL; +} + +static inline struct nand_ecc_engine * +mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng) {} + +static inline int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng, + unsigned int direction, + dma_addr_t dirmap) +{ + return -EOPNOTSUPP; +} + +#endif /* CONFIG_MTD_NAND_ECC_MXIC */ + +#endif /* __MTD_NAND_ECC_MXIC_H__ */ From patchwork Thu Dec 9 17:40:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFEE8C4332F for ; Thu, 9 Dec 2021 17:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232038AbhLIRo3 (ORCPT ); Thu, 9 Dec 2021 12:44:29 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:42607 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236876AbhLIRo3 (ORCPT ); Thu, 9 Dec 2021 12:44:29 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 3AE9024000A; Thu, 9 Dec 2021 17:40:53 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 02/12] mtd: spinand: Delay a little bit the dirmap creation Date: Thu, 9 Dec 2021 18:40:36 +0100 Message-Id: <20211209174046.535229-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As we will soon tweak the dirmap creation to act a little bit differently depending on the picked ECC engine, we need to initialize dirmaps after ECC engines. This should not have any effect as dirmaps are not yet used at this point. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 7027c09925e2..715cad26fdef 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1209,14 +1209,6 @@ static int spinand_init(struct spinand_device *spinand) if (ret) goto err_free_bufs; - ret = spinand_create_dirmaps(spinand); - if (ret) { - dev_err(dev, - "Failed to create direct mappings for read/write operations (err = %d)\n", - ret); - goto err_manuf_cleanup; - } - ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); if (ret) goto err_manuf_cleanup; @@ -1251,6 +1243,14 @@ static int spinand_init(struct spinand_device *spinand) mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; + ret = spinand_create_dirmaps(spinand); + if (ret) { + dev_err(dev, + "Failed to create direct mappings for read/write operations (err = %d)\n", + ret); + goto err_cleanup_ecc_engine; + } + return 0; err_cleanup_ecc_engine: From patchwork Thu Dec 9 17:40:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23108C433F5 for ; Thu, 9 Dec 2021 17:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237480AbhLIRog (ORCPT ); Thu, 9 Dec 2021 12:44:36 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:33369 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237141AbhLIRoa (ORCPT ); Thu, 9 Dec 2021 12:44:30 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id D7C76240003; Thu, 9 Dec 2021 17:40:54 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 03/12] spi: spi-mem: Create a helper to gather all the supports_op checks Date: Thu, 9 Dec 2021 18:40:37 +0100 Message-Id: <20211209174046.535229-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org So far we check the support for: - regular operations - dtr operations Soon, we will also need to check the support for ECC operations. As the combinatorial will increase exponentially, let's gather all the checks in a single generic function. This new helper will be called by the exported functions, directly used by the different drivers. Then, in a second time, we will add an ECC check and allow this new helper to be directly used to avoid increasing dramatically the number of new helpers needed to cover the {dtr-on/dtr-off, ecc-on/ecc-off} situations, and perhaps others too. It will always be possible to create abstraction helpers in the future if a particular combination is regularly used. Signed-off-by: Miquel Raynal --- drivers/spi/spi-mem.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 37f4443ce9a0..013efaaaac75 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -160,26 +160,36 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, return true; } +static bool spi_mem_generic_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op, + bool dtr) +{ + if (!dtr) { + if (op->cmd.dtr || op->addr.dtr || + op->dummy.dtr || op->data.dtr) + return false; + + if (op->cmd.nbytes != 1) + return false; + } else { + if (op->cmd.nbytes != 2) + return false; + } + + return spi_mem_check_buswidth(mem, op); +} + bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->cmd.nbytes != 2) - return false; - - return spi_mem_check_buswidth(mem, op); + return spi_mem_generic_supports_op(mem, op, true); } EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) - return false; - - if (op->cmd.nbytes != 1) - return false; - - return spi_mem_check_buswidth(mem, op); + return spi_mem_generic_supports_op(mem, op, false); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); From patchwork Thu Dec 9 17:40:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F3BC433EF for ; Thu, 9 Dec 2021 17:41:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241157AbhLIRof (ORCPT ); Thu, 9 Dec 2021 12:44:35 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:53605 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237473AbhLIRoc (ORCPT ); Thu, 9 Dec 2021 12:44:32 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id CF0B424000C; Thu, 9 Dec 2021 17:40:56 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 04/12] spi: spi-mem: Add an ecc_en parameter to the spi_mem_op structure Date: Thu, 9 Dec 2021 18:40:38 +0100 Message-Id: <20211209174046.535229-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Soon the SPI-NAND core will need a way to request a SPI controller to enable ECC support for a given operation. This is because of the pipelined integration of certain ECC engines, which are directly managed by the SPI controller itself. Introduce a spi_mem_op additional field for this purpose: ecc_en. So far this field is left unset and checked to be false by all the SPI controller drivers in their ->supports_op() hook, as they all call spi_mem_default/dtr_supports_op(). Signed-off-by: Miquel Raynal --- drivers/spi/spi-mem.c | 11 ++++++++--- include/linux/spi/spi-mem.h | 3 +++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 013efaaaac75..9e06cd918273 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -162,7 +162,7 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, static bool spi_mem_generic_supports_op(struct spi_mem *mem, const struct spi_mem_op *op, - bool dtr) + bool dtr, bool ecc) { if (!dtr) { if (op->cmd.dtr || op->addr.dtr || @@ -176,20 +176,25 @@ static bool spi_mem_generic_supports_op(struct spi_mem *mem, return false; } + if (!ecc) { + if (op->ecc_en) + return false; + } + return spi_mem_check_buswidth(mem, op); } bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - return spi_mem_generic_supports_op(mem, op, true); + return spi_mem_generic_supports_op(mem, op, true, false); } EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - return spi_mem_generic_supports_op(mem, op, false); + return spi_mem_generic_supports_op(mem, op, false, false); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..3be594be24c0 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -94,6 +94,7 @@ enum spi_mem_data_dir { * operation does not involve transferring data * @data.buf.in: input buffer (must be DMA-able) * @data.buf.out: output buffer (must be DMA-able) + * @ecc_en: error correction is required */ struct spi_mem_op { struct { @@ -126,6 +127,8 @@ struct spi_mem_op { const void *out; } buf; } data; + + bool ecc_en; }; #define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ From patchwork Thu Dec 9 17:40:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0B68C4321E for ; Thu, 9 Dec 2021 17:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237627AbhLIRoh (ORCPT ); Thu, 9 Dec 2021 12:44:37 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:37447 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237514AbhLIRod (ORCPT ); Thu, 9 Dec 2021 12:44:33 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 31EE6240008; Thu, 9 Dec 2021 17:40:58 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 05/12] spi: spi-mem: Export the spi_mem_generic_supports_op() helper Date: Thu, 9 Dec 2021 18:40:39 +0100 Message-Id: <20211209174046.535229-6-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The combination of checks against the number of supported operations is going to increase exponentially each time we add a new parameter. So far we only had a dtr parameter. Now we are introducing an ECC parameter. We need to make this helper available for drivers with specific needs, instead of creating another set of helpers each time we want to check something new. In the future if we see that many different drivers use the same parameter values, we might be tempted to create a specific helper for that. But for now, let's just make the generic one available. Signed-off-by: Miquel Raynal --- drivers/spi/spi-mem.c | 7 ++++--- include/linux/spi/spi-mem.h | 13 +++++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 9e06cd918273..48b55395178f 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -160,9 +160,9 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, return true; } -static bool spi_mem_generic_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op, - bool dtr, bool ecc) +bool spi_mem_generic_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op, + bool dtr, bool ecc) { if (!dtr) { if (op->cmd.dtr || op->addr.dtr || @@ -183,6 +183,7 @@ static bool spi_mem_generic_supports_op(struct spi_mem *mem, return spi_mem_check_buswidth(mem, op); } +EXPORT_SYMBOL_GPL(spi_mem_generic_supports_op); bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 3be594be24c0..07f637cbe77d 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -320,6 +320,10 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, const struct spi_mem_op *op, struct sg_table *sg); +bool spi_mem_generic_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op, + bool dtr, bool ecc); + bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); @@ -327,6 +331,7 @@ bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); #else + static inline int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, const struct spi_mem_op *op, @@ -342,6 +347,14 @@ spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, { } +static inline +bool spi_mem_generic_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op, + bool dtr, bool ecc) +{ + return false; +} + static inline bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) From patchwork Thu Dec 9 17:40:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 456BAC43219 for ; Thu, 9 Dec 2021 17:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236876AbhLIRog (ORCPT ); Thu, 9 Dec 2021 12:44:36 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:51561 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238158AbhLIRof (ORCPT ); Thu, 9 Dec 2021 12:44:35 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 76E5C240002; Thu, 9 Dec 2021 17:40:59 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 06/12] mtd: spinand: Create direct mapping descriptors for ECC operations Date: Thu, 9 Dec 2021 18:40:40 +0100 Message-Id: <20211209174046.535229-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In order for pipelined ECC engines to be able to enable/disable the ECC engine only when needed and avoid races when future parallel-operations will be supported, we need to provide the information about the use of the ECC engine in the direct mapping hooks. As direct mapping configurations are meant to be static, it is best to create two new mappings: one for regular 'raw' accesses and one for accesses involving correction. It is up to the driver to use or not the new ECC enable boolean contained in the spi-mem operation. As dirmaps are not free (they consume a few pages of MMIO address space) and because these extra entries are only meant to be used by pipelined engines, let's limit their use to this specific type of engine and save a bit of memory with all the other setups. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- include/linux/mtd/spinand.h | 2 ++ 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 715cad26fdef..eb999e47e978 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, } } - rdesc = spinand->dirmaps[req->pos.plane].rdesc; + if (req->mode == MTD_OPS_RAW) + rdesc = spinand->dirmaps[req->pos.plane].rdesc; + else + rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; while (nbytes) { ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); @@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, req->ooblen); } - wdesc = spinand->dirmaps[req->pos.plane].wdesc; + if (req->mode == MTD_OPS_RAW) + wdesc = spinand->dirmaps[req->pos.plane].wdesc; + else + wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; while (nbytes) { ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); @@ -866,6 +872,31 @@ static int spinand_create_dirmap(struct spinand_device *spinand, spinand->dirmaps[plane].rdesc = desc; + if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { + spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; + spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; + + return 0; + } + + info.op_tmpl = *spinand->op_templates.update_cache; + info.op_tmpl.ecc_en = true; + desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, + spinand->spimem, &info); + if (IS_ERR(desc)) + return PTR_ERR(desc); + + spinand->dirmaps[plane].wdesc_ecc = desc; + + info.op_tmpl = *spinand->op_templates.read_cache; + info.op_tmpl.ecc_en = true; + desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, + spinand->spimem, &info); + if (IS_ERR(desc)) + return PTR_ERR(desc); + + spinand->dirmaps[plane].rdesc_ecc = desc; + return 0; } diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6988956b8492..3aa28240a77f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -389,6 +389,8 @@ struct spinand_info { struct spinand_dirmap { struct spi_mem_dirmap_desc *wdesc; struct spi_mem_dirmap_desc *rdesc; + struct spi_mem_dirmap_desc *wdesc_ecc; + struct spi_mem_dirmap_desc *rdesc_ecc; }; /** From patchwork Thu Dec 9 17:40:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12667999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8564C433FE for ; Thu, 9 Dec 2021 17:41:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234955AbhLIRoi (ORCPT ); Thu, 9 Dec 2021 12:44:38 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:50695 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237473AbhLIRog (ORCPT ); Thu, 9 Dec 2021 12:44:36 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id BAA48240006; Thu, 9 Dec 2021 17:41:00 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal , stable@vger.kernel.org, Mason Yang , Zhengxun Li Subject: [PATCH v4 07/12] spi: mxic: Fix the transmit path Date: Thu, 9 Dec 2021 18:40:41 +0100 Message-Id: <20211209174046.535229-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org By working with external hardware ECC engines, we figured out that Under certain circumstances, it is needed for the SPI controller to check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit path (not only in the receive path). The delay penalty being negligible, move this code in the common path. Fixes: b942d80b0a39 ("spi: Add MXIC controller driver") Cc: stable@vger.kernel.org Suggested-by: Mason Yang Signed-off-by: Miquel Raynal Reviewed-by: Zhengxun Li Reviewed-by: Mark Brown --- drivers/spi/spi-mxic.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 45889947afed..03fce4493aa7 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, writel(data, mxic->regs + TXD(nbytes % 4)); + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_TX_EMPTY, 0, USEC_PER_SEC); + if (ret) + return ret; + + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_RX_NOT_EMPTY, 0, + USEC_PER_SEC); + if (ret) + return ret; + + data = readl(mxic->regs + RXD); if (rxbuf) { - ret = readl_poll_timeout(mxic->regs + INT_STS, sts, - sts & INT_TX_EMPTY, 0, - USEC_PER_SEC); - if (ret) - return ret; - - ret = readl_poll_timeout(mxic->regs + INT_STS, sts, - sts & INT_RX_NOT_EMPTY, 0, - USEC_PER_SEC); - if (ret) - return ret; - - data = readl(mxic->regs + RXD); data >>= (8 * (4 - nbytes)); memcpy(rxbuf + pos, &data, nbytes); - WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); - } else { - readl(mxic->regs + RXD); } WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); From patchwork Thu Dec 9 17:40:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12668001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47E17C433EF for ; Thu, 9 Dec 2021 17:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238752AbhLIRoj (ORCPT ); Thu, 9 Dec 2021 12:44:39 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:35991 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237151AbhLIRoh (ORCPT ); Thu, 9 Dec 2021 12:44:37 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 583C224000C; Thu, 9 Dec 2021 17:41:02 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 08/12] spi: mxic: Create a helper to configure the controller before an operation Date: Thu, 9 Dec 2021 18:40:42 +0100 Message-Id: <20211209174046.535229-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Create the mxic_spi_set_hc_cfg() helper to configure the HC_CFG register. This helper will soon be used by the dirmap implementation and having this code factorized out earlier will clarify this addition. Signed-off-by: Miquel Raynal Reviewed-by: Mark Brown --- drivers/spi/spi-mxic.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 03fce4493aa7..068543c40ce7 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -280,6 +280,22 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) +{ + int nio = 1; + + if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL)) + nio = 8; + else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) + nio = 4; + else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) + nio = 2; + + return flags | HC_CFG_NIO(nio) | + HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1); +} + static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, void *rxbuf, unsigned int len) { @@ -357,7 +373,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); - int nio = 1, i, ret; + int i, ret; u32 ss_ctrl; u8 addr[8], cmd[2]; @@ -365,18 +381,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, if (ret) return ret; - if (mem->spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL)) - nio = 8; - else if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) - nio = 4; - else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) - nio = 2; - - writel(HC_CFG_NIO(nio) | - HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) | - HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) | - HC_CFG_MAN_CS_EN, + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), mxic->regs + HC_CFG); + writel(HC_EN_BIT, mxic->regs + HC_EN); ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) | From patchwork Thu Dec 9 17:40:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12668003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E1B4C433FE for ; Thu, 9 Dec 2021 17:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237631AbhLIRoj (ORCPT ); Thu, 9 Dec 2021 12:44:39 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:50695 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234653AbhLIRoi (ORCPT ); Thu, 9 Dec 2021 12:44:38 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 7FFF524000D; Thu, 9 Dec 2021 17:41:03 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 09/12] spi: mxic: Create a helper to ease the start of an operation Date: Thu, 9 Dec 2021 18:40:43 +0100 Message-Id: <20211209174046.535229-10-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Create the mxic_spi_mem_prep_op_cfg() helper to provide the content to write to the register controlling the next IO command. This helper will soon be used by the dirmap implementation and having this code factorized out earlier will clarify this addition. Signed-off-by: Miquel Raynal Reviewed-by: Mark Brown --- drivers/spi/spi-mxic.c | 53 +++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 068543c40ce7..3c4e64cbe812 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -296,6 +296,33 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1); } +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op) +{ + u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | + OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | + (op->cmd.dtr ? OP_CMD_DDR : 0); + + if (op->addr.nbytes) + cfg |= OP_ADDR_BYTES(op->addr.nbytes) | + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | + (op->addr.dtr ? OP_ADDR_DDR : 0); + + if (op->dummy.nbytes) + cfg |= OP_DUMMY_CYC(op->dummy.nbytes); + + if (op->data.nbytes) { + cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | + (op->data.dtr ? OP_DATA_DDR : 0); + if (op->data.dir == SPI_MEM_DATA_IN) { + cfg |= OP_READ; + if (op->data.dtr) + cfg |= OP_DQS_EN; + } + } + + return cfg; +} + static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, void *rxbuf, unsigned int len) { @@ -374,7 +401,6 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, { struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); int i, ret; - u32 ss_ctrl; u8 addr[8], cmd[2]; ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); @@ -386,29 +412,8 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, writel(HC_EN_BIT, mxic->regs + HC_EN); - ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) | - OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | - (op->cmd.dtr ? OP_CMD_DDR : 0); - - if (op->addr.nbytes) - ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) | - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | - (op->addr.dtr ? OP_ADDR_DDR : 0); - - if (op->dummy.nbytes) - ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes); - - if (op->data.nbytes) { - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | - (op->data.dtr ? OP_DATA_DDR : 0); - if (op->data.dir == SPI_MEM_DATA_IN) { - ss_ctrl |= OP_READ; - if (op->data.dtr) - ss_ctrl |= OP_DQS_EN; - } - } - - writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select)); + writel(mxic_spi_mem_prep_op_cfg(op), + mxic->regs + SS_CTRL(mem->spi->chip_select)); writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, mxic->regs + HC_CFG); From patchwork Thu Dec 9 17:40:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12668005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2FF7C433EF for ; Thu, 9 Dec 2021 17:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241570AbhLIRol (ORCPT ); Thu, 9 Dec 2021 12:44:41 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:35991 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241380AbhLIRok (ORCPT ); Thu, 9 Dec 2021 12:44:40 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id AE212240002; Thu, 9 Dec 2021 17:41:04 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal , Zhengxun Li Subject: [PATCH v4 10/12] spi: mxic: Add support for direct mapping Date: Thu, 9 Dec 2021 18:40:44 +0100 Message-Id: <20211209174046.535229-11-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Implement the ->dirmap_create() and ->dirmap_read/write() hooks to provide a fast path for read and write accesses. Signed-off-by: Miquel Raynal Tested-by: Zhengxun Li Reviewed-by: Zhengxun Li Reviewed-by: Mark Brown --- drivers/spi/spi-mxic.c | 112 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 109 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 3c4e64cbe812..485a7f2afb44 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -172,6 +172,11 @@ struct mxic_spi { struct clk *send_dly_clk; void __iomem *regs; u32 cur_speed_hz; + struct { + void __iomem *map; + dma_addr_t dma; + size_t size; + } linear; }; static int mxic_spi_clk_enable(struct mxic_spi *mxic) @@ -296,7 +301,8 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1); } -static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op) +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op, + unsigned int data_len) { u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | @@ -310,7 +316,8 @@ static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op) if (op->dummy.nbytes) cfg |= OP_DUMMY_CYC(op->dummy.nbytes); - if (op->data.nbytes) { + /* Direct mapping data.nbytes field is not populated */ + if (data_len) { cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | (op->data.dtr ? OP_DATA_DDR : 0); if (op->data.dir == SPI_MEM_DATA_IN) { @@ -371,6 +378,77 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, return 0; } +static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, void *buf) +{ + struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + int ret; + u32 sts; + + if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) + return -EINVAL; + + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), + mxic->regs + LRD_CFG); + writel(desc->info.offset + offs, mxic->regs + LRD_ADDR); + len = min_t(size_t, len, mxic->linear.size); + writel(len, mxic->regs + LRD_RANGE); + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | + LMODE_SLV_ACT(desc->mem->spi->chip_select) | + LMODE_EN, + mxic->regs + LRD_CTRL); + + memcpy_fromio(buf, mxic->linear.map, len); + + writel(INT_LRD_DIS, mxic->regs + INT_STS); + writel(0, mxic->regs + LRD_CTRL); + + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_LRD_DIS, 0, USEC_PER_SEC); + if (ret) + return ret; + + return len; +} + +static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, + const void *buf) +{ + struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + u32 sts; + int ret; + + if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) + return -EINVAL; + + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), + mxic->regs + LWR_CFG); + writel(desc->info.offset + offs, mxic->regs + LWR_ADDR); + len = min_t(size_t, len, mxic->linear.size); + writel(len, mxic->regs + LWR_RANGE); + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | + LMODE_SLV_ACT(desc->mem->spi->chip_select) | + LMODE_EN, + mxic->regs + LWR_CTRL); + + memcpy_toio(mxic->linear.map, buf, len); + + writel(INT_LWR_DIS, mxic->regs + INT_STS); + writel(0, mxic->regs + LWR_CTRL); + + ret = readl_poll_timeout(mxic->regs + INT_STS, sts, + sts & INT_LWR_DIS, 0, USEC_PER_SEC); + if (ret) + return ret; + + return len; +} + static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -396,6 +474,22 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, return spi_mem_dtr_supports_op(mem, op); } +static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); + + if (!mxic->linear.map) + return -EINVAL; + + if (desc->info.offset + desc->info.length > U32_MAX) + return -EINVAL; + + if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl)) + return -EOPNOTSUPP; + + return 0; +} + static int mxic_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -412,7 +506,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, writel(HC_EN_BIT, mxic->regs + HC_EN); - writel(mxic_spi_mem_prep_op_cfg(op), + writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes), mxic->regs + SS_CTRL(mem->spi->chip_select)); writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, @@ -454,6 +548,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, static const struct spi_controller_mem_ops mxic_spi_mem_ops = { .supports_op = mxic_spi_mem_supports_op, .exec_op = mxic_spi_mem_exec_op, + .dirmap_create = mxic_spi_mem_dirmap_create, + .dirmap_read = mxic_spi_mem_dirmap_read, + .dirmap_write = mxic_spi_mem_dirmap_write, }; static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) @@ -583,6 +680,15 @@ static int mxic_spi_probe(struct platform_device *pdev) if (IS_ERR(mxic->regs)) return PTR_ERR(mxic->regs); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); + mxic->linear.map = devm_ioremap_resource(&pdev->dev, res); + if (!IS_ERR(mxic->linear.map)) { + mxic->linear.dma = res->start; + mxic->linear.size = resource_size(res); + } else { + mxic->linear.map = NULL; + } + pm_runtime_enable(&pdev->dev); master->auto_runtime_pm = true; From patchwork Thu Dec 9 17:40:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12668007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D861C433F5 for ; Thu, 9 Dec 2021 17:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237486AbhLIRom (ORCPT ); Thu, 9 Dec 2021 12:44:42 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:34707 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241534AbhLIRol (ORCPT ); Thu, 9 Dec 2021 12:44:41 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 14A87240006; Thu, 9 Dec 2021 17:41:05 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 11/12] spi: mxic: Use spi_mem_generic_supports_op() Date: Thu, 9 Dec 2021 18:40:45 +0100 Message-Id: <20211209174046.535229-12-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This driver can be simplified a little bit by using spi_mem_generic_supports_op() instead of the spi_mem_default/dtr_supports_op() couple. The all_false boolean is inverted to become a dtr boolean, which tacks if at least one of the operation member uses dtr mode. The idea behind this change is to simplify the introduction of the pipelined ECC engine. Signed-off-by: Miquel Raynal --- drivers/spi/spi-mxic.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 485a7f2afb44..84534733eb36 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -452,7 +452,7 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - bool all_false; + bool dtr; if (op->data.buswidth > 8 || op->addr.buswidth > 8 || op->dummy.buswidth > 8 || op->cmd.buswidth > 8) @@ -465,13 +465,9 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, if (op->addr.nbytes > 7) return false; - all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && - !op->data.dtr; + dtr = op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; - if (all_false) - return spi_mem_default_supports_op(mem, op); - else - return spi_mem_dtr_supports_op(mem, op); + return spi_mem_generic_supports_op(mem, op, dtr, false); } static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) From patchwork Thu Dec 9 17:40:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12668009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7694C43217 for ; Thu, 9 Dec 2021 17:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237151AbhLIRon (ORCPT ); Thu, 9 Dec 2021 12:44:43 -0500 Received: from relay10.mail.gandi.net ([217.70.178.230]:45283 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238397AbhLIRon (ORCPT ); Thu, 9 Dec 2021 12:44:43 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 463AD240003; Thu, 9 Dec 2021 17:41:07 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Julien Su , Jaime Liao , Miquel Raynal Subject: [PATCH v4 12/12] spi: mxic: Add support for pipelined ECC operations Date: Thu, 9 Dec 2021 18:40:46 +0100 Message-Id: <20211209174046.535229-13-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211209174046.535229-1-miquel.raynal@bootlin.com> References: <20211209174046.535229-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some SPI-NAND chips do not have a proper on-die ECC engine providing error correction/detection. This is particularly an issue on embedded devices with limited resources because all the computations must happen in software, unless an external hardware engine is provided. These external engines are new and can be of two categories: external or pipelined. Macronix is providing both, the former being already supported. The second, however, is very SoC implementation dependent and must be instantiated by the SPI host controller directly. An entire subsystem has been contributed to support these engines which makes the insertion into another subsystem such as SPI quite straightforward without the need for a lot of specific functions. Signed-off-by: Miquel Raynal Reviewed-by: Mark Brown --- drivers/spi/Kconfig | 2 +- drivers/spi/spi-mxic.c | 117 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 114 insertions(+), 5 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 83e352b0c8f9..bff75629e872 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -856,7 +856,7 @@ config SPI_SYNQUACER config SPI_MXIC tristate "Macronix MX25F0A SPI controller" - depends on SPI_MASTER + depends on SPI_MASTER && MTD_NAND_ECC help This selects the Macronix MX25F0A SPI controller driver. diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 84534733eb36..cfd1af3904dd 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -167,6 +169,7 @@ #define HW_TEST(x) (0xe0 + ((x) * 4)) struct mxic_spi { + struct device *dev; struct clk *ps_clk; struct clk *send_clk; struct clk *send_dly_clk; @@ -177,6 +180,12 @@ struct mxic_spi { dma_addr_t dma; size_t size; } linear; + + struct { + bool use_pipelined_conf; + struct nand_ecc_engine *pipelined_engine; + void *ctx; + } ecc; }; static int mxic_spi_clk_enable(struct mxic_spi *mxic) @@ -400,7 +409,15 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, LMODE_EN, mxic->regs + LRD_CTRL); - memcpy_fromio(buf, mxic->linear.map, len); + if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.ecc_en) { + ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, + NAND_PAGE_READ, + mxic->linear.dma + offs); + if (ret) + return ret; + } else { + memcpy_fromio(buf, mxic->linear.map, len); + } writel(INT_LRD_DIS, mxic->regs + INT_STS); writel(0, mxic->regs + LRD_CTRL); @@ -436,7 +453,15 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, LMODE_EN, mxic->regs + LWR_CTRL); - memcpy_toio(mxic->linear.map, buf, len); + if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.ecc_en) { + ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, + NAND_PAGE_WRITE, + mxic->linear.dma + offs); + if (ret) + return ret; + } else { + memcpy_toio(mxic->linear.map, buf, len); + } writel(INT_LWR_DIS, mxic->regs + INT_STS); writel(0, mxic->regs + LWR_CTRL); @@ -452,7 +477,7 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - bool dtr; + bool dtr, ecc; if (op->data.buswidth > 8 || op->addr.buswidth > 8 || op->dummy.buswidth > 8 || op->cmd.buswidth > 8) @@ -466,8 +491,9 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, return false; dtr = op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; + ecc = op->ecc_en; - return spi_mem_generic_supports_op(mem, op, dtr, false); + return spi_mem_generic_supports_op(mem, op, dtr, ecc); } static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) @@ -611,6 +637,80 @@ static int mxic_spi_transfer_one(struct spi_master *master, return 0; } +/* ECC wrapper */ +static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand) +{ + struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops(); + struct mxic_spi *mxic = nand->ecc.engine->priv; + + mxic->ecc.use_pipelined_conf = true; + + return ops->init_ctx(nand); +} + +static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand) +{ + struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops(); + struct mxic_spi *mxic = nand->ecc.engine->priv; + + mxic->ecc.use_pipelined_conf = false; + + ops->cleanup_ctx(nand); +} + +static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops(); + + return ops->prepare_io_req(nand, req); +} + +static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops(); + + return ops->finish_io_req(nand, req); +} + +static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = { + .init_ctx = mxic_spi_mem_ecc_init_ctx, + .cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx, + .prepare_io_req = mxic_spi_mem_ecc_prepare_io_req, + .finish_io_req = mxic_spi_mem_ecc_finish_io_req, +}; + +static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic) +{ + if (mxic->ecc.pipelined_engine) { + mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine); + nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine); + } +} + +static int mxic_spi_mem_ecc_probe(struct platform_device *pdev, + struct mxic_spi *mxic) +{ + struct nand_ecc_engine *eng; + + if (!mxic_ecc_get_pipelined_ops()) + return -EOPNOTSUPP; + + eng = mxic_ecc_get_pipelined_engine(pdev); + if (IS_ERR(eng)) + return PTR_ERR(eng); + + eng->dev = &pdev->dev; + eng->integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; + eng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops; + eng->priv = mxic; + mxic->ecc.pipelined_engine = eng; + nand_ecc_register_on_host_hw_engine(eng); + + return 0; +} + static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); @@ -656,6 +756,7 @@ static int mxic_spi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); mxic = spi_master_get_devdata(master); + mxic->dev = &pdev->dev; master->dev.of_node = pdev->dev.of_node; @@ -701,6 +802,12 @@ static int mxic_spi_probe(struct platform_device *pdev) mxic_spi_hw_init(mxic); + ret = mxic_spi_mem_ecc_probe(pdev, mxic); + if (ret == -EPROBE_DEFER) { + pm_runtime_disable(&pdev->dev); + return ret; + } + ret = spi_register_master(master); if (ret) { dev_err(&pdev->dev, "spi_register_master failed\n"); @@ -713,8 +820,10 @@ static int mxic_spi_probe(struct platform_device *pdev) static int mxic_spi_remove(struct platform_device *pdev) { struct spi_master *master = platform_get_drvdata(pdev); + struct mxic_spi *mxic = spi_master_get_devdata(master); pm_runtime_disable(&pdev->dev); + mxic_spi_mem_ecc_remove(mxic); spi_unregister_master(master); return 0;