From patchwork Fri Dec 21 16:02:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740653 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A31113B5 for ; Fri, 21 Dec 2018 16:05:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE92F26E54 for ; Fri, 21 Dec 2018 16:05:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E25522846C; Fri, 21 Dec 2018 16:05:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4209726E54 for ; Fri, 21 Dec 2018 16:05:09 +0000 (UTC) Received: from localhost ([::1]:46408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNIS-0002ZW-QR for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Dec 2018 11:05:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNGw-0001FE-F1 for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:03:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gaNGv-0003xc-KD for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:03:34 -0500 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]:40302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gaNGv-0003xD-Fu for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:03:33 -0500 Received: by mail-qt1-x833.google.com with SMTP id k12so6181895qtf.7 for ; Fri, 21 Dec 2018 08:03:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:cc:from:to; bh=ACO3xZNidVZe/8lJl6dILcNtHXgshs90c10YxGoZDdw=; b=m6osPkrjRIu6a3iNHn6MtUW1XCASEenefbGAoK8mOG816ItfYf65/lKbj9EF9Q7K3L WHUkH1LDGpJzMKqBE7SicS9eLGFEv/KvHVwyTryAmvwgLG7cqeH4VNIUj8tJe/oGHQ9k DSiHndLzTw05J7fyyaSHJdwpeKLUFskPZzI0DykuhyBLnzABEFkSpevOVoOZkDIxDnmY RknpnmO+RB5LNueETX0uq2CAyWxqeb+mm78mpPLJDc5QvNGRTeOWLZl4InYNyJYK+CBl ErmjgwG0AOJBmSl3TMe1sMqgPJzUp/K2XRdIWGeXqHeq4SDe8AjwJQcu7BDIM2kXr2io f/lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=ACO3xZNidVZe/8lJl6dILcNtHXgshs90c10YxGoZDdw=; b=TKeqH3/viVLYIa7d1weHVs2wDmm+I5nxHuyIXBf1kL5emlSWn0+8XZuHLngCUty4ra WsgYZ+06uobmpSsaOt0lCLFllnDBrCiJA/Jf1l1uDejoV7A4QppPq7jIXtBIQ8wLXx9/ tmlC9pc8HMc/15AOgcvMKDCbul/KNotWhu6fSOYrXNkSeKpoBL+knYz++4smO3wJ0Xtw EIZ/7vlWt7urOgnjN59yUAbjrama8SGqI0Tt3yJPdRsCjPvelB5RINeVHxZf+wRV2JhW EYbyHbrqJsu/r9q9lc37Ud1Cmi815vBroc1b2KInT7u8w2NYjo3d0lbPSjY8o+EJqbI8 HjIA== X-Gm-Message-State: AA+aEWb2F8AUyY7dZB0KaXbd2QLx6rrO2bfw8ylb8a4AbXxSQSZ3SJYQ lQRN4QCY4UPg/6PWQibkehpspydfD3Y= X-Google-Smtp-Source: ALg8bN6r3Hz+1BmKWUDJGKqDBuQmHQ8GvdtflpBSDPVcX2ztZF0mWYW0rLgpWVeVIanvecT8/jRx4Q== X-Received: by 2002:ac8:d03:: with SMTP id q3mr2896551qti.387.1545408212517; Fri, 21 Dec 2018 08:03:32 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id k22sm4472666qtm.73.2018.12.21.08.03.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:31 -0800 (PST) Date: Fri, 21 Dec 2018 08:02:53 -0800 Message-Id: <20181221160307.14819-1-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::833 Subject: [Qemu-devel] [PR RFC] RISC-V Changes for 3.2, Part 1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429: Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-19 15:31:02 +0000) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-3.2-part1 for you to fetch changes up to 7b91ae7d7944056c5e8045342e4039e978e43c82: MAINTAINERS: Mark RISC-V as Supported (2018-12-21 07:57:15 -0800) ---------------------------------------------------------------- RISC-V Changes for 3.2, Part 1 This pull request contains the first set of RISC-V patches I'd like to target for the 3.2 development cycle. It's really just a collection of bug fixes with one major new feature: PCIe can now be attached to RISC-V guests. This has passed my usual test of booting the latest Linux RC into a Fedora disk image on the virt machine. ---------------------------------------------------------------- Alistair Francis (4): hw/riscv/virt: Increase the number of interrupts hw/riscv/virt: Adjust memory layout spacing hw/riscv/virt: Connect the gpex PCIe riscv: Enable VGA and PCIE_VGA Anup Patel (3): sifive_u: Add clock DT node for GEM ethernet sifive_u: Set 'clock-frequency' DT property for SiFive UART target/riscv/pmp.c: Fix pmp_decode_napot() Mao Zhongyi (1): riscv/cpu: use device_class_set_parent_realize Michael Clark (4): RISC-V: Add hartid and \n to interrupt logging RISC-V: Fix CLINT timecmp low 32-bit writes RISC-V: Fix PLIC pending bitfield reads RISC-V: Enable second UART on sifive_e and sifive_u Nathaniel Graff (1): sifive_uart: Implement interrupt pending register Palmer Dabbelt (1): MAINTAINERS: Mark RISC-V as Supported MAINTAINERS | 2 +- default-configs/riscv32-softmmu.mak | 8 +- default-configs/riscv64-softmmu.mak | 8 +- hw/riscv/sifive_clint.c | 8 +- hw/riscv/sifive_e.c | 5 +- hw/riscv/sifive_plic.c | 2 +- hw/riscv/sifive_u.c | 25 +++++- hw/riscv/sifive_uart.c | 24 ++++-- hw/riscv/virt.c | 147 +++++++++++++++++++++++++++++++++--- include/hw/riscv/sifive_u.h | 3 +- include/hw/riscv/sifive_uart.h | 3 + include/hw/riscv/virt.h | 15 +++- target/riscv/cpu.c | 4 +- target/riscv/cpu_helper.c | 18 +++-- target/riscv/pmp.c | 2 +- 15 files changed, 231 insertions(+), 43 deletions(-) From patchwork Fri Dec 21 16:02:55 2018 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::834 Subject: [Qemu-devel] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Logan Gunthorpe Tested-by: Guenter Roeck Tested-by: Andrea Bolognani Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2b38f890702c..6b6fa39aaa38 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -47,14 +47,14 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } virt_memmap[] = { - [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0x11000 }, - [VIRT_TEST] = { 0x100000, 0x1000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, 0x4000000 }, - [VIRT_UART0] = { 0x10000000, 0x100 }, - [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, + [VIRT_DEBUG] = { 0x0, 0x100 }, + [VIRT_MROM] = { 0x1000, 0x11000 }, + [VIRT_TEST] = { 0x100000, 0x1000 }, + [VIRT_CLINT] = { 0x2000000, 0x10000 }, + [VIRT_PLIC] = { 0xc000000, 0x4000000 }, + [VIRT_UART0] = { 0x10000000, 0x100 }, + [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, + [VIRT_DRAM] = { 0x80000000, 0x0 }, }; static uint64_t load_kernel(const char *kernel_filename) From patchwork Fri Dec 21 16:02:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2182613B5 for ; Fri, 21 Dec 2018 16:08:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0E67326E54 for ; Fri, 21 Dec 2018 16:08:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 026A128479; Fri, 21 Dec 2018 16:08:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78DE826E54 for ; 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X-Received-From: 2607:f8b0:4864:20::843 Subject: [Qemu-devel] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Logan Gunthorpe , Palmer Dabbelt , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Alistair Francis Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis Signed-off-by: Logan Gunthorpe Reviewed-by: Logan Gunthorpe Tested-by: Guenter Roeck Tested-by: Andrea Bolognani Signed-off-by: Palmer Dabbelt --- default-configs/riscv32-softmmu.mak | 5 +- default-configs/riscv64-softmmu.mak | 5 +- hw/riscv/virt.c | 131 +++++++++++++++++++++++++++- include/hw/riscv/virt.h | 13 ++- 4 files changed, 150 insertions(+), 4 deletions(-) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 7937c69e2247..c5ea36cba597 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -1,7 +1,10 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 7937c69e2247..c5ea36cba597 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,7 +1,10 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6b6fa39aaa38..e7f0716fb667 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,6 +39,8 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" #include "elf.h" #include @@ -55,6 +57,9 @@ static const struct MemmapEntry { [VIRT_UART0] = { 0x10000000, 0x100 }, [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, [VIRT_DRAM] = { 0x80000000, 0x0 }, + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, + [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 }, + [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, }; static uint64_t load_kernel(const char *kernel_filename) @@ -98,6 +103,51 @@ static hwaddr load_initrd(const char *filename, uint64_t mem_size, return *start + size; } +static void create_pcie_irq_map(void *fdt, char *nodename, + uint32_t plic_phandle) +{ + int pin, dev; + uint32_t + full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; + uint32_t *irq_map = full_irq_map; + + /* This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { + int devfn = dev * 0x8; + + for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { + int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); + int i = 0; + + irq_map[i] = cpu_to_be32(devfn << 8); + + i += FDT_PCI_ADDR_CELLS; + irq_map[i] = cpu_to_be32(pin + 1); + + i += FDT_PCI_INT_CELLS; + irq_map[i++] = cpu_to_be32(plic_phandle); + + i += FDT_PLIC_ADDR_CELLS; + irq_map[i] = cpu_to_be32(irq_nr); + + irq_map += FDT_INT_MAP_WIDTH; + } + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", + full_irq_map, sizeof(full_irq_map)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { @@ -203,7 +253,10 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[VIRT_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", + FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", @@ -233,6 +286,33 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, g_free(nodename); } + nodename = g_strdup_printf("/soc/pci@%lx", + (long) memmap[VIRT_PCIE_ECAM].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", + FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", + FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "pci-host-ecam-generic"); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, + memmap[VIRT_PCIE_ECAM].base / + PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, + 0, memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, + 1, FDT_PCI_RANGE_MMIO, + 2, memmap[VIRT_PCIE_MMIO].base, + 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); + create_pcie_irq_map(fdt, nodename, plic_phandle); + g_free(nodename); + nodename = g_strdup_printf("/test@%lx", (long)memmap[VIRT_TEST].base); qemu_fdt_add_subnode(fdt, nodename); @@ -263,6 +343,47 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, return fdt; } + +static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, + hwaddr ecam_base, hwaddr ecam_size, + hwaddr mmio_base, hwaddr mmio_size, + hwaddr pio_base, + DeviceState *plic, bool link_up) +{ + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *mmio_reg; + qemu_irq irq; + int i; + + dev = qdev_create(NULL, TYPE_GPEX_HOST); + + qdev_init_nofail(dev); + + ecam_alias = g_new0(MemoryRegion, 1); + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, ecam_size); + memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); + + mmio_alias = g_new0(MemoryRegion, 1); + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); + } + + return dev; +} + static void riscv_virt_board_init(MachineState *machine) { const struct MemmapEntry *memmap = virt_memmap; @@ -385,6 +506,14 @@ static void riscv_virt_board_init(MachineState *machine) qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); } + gpex_pcie_init(system_memory, + memmap[VIRT_PCIE_ECAM].base, + memmap[VIRT_PCIE_ECAM].size, + memmap[VIRT_PCIE_MMIO].base, + memmap[VIRT_PCIE_MMIO].size, + memmap[VIRT_PCIE_PIO].base, + DEVICE(s->plic), true); + serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 2b2e6dd4ea6b..f12deaebd697 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -38,13 +38,17 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, - VIRT_DRAM + VIRT_DRAM, + VIRT_PCIE_MMIO, + VIRT_PCIE_PIO, + VIRT_PCIE_ECAM }; enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, + PCIE_IRQ = 0x20, /* 32 to 35 */ VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ }; @@ -62,6 +66,13 @@ enum { #define VIRT_PLIC_CONTEXT_BASE 0x200000 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_INT_CELLS 1 +#define FDT_PLIC_ADDR_CELLS 0 +#define FDT_PLIC_INT_CELLS 1 +#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ + FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) + #if defined(TARGET_RISCV32) #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 #elif defined(TARGET_RISCV64) From patchwork Fri Dec 21 16:02:57 2018 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::835 Subject: [Qemu-devel] [PULL 04/14] riscv: Enable VGA and PCIE_VGA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Alistair Francis Enable compile support for VGA devices. This allows the user to conenct a display by adding '-device bochs-display -display sdl' to their command line argument. Signed-off-by: Alistair Francis Reviewed-by: Logan Gunthorpe Tested-by: Andrea Bolognani Signed-off-by: Palmer Dabbelt --- default-configs/riscv32-softmmu.mak | 3 +++ default-configs/riscv64-softmmu.mak | 3 +++ 2 files changed, 6 insertions(+) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index c5ea36cba597..dbc93982848a 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -8,3 +8,6 @@ CONFIG_VIRTIO_MMIO=y CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index c5ea36cba597..dbc93982848a 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -8,3 +8,6 @@ CONFIG_VIRTIO_MMIO=y CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y From patchwork Fri Dec 21 16:02:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B53C714E2 for ; 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Fri, 21 Dec 2018 08:03:41 -0800 (PST) Date: Fri, 21 Dec 2018 08:02:58 -0800 Message-Id: <20181221160307.14819-6-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 Subject: [Qemu-devel] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , Alistair Francis , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Anup Patel The GEM ethernet on SiFive unleashed has fixed input clock of 125MHz as-per SiFive FU540 manual. This patch updates FDT generation for QEMU sifive_u machine to provide fixed-rate clock for GEM ethernet. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 18 +++++++++++++++++- include/hw/riscv/sifive_u.h | 3 ++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ef07df244241..5c41ee5017e4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -85,7 +85,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - uint32_t plic_phandle; + char ethclk_names[] = "pclk\0hclk\0tx_clk"; + uint32_t plic_phandle, ethclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -197,6 +198,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + nodename = g_strdup_printf("/soc/ethclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_GEM_CLOCK_FREQ); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3); + qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3); + ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); + g_free(nodename); + nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -208,6 +220,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + ethclk_phandle, ethclk_phandle, ethclk_phandle); + qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, + sizeof(ethclk_names)); qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); g_free(nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e8b4d9ffa3fb..be13cc1304cc 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -63,7 +63,8 @@ enum { }; enum { - SIFIVE_U_CLOCK_FREQ = 1000000000 + SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; #define SIFIVE_U_PLIC_HART_CONFIG "MS" From patchwork Fri Dec 21 16:02:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 60ED514DE for ; Fri, 21 Dec 2018 16:18:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F98A284E9 for ; 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Fri, 21 Dec 2018 08:03:43 -0800 (PST) Date: Fri, 21 Dec 2018 08:02:59 -0800 Message-Id: <20181221160307.14819-7-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::842 Subject: [Qemu-devel] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , Alistair Francis , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Anup Patel The 'clock-frequency' DT property is required by U-Boot to compute the divider value. This patch sets the 'clock-frequency' DT property of the SiFive UART device tree node (similar to virt machine). Signed-off-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5c41ee5017e4..849fa2e6311a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -241,6 +241,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); From patchwork Fri Dec 21 16:03:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9ED1513B5 for ; Fri, 21 Dec 2018 16:13:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D5C2284E4 for ; Fri, 21 Dec 2018 16:13:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8129C284ED; Fri, 21 Dec 2018 16:13:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0CF83284E4 for ; Fri, 21 Dec 2018 16:13:18 +0000 (UTC) Received: from localhost ([::1]:46467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNQL-00022e-5L for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Dec 2018 11:13:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNHN-0001dT-Fn for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gaNHM-0004D5-Gl for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:01 -0500 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]:33591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gaNHK-00047R-Go for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:03:58 -0500 Received: by mail-qk1-x72a.google.com with SMTP id o89so3363636qko.0 for ; Fri, 21 Dec 2018 08:03:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=6p7JyG3RH0lXqirJxx0bPeJBobxdYh1L5CqZ7x4vX6o=; b=i5VRlBJXxsxNZX8ofxaIH9l0PPfVsIyemjtcRHurEggdU1upO3T75vMEMMQaS3aq57 P+u/PEaBJu6uYxklxO7snsysI3RvHBNULRMHWp7sA/HwqIIaWcyRNFx0QuAf+ZjloY3r BHpyAuqFtYxu4dIDzK5wtBAAXDke+y1Dlz1YmsDDkoj3dg1iD45zCwWJRGBMV+NNkyiY nkBnk3twCBY7Qq37LjwOc9XW/JaLQP9ysY1C98FDIdSDWYUuWDjkiREv20vwgaqwDWdO m2u5hBuWUZbn8Ai9tpmEHYif87CoIZlJGOB2fpllx2Z1co4o4lab1TrE0Z/GWMOfE+ya 9Phg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=6p7JyG3RH0lXqirJxx0bPeJBobxdYh1L5CqZ7x4vX6o=; b=Q8EOiYaWMgJ5f+QweOwf8CVI81nSn/V14veewa9f7ctcn0b7TRt4M6/Qlh6R45xlTe g+Vft2JwTOpuHk3UpHIe41By4tA1MiYBD/dB3Abps0xYuGdv8pupu+VdCKrvzwhU/krb okkVAx1I4+Br7X2AhSrqw51oZ0r6LUC6LxdXbLjpZu1ZnFEXW3oL5l+GNMm8X9tPRB/e dAqF5tMF/pfC7wbQcUqEr/JPDfI/bp1XUU58P+Mn+hTL1L49nXBBswcC//no7SsbakOs iLK9PspJgcgiu58KBMD8kO4H7VbMQY6cS/8giDrx135w9sTjLBh/m99pX31MtyTYlmJk R5Ow== X-Gm-Message-State: AJcUukcibYi7Vm42WLLUh8+tkKsZ1r0TxMTIc2lt7StKPIxsMt2pBX50 16F4qWPpoeJpL0b7nVd+ikjBgNkzRbo= X-Google-Smtp-Source: ALg8bN5E6/wcHqKSJTWLLgX85358q0sOVtwP/4yG41Zp/vwnghwX/2+D4xGm2LFBUtO55W8yA4UtOg== X-Received: by 2002:a37:96c2:: with SMTP id y185mr2692248qkd.239.1545408225952; Fri, 21 Dec 2018 08:03:45 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id n3sm6635062qtc.81.2018.12.21.08.03.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:45 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:00 -0800 Message-Id: <20181221160307.14819-8-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::72a Subject: [Qemu-devel] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark Add carriage return that was erroneously removed when converting to qemu_log. Change hard coded core number to the actual hartid. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 86f9f4730c88..0234c2d52886 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -445,11 +445,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (RISCV_DEBUG_INTERRUPT) { int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK; if (cs->exception_index & RISCV_EXCP_INT_FLAG) { - qemu_log_mask(LOG_TRACE, "core 0: trap %s, epc 0x" TARGET_FMT_lx, - riscv_intr_names[log_cause], env->pc); + qemu_log_mask(LOG_TRACE, "core " + TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n", + env->mhartid, riscv_intr_names[log_cause], env->pc); } else { - qemu_log_mask(LOG_TRACE, "core 0: intr %s, epc 0x" TARGET_FMT_lx, - riscv_excp_names[log_cause], env->pc); + qemu_log_mask(LOG_TRACE, "core " + TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n", + env->mhartid, riscv_excp_names[log_cause], env->pc); } } @@ -511,8 +513,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (hasbadaddr) { if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld - ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" + TARGET_FMT_lx "\n", env->mhartid, env->badaddr); } env->sbadaddr = env->badaddr; } else { @@ -536,8 +538,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (hasbadaddr) { if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld - ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" + TARGET_FMT_lx "\n", env->mhartid, env->badaddr); } env->mbadaddr = env->badaddr; } else { From patchwork Fri Dec 21 16:03:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0325F13B5 for ; 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Fri, 21 Dec 2018 08:03:46 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:01 -0800 Message-Id: <20181221160307.14819-9-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::741 Subject: [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark A missing shift made updates to the low order bits of timecmp erroneously copy the old low order bits into the high order bits of the 64-bit timecmp register. Add the missing shift and rename timecmp local variables to timecmp_hi and timecmp_lo. This bug didn't show up as the low order bits are usually written first followed by the high order bits meaning the high order bits contained an invalid value between the timecmp_lo and timecmp_hi update. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Co-Authored-by: Johannes Haring Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 0d2fd52487e6..d4c159e93736 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -146,15 +146,15 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { /* timecmp_lo */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_hi = env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); return; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_lo = env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)addr); } From patchwork Fri Dec 21 16:03:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E207913B5 for ; Fri, 21 Dec 2018 16:10:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFC2D28479 for ; Fri, 21 Dec 2018 16:10:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C249C2849D; Fri, 21 Dec 2018 16:10:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4700828479 for ; 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Fri, 21 Dec 2018 08:03:49 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id h35sm6519532qth.59.2018.12.21.08.03.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:48 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:02 -0800 Message-Id: <20181221160307.14819-10-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 Subject: [Qemu-devel] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark The address calculation for the pending bitfield had a copy paste bug. This bug went unnoticed because the Linux PLIC driver does not read the pending bitfield, rather it reads pending interrupt numbers from the claim register and writes acknowledgements back to the claim register. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Reported-by: Vincent Siles Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_plic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 9cf9a1f98644..d12ec3fc9a54 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -214,7 +214,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { - uint32_t word = (addr - plic->priority_base) >> 2; + uint32_t word = (addr - plic->pending_base) >> 2; if (RISCV_DEBUG_PLIC) { qemu_log("plic: read pending: word=%d value=%d\n", word, plic->pending[word]); From patchwork Fri Dec 21 16:03:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740673 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF70714DE for ; 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Fri, 21 Dec 2018 08:03:50 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:03 -0800 Message-Id: <20181221160307.14819-11-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::82e Subject: [Qemu-devel] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark Previously the second UARTs on the sifive_e and sifive_u machines where disabled due to check-qtest-riscv32 and check-qtest-riscv64 failures. Recent changes in the QEMU core serial code have resolved these failures so the second UARTs can be instantiated. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e.c | 5 ++--- hw/riscv/sifive_u.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index cb513cc3bb50..5d9d65ff29ab 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -192,9 +192,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); - /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_E_UART1_IRQ)); */ + sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 849fa2e6311a..3bd3b67507f8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -368,9 +368,8 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_PLIC].size); sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); - /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_U_UART1_IRQ)); */ + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); From patchwork Fri Dec 21 16:03:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740679 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB40D14DE for ; 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Fri, 21 Dec 2018 08:03:52 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:04 -0800 Message-Id: <20181221160307.14819-12-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::834 Subject: [Qemu-devel] [PULL 11/14] sifive_uart: Implement interrupt pending register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nathaniel Graff , Palmer Dabbelt , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Nathaniel Graff The watermark bits are set in the interrupt pending register according to the configuration of txcnt and rxcnt in the txctrl and rxctrl registers. Since the UART TX does not implement a FIFO, the txwm bit is set as long as the TX watermark level is greater than zero. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_uart.c | 24 +++++++++++++++++++----- include/hw/riscv/sifive_uart.h | 3 +++ 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index b0c3798cf274..456a3d3697c2 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -28,12 +28,26 @@ * Not yet implemented: * * Transmit FIFO using "qemu/fifo8.h" - * SIFIVE_UART_IE_TXWM interrupts - * SIFIVE_UART_IE_RXWM interrupts must honor fifo watermark - * Rx FIFO watermark interrupt trigger threshold - * Tx FIFO watermark interrupt trigger threshold. */ +/* Returns the state of the IP (interrupt pending) register */ +static uint64_t uart_ip(SiFiveUARTState *s) +{ + uint64_t ret = 0; + + uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); + uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); + + if (txcnt != 0) { + ret |= SIFIVE_UART_IP_TXWM; + } + if (s->rx_fifo_len > rxcnt) { + ret |= SIFIVE_UART_IP_RXWM; + } + + return ret; +} + static void update_irq(SiFiveUARTState *s) { int cond = 0; @@ -69,7 +83,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: - return s->rx_fifo_len ? SIFIVE_UART_IP_RXWM : 0; + return uart_ip(s); case SIFIVE_UART_TXCTRL: return s->txctrl; case SIFIVE_UART_RXCTRL: diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h index 504f18a60f1b..c8dc1c57fd0b 100644 --- a/include/hw/riscv/sifive_uart.h +++ b/include/hw/riscv/sifive_uart.h @@ -43,6 +43,9 @@ enum { SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ }; +#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) +#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) + #define TYPE_SIFIVE_UART "riscv.sifive.uart" #define SIFIVE_UART(obj) \ From patchwork Fri Dec 21 16:03:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96C8314DE for ; Fri, 21 Dec 2018 16:08:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87206284B9 for ; Fri, 21 Dec 2018 16:08:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B96E284D4; Fri, 21 Dec 2018 16:08:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 73300284B9 for ; Fri, 21 Dec 2018 16:08:01 +0000 (UTC) Received: from localhost ([::1]:46417 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNLE-0003su-Lj for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Dec 2018 11:08:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNHO-0001fY-Vq for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gaNHO-0004Fc-2B for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:02 -0500 Received: from mail-qt1-x841.google.com ([2607:f8b0:4864:20::841]:44348) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gaNHN-0004BA-LV for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:01 -0500 Received: by mail-qt1-x841.google.com with SMTP id n32so6162105qte.11 for ; Fri, 21 Dec 2018 08:03:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=pGdFvWxsyK+082c4RANqehx4XfGix5v1XjwMetfsyZg=; b=BFLxT6q9KDFCMRBUTi6o8oPwvKDwh+WJDvy1PvXZOXrgmkn4lqivhU6vuZOuHVPFrb LmHjWBJSBPmDmwU6FC9tAcwzXxstYH2KT0tGfIuYNQfJmp2A4sdgr9TRVGrY/z9pM1AN YnnLeXxJjo7XlIyHOrEwgUvt37uDJ5YDJIm9jF1UN80vE5SWHW/0BZH0EMVxHPbrcDEk TUvEzQrdhDl1NoXj+uhIUvvcAXQ7INx/WtKXFxlO0tuGs4o4EgYrXYa5QwOqCmzMOGum +0Hb0a7njE3gwdhAcFFjlS92xTuNkrYaRHfYXecTWK4vkoaZXAzRrZA40er5tRxGJVan dcoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=pGdFvWxsyK+082c4RANqehx4XfGix5v1XjwMetfsyZg=; b=tkROPMT8E94V9AGfiOTHLOQjFxsgoOZvtMhveFtbH5vo3Emr6Asi8UW0J0GAiJfT/k NhH9QnUmLerIVIW3Gk6VSRRXvRFn4oMEKbYcjMeJ+wXqDuBtNPXGDGexxmhZ5HdwoCOU EkGrOnPDRymLiL0xUIEoBboRnRRZP7O0i0q5NrQ31tvs4Cijis4tQOPHONqqfs5x1KPE eECieA9fkuGXdBJ41duXfmJMgOCynvUj4OTx5+L/6johXXTQu9XG4Aob4Y5GLlCLUPfn KPXxzyOl1VYDFFIlOuBhMO1O/USpcCw+UZOq/P92VMQQbqhF6+GYXS/J4Wg2Sd+RTmxI tS9g== X-Gm-Message-State: AJcUukcmVBEfRT1fNKqSH3jJV3ThFwmtfI4D8+HhRHcV7W2HDiL/rTpb gkmFqNY8GxzYShwDqM08LAuRspiU5ME= X-Google-Smtp-Source: ALg8bN7HDkHstcrzBb2D1EL2iZd9wYwALtAwVk5F7dj5Zd+ikIVsdvekOmaJkaezjpTpGeLN2J6RwA== X-Received: by 2002:a0c:b093:: with SMTP id o19mr2997013qvc.49.1545408234814; Fri, 21 Dec 2018 08:03:54 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id 24sm6307676qkx.77.2018.12.21.08.03.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:54 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:05 -0800 Message-Id: <20181221160307.14819-13-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 Subject: [Qemu-devel] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , Alistair Francis , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Anup Patel Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 03abd8fe5eb7..15a5366616bd 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -138,7 +138,7 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) return; } else { target_ulong t1 = ctz64(~a); - target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; + target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2; target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; *sa = base; *ea = base + range; From patchwork Fri Dec 21 16:03:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 15A3014DE for ; Fri, 21 Dec 2018 16:10:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0526D284A5 for ; Fri, 21 Dec 2018 16:10:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED4B1284B9; Fri, 21 Dec 2018 16:10:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A5277284A5 for ; Fri, 21 Dec 2018 16:10:46 +0000 (UTC) Received: from localhost ([::1]:46451 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNNt-0008AY-K5 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Dec 2018 11:10:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNHQ-0001h9-3X for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gaNHN-0004F6-N2 for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:03 -0500 Received: from mail-qk1-x732.google.com ([2607:f8b0:4864:20::732]:46705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gaNHN-0004Bp-DL for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:01 -0500 Received: by mail-qk1-x732.google.com with SMTP id q1so3331102qkf.13 for ; Fri, 21 Dec 2018 08:03:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=tnbr8NQlLnEwyDk6jq23yeNCNXL8rh7xi2hs6eUQisk=; b=mFl6Z5azvogZ9jJPXFPruvbA9SbiO4GkQV8grB0yT4t5k4U9y/JlSch+ceztPgE1Yx +ETdBUbuEIMdWib2/w/0/KDdgSOnfrDhDeCb3AUpv0Z846Z/EKJES2Gzh1nHYYaU9DEZ Y6ZNeOodMjNsNbpGzkkmMcIimGH+SBwZF9lskKOU/eMx5J6vhsfLbwqg7MIRGeiSa15C QkoQRMfOLlHW5Zrw0gf+X7jkB94ppsat4AeYINa7yFBy8yM0bIJ6HKpABA3qT6YQbEcG MCKse4gChsaH0RnoPPFWMoW2xCEWqulmaJrWTonxQh94o76TR+hb+zQpQrsHLrGgU3/I hqjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=tnbr8NQlLnEwyDk6jq23yeNCNXL8rh7xi2hs6eUQisk=; b=IX9QO4CyZxX7n09LdV0c4AmhgKlEoMD4TufQfCoNizX16eYrC2gvF/BroA19zX+o2r mA4kb+6tZIjbdnV+fd2SAHAXdFiGV9YJ5K8pWYqt60R/Rv05d6Nr2PRJIEGEzV0UaVf9 +FSIwbBCNswpKsaKWKIuFvEVzKZXIDAOIWH5vAAgVfImspXG9GMY/hMVtqmXADuOuP6M 0XWdbk9L4chXRhDxrDOKBSgpDfTeNtZ0OQFmorZaf625ZTbz+/xKEJDTAObmJS5RKEYz cLrvqSGtGVuR4c/MwYBcyS8IUb+nV5kFt3cN5onLl+dWIKY7Xo1EBY86eK0qd/so+Jqp +9LA== X-Gm-Message-State: AJcUukdrGzZQgwyf1J3JQyVaUQp1eazXjdoXnxZeRTZSIiNS0LLkZHP+ kEyUSZ9uhipE3wX6gEWLciDAUPC0rug= X-Google-Smtp-Source: ALg8bN7KRmM2VX/iRzWCAqmI5J62TMLWFDcOwY2wu4BZEr/5qRmoInpDlcG78FcsvQuzzfYGJrScuQ== X-Received: by 2002:a37:ba06:: with SMTP id k6mr2860378qkf.115.1545408236411; Fri, 21 Dec 2018 08:03:56 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id a68sm6069751qkj.63.2018.12.21.08.03.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:55 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:06 -0800 Message-Id: <20181221160307.14819-14-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::732 Subject: [Qemu-devel] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-devel@nongnu.org, Mao Zhongyi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Mao Zhongyi Signed-off-by: Mao Zhongyi Reviewed-by: Bastian Koppelmann Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a025a0a3baac..5e8a2cb2ba61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -330,8 +330,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); - mcc->parent_realize = dc->realize; - dc->realize = riscv_cpu_realize; + device_class_set_parent_realize(dc, riscv_cpu_realize, + &mcc->parent_realize); mcc->parent_reset = cc->reset; cc->reset = riscv_cpu_reset; From patchwork Fri Dec 21 16:03:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A21BC13B5 for ; Fri, 21 Dec 2018 16:08:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 919B127C2D for ; Fri, 21 Dec 2018 16:08:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 855C52849D; Fri, 21 Dec 2018 16:08:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0328A27C2D for ; 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X-Received-From: 2607:f8b0:4864:20::831 Subject: [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP There's at least two of us that are paid to work on this. Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index d676c73f8840..317eff6cec4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -262,7 +262,7 @@ M: Alistair Francis M: Sagar Karandikar M: Bastian Koppelmann L: qemu-riscv@nongnu.org -S: Maintained +S: Supported F: target/riscv/ F: hw/riscv/ F: include/hw/riscv/