From patchwork Mon Dec 20 21:15:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E5FBC43219 for ; Mon, 20 Dec 2021 21:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.249993.430485 (Exim 4.92) (envelope-from ) id 1mzQ15-0005LD-Bx; Mon, 20 Dec 2021 21:16:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 249993.430485; Mon, 20 Dec 2021 21:16:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mzQ15-0005Kp-59; Mon, 20 Dec 2021 21:16:19 +0000 Received: by outflank-mailman (input) for mailman id 249993; Mon, 20 Dec 2021 21:16:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mzQ13-0005IG-AV for xen-devel@lists.xenproject.org; Mon, 20 Dec 2021 21:16:17 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1119e5da-61da-11ec-9e60-abaf8a552007; Mon, 20 Dec 2021 22:16:16 +0100 (CET) Received: by mail-lf1-x134.google.com with SMTP id x21so16375186lfa.5 for ; Mon, 20 Dec 2021 13:16:15 -0800 (PST) Received: from otyshchenko.router ([212.22.223.21]) by smtp.gmail.com with ESMTPSA id b35sm635132lfv.209.2021.12.20.13.16.14 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Dec 2021 13:16:15 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1119e5da-61da-11ec-9e60-abaf8a552007 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5gytA2pLllrFj6CH99Xdk/Opt3jWfGlT8ShBqhaNetg=; b=Cdq4GjJ/2iK2iIIDzgHUFWhpcJBt2NTM2SeUjG+PuWAccmKfbquvFCKrO8Ez+FFwHY j111WBq0jRNFONhvtOulyEGsd1uE8GrmfipXT25rC/jzrCa/2mWJxkbPiNiNFvtwYjts GGa0E43hrhogNSeQPjJhaorFWWucTU2cQtt1RbtbkyzjF9wjvM0c5XxbMs8TJxBxcIK9 UuGDvoU+OfsP7bPu8VX5JmKNzsOxXb+US2eNpRCaEtd/6WHXFfa2XK7GToLiBlQGvOX8 JHwdxdmuFUmDT5SQm/OzzoKiDS8kJVoCL7P9GjMK2l4CrMaEb9O9qu2+EE7ZVSa1AmYD Q1dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5gytA2pLllrFj6CH99Xdk/Opt3jWfGlT8ShBqhaNetg=; b=KNQUR3+RpFwnnt8fZ/R+g94yd7NWIM+7jeWnVkgMiVVcPR/YoLdjwdANn+cZiCjA73 PyAk6iobzS2ITOFvmUPV9NwRasuUfClNtQUPoTJS9cH4g/th8kNOTJS+3+UcbQhoTEnC NnFacY9BzGeOSW4l5yPlR+yxZ9qqz2VNvMkYUtp6xal7ITPfYYt3/eSj5BHOiimn2M/D DGcoeB1Ww+WY+MLQkaTyyfs12ZsLY72+U1Uc5TkrvM8lS0mYGFTT3azhHdLTVUOAgJez /ux2Nr+cts4jPM6tc7X6JbaxNhrCs/3FItaSVLdYqgor7XF/LOEoP2FzsOS7zayWOTPd 8mGw== X-Gm-Message-State: AOAM531ZW/1jAxzCTefvA8eYem2CtNUh+zU28J+ro/ptbKZ5Pu55iRkn as1eTakfBbL10jhYapxquavUcqonBoE= X-Google-Smtp-Source: ABdhPJxaDOs+TBKah+ukRAfspi33bXHs6F6TXrKYX+7z3geOaurnZi1gkTrB2n7oqg3+F9pCzFg0Wg== X-Received: by 2002:a05:6512:3054:: with SMTP id b20mr2857265lfb.359.1640034975570; Mon, 20 Dec 2021 13:16:15 -0800 (PST) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Yoshihiro Shimoda , Oleksandr Andrushchenko Subject: [PATCH V2 01/10] iommu/ipmmu-vmsa: Remove all unused register definitions Date: Mon, 20 Dec 2021 23:15:48 +0200 Message-Id: <1640034957-19764-2-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> References: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> MIME-Version: 1.0 From: Oleksandr Tyshchenko This is a non-verbatim port of corresponding Linux upsteam commit: 77cf983892b2e0d40dc256b784930a9ffaad4fc8 Original commit message: commit 77cf983892b2e0d40dc256b784930a9ffaad4fc8 Author: Yoshihiro Shimoda Date: Wed Nov 6 11:35:45 2019 +0900 iommu/ipmmu-vmsa: Remove all unused register definitions To support different registers memory mapping hardware easily in the future, this patch removes all unused register definitions. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Niklas Söderlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Although Linux and Xen drivers have a lot in common, the main differences are in translation stages (table formats), VMSAv8 modes, supported SoC generations, etc, therefore that's why there is a slight difference in registers/bits each driver considers unused. No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 59 ++------------------------------ 1 file changed, 2 insertions(+), 57 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 1255b0d..4a8a974 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -166,15 +166,11 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMCTR 0x0000 /* - * These fields are implemented in IPMMU-MM only. So, can be set for + * This field is implemented in IPMMU-MM only. So, can be set for * Root IPMMU only. */ #define IMCTR_VA64 (1 << 29) -#define IMCTR_TRE (1 << 17) -#define IMCTR_AFE (1 << 16) -#define IMCTR_RTSEL_MASK (3 << 4) -#define IMCTR_RTSEL_SHIFT 4 -#define IMCTR_TREN (1 << 3) + /* * These fields are common for all IPMMU devices. So, can be set for * Cache IPMMUs as well. @@ -184,42 +180,9 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMCTR_MMUEN (1 << 0) #define IMCTR_COMMON_MASK (7 << 0) -#define IMCAAR 0x0004 - #define IMTTBCR 0x0008 #define IMTTBCR_EAE (1U << 31) #define IMTTBCR_PMB (1 << 30) -#define IMTTBCR_SH1_NON_SHAREABLE (0 << 28) -#define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28) -#define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28) -#define IMTTBCR_SH1_MASK (3 << 28) -#define IMTTBCR_ORGN1_NC (0 << 26) -#define IMTTBCR_ORGN1_WB_WA (1 << 26) -#define IMTTBCR_ORGN1_WT (2 << 26) -#define IMTTBCR_ORGN1_WB (3 << 26) -#define IMTTBCR_ORGN1_MASK (3 << 26) -#define IMTTBCR_IRGN1_NC (0 << 24) -#define IMTTBCR_IRGN1_WB_WA (1 << 24) -#define IMTTBCR_IRGN1_WT (2 << 24) -#define IMTTBCR_IRGN1_WB (3 << 24) -#define IMTTBCR_IRGN1_MASK (3 << 24) -#define IMTTBCR_TSZ1_MASK (0x1f << 16) -#define IMTTBCR_TSZ1_SHIFT 16 -#define IMTTBCR_SH0_NON_SHAREABLE (0 << 12) -#define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12) -#define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) -#define IMTTBCR_SH0_MASK (3 << 12) -#define IMTTBCR_ORGN0_NC (0 << 10) -#define IMTTBCR_ORGN0_WB_WA (1 << 10) -#define IMTTBCR_ORGN0_WT (2 << 10) -#define IMTTBCR_ORGN0_WB (3 << 10) -#define IMTTBCR_ORGN0_MASK (3 << 10) -#define IMTTBCR_IRGN0_NC (0 << 8) -#define IMTTBCR_IRGN0_WB_WA (1 << 8) -#define IMTTBCR_IRGN0_WT (2 << 8) -#define IMTTBCR_IRGN0_WB (3 << 8) -#define IMTTBCR_IRGN0_MASK (3 << 8) -#define IMTTBCR_SL0_LVL_2 (0 << 6) #define IMTTBCR_SL0_LVL_1 (1 << 6) #define IMTTBCR_TSZ0_MASK (0x1f << 0) #define IMTTBCR_TSZ0_SHIFT 0 @@ -228,18 +191,8 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMTTLBR0_TTBR_MASK (0xfffff << 12) #define IMTTUBR0 0x0014 #define IMTTUBR0_TTBR_MASK (0xff << 0) -#define IMTTLBR1 0x0018 -#define IMTTLBR1_TTBR_MASK (0xfffff << 12) -#define IMTTUBR1 0x001c -#define IMTTUBR1_TTBR_MASK (0xff << 0) #define IMSTR 0x0020 -#define IMSTR_ERRLVL_MASK (3 << 12) -#define IMSTR_ERRLVL_SHIFT 12 -#define IMSTR_ERRCODE_TLB_FORMAT (1 << 8) -#define IMSTR_ERRCODE_ACCESS_PERM (4 << 8) -#define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8) -#define IMSTR_ERRCODE_MASK (7 << 8) #define IMSTR_MHIT (1 << 4) #define IMSTR_ABORT (1 << 2) #define IMSTR_PF (1 << 1) @@ -251,11 +204,7 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) #define IMUCTR0(n) (0x0300 + ((n) * 16)) #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) -#define IMUCTR_FIXADDEN (1U << 31) -#define IMUCTR_FIXADD_MASK (0xff << 16) -#define IMUCTR_FIXADD_SHIFT 16 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) -#define IMUCTR_TTSEL_PMB (8 << 4) #define IMUCTR_TTSEL_MASK (15 << 4) #define IMUCTR_TTSEL_SHIFT 4 #define IMUCTR_FLUSH (1 << 1) @@ -264,10 +213,6 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) #define IMUASID0(n) (0x0308 + ((n) * 16)) #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) -#define IMUASID_ASID8_MASK (0xff << 8) -#define IMUASID_ASID8_SHIFT 8 -#define IMUASID_ASID0_MASK (0xff << 0) -#define IMUASID_ASID0_SHIFT 0 #define IMSAUXCTLR 0x0504 #define IMSAUXCTLR_S2PTE (1 << 3) From patchwork Mon Dec 20 21:15:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63FACC43217 for ; Mon, 20 Dec 2021 21:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.249994.430493 (Exim 4.92) (envelope-from ) id 1mzQ15-0005Qi-Lo; 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No behavior change. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Besides changes done in the original commit, we also need to update an extra call sites which Linux driver doesn't have, but Xen driver has such as ipmmu_ctx_write_cache(), etc. No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 4a8a974..ce5c3bc 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -307,18 +307,35 @@ static void ipmmu_write(struct ipmmu_vmsa_device *mmu, uint32_t offset, writel(data, mmu->base + offset); } +static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, + unsigned int context_id, uint32_t reg) +{ + return context_id * IM_CTX_SIZE + reg; +} + +static uint32_t ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, + unsigned int context_id, uint32_t reg) +{ + return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg)); +} + +static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu, + unsigned int context_id, uint32_t reg, + uint32_t data) +{ + ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data); +} + static uint32_t ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, uint32_t reg) { - return ipmmu_read(domain->mmu->root, - domain->context_id * IM_CTX_SIZE + reg); + return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); } static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, uint32_t reg, uint32_t data) { - ipmmu_write(domain->mmu->root, - domain->context_id * IM_CTX_SIZE + reg, data); + ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); } static void ipmmu_ctx_write_cache(struct ipmmu_vmsa_domain *domain, @@ -329,8 +346,8 @@ static void ipmmu_ctx_write_cache(struct ipmmu_vmsa_domain *domain, /* Mask fields which are implemented in IPMMU-MM only. */ if ( !ipmmu_is_root(domain->mmu) ) - ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, - data & IMCTR_COMMON_MASK); + ipmmu_ctx_write(domain->mmu, domain->context_id, reg, + data & IMCTR_COMMON_MASK); } /* @@ -693,7 +710,7 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) /* Disable all contexts. */ for ( i = 0; i < mmu->num_ctx; ++i ) - ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0); + ipmmu_ctx_write(mmu, i, IMCTR, 0); } /* R-Car Gen3 SoCs product and cut information. */ From patchwork Mon Dec 20 21:15:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51088C4332F for ; Mon, 20 Dec 2021 21:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.249995.430502 (Exim 4.92) (envelope-from ) id 1mzQ16-0005gn-7I; Mon, 20 Dec 2021 21:16:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 249995.430502; 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Mon, 20 Dec 2021 13:16:16 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 11ee8156-61da-11ec-85d3-df6b77346a89 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hajm4OA2mR1rqKBWo1oPRyQ75UieT0Vx1ZnO7YitzIM=; b=qIXmN3ldE/ZN74+4YThza4AYid4jpygjX+xdmfkD6EAA5y37CvzdUbPtTSqP+1hezy FbateqQKdPFMOjjVuW3VU6Std4HufcBhyTDj+OTVAdRyBwkZNr0k/MHwOk9aYF+ijU1z 50fNGe+Ij8QFC6URM0g//2mLElYzbjnUFC4cs4myBgUpaHWUG9fB3EfSmWFmWIlCqG/R e4uCVxbL6WrKLuyi/hgXa5dpUx1cVncs8xDJoil1jpJPbOdHZiQEuTIpBnDUonl6P6kI Pweo79tXZ5V1g8p0e8nexsWb8XlHgeuno1/k/jxl3Sp9RBn9Su9HDg01r8kaK3EVMhWF v9FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hajm4OA2mR1rqKBWo1oPRyQ75UieT0Vx1ZnO7YitzIM=; b=z70XkiH2NGmtAtHattaH6UB4GV+988PBJwoQYJkJ/iftam1D068s1rOKIH2QzwNclj f2aFUt11kE1nijbcMIwGi3Nq7FHIfHkTY8VmHbYtMaxV+jjhsQ0snJjQudsvwsCosidR BVoC7jzgkBS1YXBugV3SSBKKveizofBmaa3fvTYICxLbXnVfWWkeedP6dVdoITEyHo+L 00fg8A2H+jSqIq0cHjf1tR7lf6hUFWwW1otP+WaD6d1Zz3CYvqtERFmcJJikhBULr13f aylHy1la0tACvfplAoDUeIGZMs7mDNQfh88GzO6UpamNjEptV6Z5X5ob/eWWEmFQ5qcv tpSQ== X-Gm-Message-State: AOAM531Lbzhh+U4WQqfkTdGpUmznGyNfrAK73Ufvjd1m2gzZrjoNzB9h A9sBooliReySq1WWltcpt5+QucRfkOY= X-Google-Smtp-Source: ABdhPJxzTfRun3YkUwibQaiDMstuUa+taVcJp9VRWabBxAHUy/4zPZawhc2OjDWcR5BYP0Abgva61g== X-Received: by 2002:a05:6512:3054:: with SMTP id b20mr2857353lfb.359.1640034976971; Mon, 20 Dec 2021 13:16:16 -0800 (PST) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Yoshihiro Shimoda , Oleksandr Andrushchenko Subject: [PATCH V2 03/10] iommu/ipmmu-vmsa: Add helper functions for "uTLB" registers Date: Mon, 20 Dec 2021 23:15:50 +0200 Message-Id: <1640034957-19764-4-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> References: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> MIME-Version: 1.0 From: Oleksandr Tyshchenko This is a non-verbatim port of corresponding Linux upsteam commit: 3667c9978b2911dc1ded77f5971df477885409c4 Original commit message: commit 3667c9978b2911dc1ded77f5971df477885409c4 Author: Yoshihiro Shimoda Date: Wed Nov 6 11:35:49 2019 +0900 iommu/ipmmu-vmsa: Add helper functions for "uTLB" registers Since we will have changed memory mapping of the IPMMU in the future, This patch adds helper functions ipmmu_utlb_reg() and ipmmu_imu{asid,ctr}_write() for "uTLB" registers. No behavior change. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Besides changes done in the original commit, we also need to introduce ipmmu_imuctr_read() since Xen driver contains an additional logic in ipmmu_utlb_enable() to prevent the use cases where devices which use the same micro-TLB are assigned to different Xen domains. No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 33 +++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index ce5c3bc..1b94af2 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -366,6 +366,29 @@ static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, ipmmu_ctx_write_root(domain, reg, data); } +static uint32_t ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, uint32_t reg) +{ + return reg; +} + +static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu, + unsigned int utlb, uint32_t data) +{ + ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data); +} + +static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu, + unsigned int utlb, uint32_t data) +{ + ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data); +} + +static uint32_t ipmmu_imuctr_read(struct ipmmu_vmsa_device *mmu, + unsigned int utlb) +{ + return ipmmu_read(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb))); +} + /* TLB and micro-TLB Management */ /* Wait for any pending TLB invalidations to complete. */ @@ -413,7 +436,7 @@ static int ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, * context_id for already enabled micro-TLB and prevent different context * bank from being set. */ - imuctr = ipmmu_read(mmu, IMUCTR(utlb)); + imuctr = ipmmu_imuctr_read(mmu, utlb); if ( imuctr & IMUCTR_MMUEN ) { unsigned int context_id; @@ -431,9 +454,9 @@ static int ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, * TODO: Reference-count the micro-TLB as several bus masters can be * connected to the same micro-TLB. */ - ipmmu_write(mmu, IMUASID(utlb), 0); - ipmmu_write(mmu, IMUCTR(utlb), imuctr | - IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_MMUEN); + ipmmu_imuasid_write(mmu, utlb, 0); + ipmmu_imuctr_write(mmu, utlb, imuctr | + IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_MMUEN); return 0; } @@ -444,7 +467,7 @@ static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, { struct ipmmu_vmsa_device *mmu = domain->mmu; - ipmmu_write(mmu, IMUCTR(utlb), 0); + ipmmu_imuctr_write(mmu, utlb, 0); } /* Domain/Context Management */ From patchwork Mon Dec 20 21:15:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4AF7C433EF for ; Mon, 20 Dec 2021 21:16:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.249996.430507 (Exim 4.92) (envelope-from ) id 1mzQ16-0005p6-Iz; Mon, 20 Dec 2021 21:16:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 249996.430507; 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Mon, 20 Dec 2021 13:16:17 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 125b3604-61da-11ec-9e60-abaf8a552007 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KJJAXoBnqeeexsUsPrxE65JqoMaWk11lTyVByXKTYSU=; b=gOLATyKm4zSuOWV9E6Se+183dJv3dZ4/1hi1dCnT5d0xz/p49ipsWk4V+62Um9IuBV rXA6KY/y9/6AbhC7qupKNiWW2cVU68mDGL7tetdBNNv1EtYpiFMhUVL2ihZ7sGQxh3M9 cVb7anEJhQ2h3n6Z2f32MmLl6TWR+uugTRwLnidi1KpP4CFIO0Dn9ztq49JAzMtWx/nZ OI/iBvIwdtbUhiX81WTHj1fvg+TJi10f6qqRdn0KEmkhI9SHbfRvkevt71a8XedKaQkc IV1Kjwr0YxIQZvKezY9U/6U5tg4DhurweX+Yna+L9OBmffGONeFCvmXZoW6Ktzu8f5UH phqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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We don't need to pull the whole struct and all instances as Xen driver doesn't support old Arm32 based Gen2 SoCs, so there is no point in keeping all differences between Gen2 and Gen3 here. All what we need is a minimal support to be able to operate with Gen3 and new S4. Add Gen3 specific info with only two fields (number_of_contexts and num_utlbs) for now, the subsequent patches will add remaining bits. No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 54 +++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 14 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 1b94af2..369be4c 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -71,9 +71,9 @@ * R-Car Gen3 SoCs make use of up to 8 IPMMU contexts (sets of page table) and * these can be managed independently. Each context is mapped to one Xen domain. */ -#define IPMMU_CTX_MAX 8 +#define IPMMU_CTX_MAX 8U /* R-Car Gen3 SoCs make use of up to 48 micro-TLBs per IPMMU device. */ -#define IPMMU_UTLB_MAX 48 +#define IPMMU_UTLB_MAX 48U /* IPMMU context supports IPA size up to 40 bit. */ #define IPMMU_MAX_P2M_IPA_BITS 40 @@ -106,17 +106,22 @@ struct ipmmu_vmsa_xen_device { struct ipmmu_vmsa_device *mmu; }; +struct ipmmu_features { + unsigned int number_of_contexts; + unsigned int num_utlbs; +}; + /* Root/Cache IPMMU device's information */ struct ipmmu_vmsa_device { struct device *dev; void __iomem *base; struct ipmmu_vmsa_device *root; struct list_head list; - unsigned int num_utlbs; unsigned int num_ctx; spinlock_t lock; /* Protects ctx and domains[] */ DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; + const struct ipmmu_features *features; }; /* @@ -727,6 +732,11 @@ static int ipmmu_init_platform_device(struct device *dev, return 0; } +static const struct ipmmu_features ipmmu_features_rcar_gen3 = { + .number_of_contexts = 8, + .num_utlbs = 48, +}; + static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) { unsigned int i; @@ -798,6 +808,27 @@ static __init bool ipmmu_stage2_supported(void) return stage2_supported; } +static const struct dt_device_match ipmmu_dt_match[] __initconst = +{ + { + .compatible = "renesas,ipmmu-r8a7795", + .data = &ipmmu_features_rcar_gen3, + }, + { + .compatible = "renesas,ipmmu-r8a77965", + .data = &ipmmu_features_rcar_gen3, + }, + { + .compatible = "renesas,ipmmu-r8a7796", + .data = &ipmmu_features_rcar_gen3, + }, + { + .compatible = "renesas,ipmmu-r8a77961", + .data = &ipmmu_features_rcar_gen3, + }, + { /* sentinel */ }, +}; + /* * This function relies on the fact that Root IPMMU device is being probed * the first. If not the case, it denies further Cache IPMMU device probes @@ -806,6 +837,7 @@ static __init bool ipmmu_stage2_supported(void) */ static int ipmmu_probe(struct dt_device_node *node) { + const struct dt_device_match *match; struct ipmmu_vmsa_device *mmu; uint64_t addr, size; int irq, ret; @@ -817,9 +849,12 @@ static int ipmmu_probe(struct dt_device_node *node) return -ENOMEM; } + match = dt_match_node(ipmmu_dt_match, node); + ASSERT(match); + mmu->features = match->data; + mmu->dev = &node->dev; - mmu->num_utlbs = IPMMU_UTLB_MAX; - mmu->num_ctx = IPMMU_CTX_MAX; + mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); spin_lock_init(&mmu->lock); bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); @@ -1296,15 +1331,6 @@ static const struct iommu_ops ipmmu_iommu_ops = .add_device = ipmmu_add_device, }; -static const struct dt_device_match ipmmu_dt_match[] __initconst = -{ - DT_MATCH_COMPATIBLE("renesas,ipmmu-r8a7795"), - DT_MATCH_COMPATIBLE("renesas,ipmmu-r8a77965"), - DT_MATCH_COMPATIBLE("renesas,ipmmu-r8a7796"), - DT_MATCH_COMPATIBLE("renesas,ipmmu-r8a77961"), - { /* sentinel */ }, -}; - static __init int ipmmu_init(struct dt_device_node *node, const void *data) { int ret; From patchwork Mon Dec 20 21:15:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5DB3C4321E for ; Mon, 20 Dec 2021 21:16:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.249997.430514 (Exim 4.92) (envelope-from ) id 1mzQ17-0005uL-3h; Mon, 20 Dec 2021 21:16:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 249997.430514; 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No behavior change. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Almost the same change as original commit makes, but without updating struct ipmmu_features_default which Xen driver doesn't have (there is no support of old Arm32 based Gen2 SoCs). No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 369be4c..ca33456 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -109,6 +109,8 @@ struct ipmmu_vmsa_xen_device { struct ipmmu_features { unsigned int number_of_contexts; unsigned int num_utlbs; + unsigned int ctx_offset_base; + unsigned int ctx_offset_stride; }; /* Root/Cache IPMMU device's information */ @@ -167,8 +169,6 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define TLB_LOOP_TIMEOUT 100 /* 100us */ /* Registers Definition */ -#define IM_CTX_SIZE 0x40 - #define IMCTR 0x0000 /* * This field is implemented in IPMMU-MM only. So, can be set for @@ -315,7 +315,8 @@ static void ipmmu_write(struct ipmmu_vmsa_device *mmu, uint32_t offset, static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, unsigned int context_id, uint32_t reg) { - return context_id * IM_CTX_SIZE + reg; + return mmu->features->ctx_offset_base + + context_id * mmu->features->ctx_offset_stride + reg; } static uint32_t ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, @@ -735,6 +736,8 @@ static int ipmmu_init_platform_device(struct device *dev, static const struct ipmmu_features ipmmu_features_rcar_gen3 = { .number_of_contexts = 8, .num_utlbs = 48, + .ctx_offset_base = 0, + .ctx_offset_stride = 0x40, }; static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) From patchwork Mon Dec 20 21:15:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9946C433FE for ; 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No behavior change. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Niklas Söderlund Signed-off-by: Joerg Roedel ********** This is a prereq work needed to add support for S4 series easily in the future. Almost the same change as original commit makes, but without updating struct ipmmu_features_default which Xen driver doesn't have (there is no support of old Arm32 based Gen2 SoCs). No change in behavior. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index ca33456..d8f96fc 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -111,6 +111,7 @@ struct ipmmu_features { unsigned int num_utlbs; unsigned int ctx_offset_base; unsigned int ctx_offset_stride; + unsigned int utlb_offset_base; }; /* Root/Cache IPMMU device's information */ @@ -374,7 +375,7 @@ static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, static uint32_t ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, uint32_t reg) { - return reg; + return mmu->features->utlb_offset_base + reg; } static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu, @@ -738,6 +739,7 @@ static const struct ipmmu_features ipmmu_features_rcar_gen3 = { .num_utlbs = 48, .ctx_offset_base = 0, .ctx_offset_stride = 0x40, + .utlb_offset_base = 0, }; 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Mon, 20 Dec 2021 13:16:19 -0800 (PST) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Jan Beulich , Paul Durrant , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Yoshihiro Shimoda , Oleksandr Andrushchenko Subject: [PATCH V2 07/10] iommu/ipmmu-vmsa: Add Renesas R8A779F0 (R-Car S4) support Date: Mon, 20 Dec 2021 23:15:54 +0200 Message-Id: <1640034957-19764-8-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> References: <1640034957-19764-1-git-send-email-olekstysh@gmail.com> MIME-Version: 1.0 From: Oleksandr Tyshchenko Based on the following Linux upsteam commit: 7a62ced8ebd0e1b692c9dc4781a8d4ddb0f74792 Original commit message: commit 7a62ced8ebd0e1b692c9dc4781a8d4ddb0f74792 Author: Yoshihiro Shimoda Date: Tue Sep 7 17:30:20 2021 +0900 iommu/ipmmu-vmsa: Add support for r8a779a0 Add support for r8a779a0 (R-Car V3U). The IPMMU hardware design of this SoC differs than others. So, add a new ipmmu_features for it. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20210907083020.907648-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Joerg Roedel ********** The R-Car S4 is an automotive System-on-Chip (SoC) for Car Server/Communication Gateway and is one of the first products in Renesas’ 4th-generation R-Car Family. The integrated IOMMU HW is also VMSA-compatible and supports stage 2 translation table format, therefore can be used with current driver with slight modifications (thanks to the prereq work). In the context of Xen driver the main differences between Gen3 and Gen4 are the following: - HW capacity was enlarged to support up to 16 IPMMU contexts (sets of page table) and up to 64 micro-TLBs per IPMMU device - the memory mapped registers have different bases and offsets Please note that Linux upstream doesn't support R-Car S4 SoC yet unlike Renesas BSP [1], but it was decided to reuse upstream patch for R-Car V3U anyway as the IPMMU HW settings are similar. [1] 7003b9f732cf iommu/ipmmu-vmsa: Add Renesas R8A779F0 (R-Car S4) support https://github.com/renesas-rcar/linux-bsp/tree/v5.10.41/rcar-5.1.3.rc5 Signed-off-by: Oleksandr Tyshchenko Signed-off-by: Oleksandr Andrushchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - base on the Linux upsteam patch instead of BSP's one - update patch description and comments in code - replace ipmmu_features_rcar_s4 with ipmmu_features_rcar_gen4 - introduce control_offset_base field --- xen/drivers/passthrough/Kconfig | 6 +-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 63 +++++++++++++++++++++++--------- 2 files changed, 49 insertions(+), 20 deletions(-) diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kconfig index 09505aa..479d7de 100644 --- a/xen/drivers/passthrough/Kconfig +++ b/xen/drivers/passthrough/Kconfig @@ -25,14 +25,14 @@ config ARM_SMMU_V3 the ARM SMMUv3 architecture. config IPMMU_VMSA - bool "Renesas IPMMU-VMSA found in R-Car Gen3 SoCs" + bool "Renesas IPMMU-VMSA found in R-Car Gen3/Gen4 SoCs" depends on ARM_64 ---help--- Support for implementations of the Renesas IPMMU-VMSA found - in R-Car Gen3 SoCs. + in R-Car Gen3/Gen4 SoCs. Say Y here if you are using newest R-Car Gen3 SoCs revisions - (H3 ES3.0, M3-W+, etc) which IPMMU hardware supports stage 2 + (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports stage 2 translation table format and is able to use CPU's P2M table as is. endif diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index d8f96fc..14848ce 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1,15 +1,15 @@ /* * xen/drivers/passthrough/arm/ipmmu-vmsa.c * - * Driver for the Renesas IPMMU-VMSA found in R-Car Gen3 SoCs. + * Driver for the Renesas IPMMU-VMSA found in R-Car Gen3/Gen4 SoCs. * * The IPMMU-VMSA is VMSA-compatible I/O Memory Management Unit (IOMMU) * which provides address translation and access protection functionalities * to processing units and interconnect networks. * * Please note, current driver is supposed to work only with newest - * R-Car Gen3 SoCs revisions which IPMMU hardware supports stage 2 translation - * table format and is able to use CPU's P2M table as is. + * R-Car Gen3/Gen4 SoCs revisions which IPMMU hardware supports stage 2 + * translation table format and is able to use CPU's P2M table as is. * * Based on Linux's IPMMU-VMSA driver from Renesas BSP: * drivers/iommu/ipmmu-vmsa.c @@ -20,9 +20,9 @@ * and Xen's SMMU driver: * xen/drivers/passthrough/arm/smmu.c * - * Copyright (C) 2014-2019 Renesas Electronics Corporation + * Copyright (C) 2014-2021 Renesas Electronics Corporation * - * Copyright (C) 2016-2019 EPAM Systems Inc. + * Copyright (C) 2016-2021 EPAM Systems Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms and conditions of the GNU General Public @@ -68,12 +68,13 @@ dev_print(dev, XENLOG_ERR, fmt, ## __VA_ARGS__) /* - * R-Car Gen3 SoCs make use of up to 8 IPMMU contexts (sets of page table) and - * these can be managed independently. Each context is mapped to one Xen domain. + * R-Car Gen3/Gen4 SoCs make use of up to 16 IPMMU contexts (sets of page table) + * and these can be managed independently. Each context is mapped to one Xen + * domain. */ -#define IPMMU_CTX_MAX 8U -/* R-Car Gen3 SoCs make use of up to 48 micro-TLBs per IPMMU device. */ -#define IPMMU_UTLB_MAX 48U +#define IPMMU_CTX_MAX 16U +/* R-Car Gen3/Gen4 SoCs make use of up to 64 micro-TLBs per IPMMU device. */ +#define IPMMU_UTLB_MAX 64U /* IPMMU context supports IPA size up to 40 bit. */ #define IPMMU_MAX_P2M_IPA_BITS 40 @@ -112,6 +113,8 @@ struct ipmmu_features { unsigned int ctx_offset_base; unsigned int ctx_offset_stride; unsigned int utlb_offset_base; + unsigned int control_offset_base; + unsigned int imuctr_ttsel_mask; }; /* Root/Cache IPMMU device's information */ @@ -211,7 +214,6 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUCTR0(n) (0x0300 + ((n) * 16)) #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) #define IMUCTR_TTSEL_MMU(n) ((n) << 4) -#define IMUCTR_TTSEL_MASK (15 << 4) #define IMUCTR_TTSEL_SHIFT 4 #define IMUCTR_FLUSH (1 << 1) #define IMUCTR_MMUEN (1 << 0) @@ -316,8 +318,12 @@ static void ipmmu_write(struct ipmmu_vmsa_device *mmu, uint32_t offset, static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, unsigned int context_id, uint32_t reg) { - return mmu->features->ctx_offset_base + - context_id * mmu->features->ctx_offset_stride + reg; + unsigned int base = mmu->features->ctx_offset_base; + + if ( context_id > 7 ) + base += 0x800 - 8 * 0x40; + + return base + context_id * mmu->features->ctx_offset_stride + reg; } static uint32_t ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, @@ -448,7 +454,8 @@ static int ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, { unsigned int context_id; - context_id = (imuctr & IMUCTR_TTSEL_MASK) >> IMUCTR_TTSEL_SHIFT; + context_id = (imuctr & mmu->features->imuctr_ttsel_mask) >> + IMUCTR_TTSEL_SHIFT; if ( domain->context_id != context_id ) { dev_err(mmu->dev, "Micro-TLB %u already assigned to IPMMU context %u\n", @@ -740,6 +747,18 @@ static const struct ipmmu_features ipmmu_features_rcar_gen3 = { .ctx_offset_base = 0, .ctx_offset_stride = 0x40, .utlb_offset_base = 0, + .control_offset_base = 0, + .imuctr_ttsel_mask = (15 << 4), +}; + +static const struct ipmmu_features ipmmu_features_rcar_gen4 = { + .number_of_contexts = 16, + .num_utlbs = 64, + .ctx_offset_base = 0x10000, + .ctx_offset_stride = 0x1040, + .utlb_offset_base = 0x3000, + .control_offset_base = 0x1000, + .imuctr_ttsel_mask = (31 << 4), }; static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) @@ -751,11 +770,12 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) ipmmu_ctx_write(mmu, i, IMCTR, 0); } -/* R-Car Gen3 SoCs product and cut information. */ +/* R-Car Gen3/Gen4 SoCs product and cut information. */ #define RCAR_PRODUCT_MASK 0x00007F00 #define RCAR_PRODUCT_H3 0x00004F00 #define RCAR_PRODUCT_M3W 0x00005200 #define RCAR_PRODUCT_M3N 0x00005500 +#define RCAR_PRODUCT_S4 0x00005A00 #define RCAR_CUT_MASK 0x000000FF #define RCAR_CUT_VER30 0x00000020 @@ -803,6 +823,10 @@ static __init bool ipmmu_stage2_supported(void) stage2_supported = true; break; + case RCAR_PRODUCT_S4: + stage2_supported = true; + break; + default: printk(XENLOG_ERR "ipmmu: Unsupported SoC version\n"); break; @@ -831,6 +855,10 @@ static const struct dt_device_match ipmmu_dt_match[] __initconst = .compatible = "renesas,ipmmu-r8a77961", .data = &ipmmu_features_rcar_gen3, }, + { + .compatible = "renesas,ipmmu-r8a779f0", + .data = &ipmmu_features_rcar_gen4, + }, { /* sentinel */ }, }; @@ -845,6 +873,7 @@ static int ipmmu_probe(struct dt_device_node *node) const struct dt_device_match *match; struct ipmmu_vmsa_device *mmu; uint64_t addr, size; + uint32_t reg; int irq, ret; mmu = xzalloc(struct ipmmu_vmsa_device); @@ -930,8 +959,8 @@ static int ipmmu_probe(struct dt_device_node *node) * Use stage 2 translation table format when stage 2 translation * enabled. */ - ipmmu_write(mmu, IMSAUXCTLR, - ipmmu_read(mmu, IMSAUXCTLR) | IMSAUXCTLR_S2PTE); + reg = IMSAUXCTLR + mmu->features->control_offset_base; + ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) | IMSAUXCTLR_S2PTE); dev_info(&node->dev, "IPMMU context 0 is reserved\n"); set_bit(0, mmu->ctx); From patchwork Mon Dec 20 21:15:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B1F2C4167B for ; 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Signed-off-by: Nam Nguyen commit a8d93bc07da89a7fcf4d85f34d119a030310efa5 Author: Nam Nguyen Date: Tue Sep 7 14:46:12 2021 +0700 iommu/ipmmu-vmsa: Update IMSCTLR register offset address for R-Car S4 Update IMSCTLR register offset address to align with R-Car S4 H/W UM. Signed-off-by: Nam Nguyen ********** It is still a question whether this really needs to be done in Xen, rather in firmware, but better to be on the safe side. After all, if firmware already takes care of clearing this bit, nothing bad will happen. Please note the following: 1. I decided to squash both commits since the first commit adds clearing code and only the second one makes it functional on S4. Moreover, this is not a direct port. So it would be better to introduce complete solution by a single patch. 2. Although patch indeed does what it claims in the subject, the implementation is different in comparison with original changes. On Linux the clearing is done at runtime in ipmmu_domain_setup_context(). On Xen the clearing is done at boot time in ipmmu_probe(). The IMSCTLR is not a MMU "context" register at all, so I think there is no point in performing the clearing each time we initialize the context, instead perform the clearing at once during initialization. Also do not abuse ctx_offset_stride_adj field for the register's offset calculation, instead use recently added control_offset_base field. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Volodymyr Babchuk Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b - update patch description - replace ctx_offset_stride_adj with control_offset_base for register's offset calculation --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 14848ce..649b9f6 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -222,6 +222,9 @@ static DEFINE_SPINLOCK(ipmmu_devices_lock); #define IMUASID0(n) (0x0308 + ((n) * 16)) #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) +#define IMSCTLR 0x0500 +#define IMSCTLR_USE_SECGRP (1 << 28) + #define IMSAUXCTLR 0x0504 #define IMSAUXCTLR_S2PTE (1 << 3) @@ -966,6 +969,10 @@ static int ipmmu_probe(struct dt_device_node *node) set_bit(0, mmu->ctx); } + /* Do not use security group function. */ + reg = IMSCTLR + mmu->features->control_offset_base; + ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) & ~IMSCTLR_USE_SECGRP); + spin_lock(&ipmmu_devices_lock); list_add(&mmu->list, &ipmmu_devices); spin_unlock(&ipmmu_devices_lock); From patchwork Mon Dec 20 21:15:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41760C433FE for ; Mon, 20 Dec 2021 21:16:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.250001.430567 (Exim 4.92) (envelope-from ) id 1mzQ1B-0007KU-R4; Mon, 20 Dec 2021 21:16:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 250001.430567; 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Mon, 20 Dec 2021 13:16:21 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 14a0a55c-61da-11ec-85d3-df6b77346a89 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ruH/ZtUTmX8iN6zofPsz6r1KAf8lKOAgjKOqJDL6kwU=; b=CDMSfqEUyrVBM25MEGIzHLeoHcUFlBF7AVUEDESUE2sPkWXL1Pj7uRg78VNv5JoKuc 54fvBdonm1Nq4ZFPMqV5wAT0Burub2MDNaPv3jjEddM4NEa4TLhHI/nQIAGNranFaIv3 +JXNyPkx9D5HBA/g/4ar7r/RDoZ3Z9N8I6JA/QgJNtlJRziKacOOxL/xiKvpeibC6htM JnUDFzpcJqsHwPYmUrz2IxA+MQSteMNkPsvdiRFcYB9H28gvILoJVOoqN6Cl3MK0ajI3 CfgvX7UrBZdqSEGs4wwbU/zALJm1rUmGQOGszcuDxqlTITemRI+rvjGe9AsDNfT+0ccm HwnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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This wasn't an issue so far, since the platform devices (this driver deals with) get assigned/deassigned together during domain creation/destruction. But, in order to support PCI devices (which are hot-pluggable) in the near future we will need to take care of. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b - add ASSERT() in ipmmu_utlb_disable() --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 649b9f6..1224ea4 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -127,6 +127,7 @@ struct ipmmu_vmsa_device { spinlock_t lock; /* Protects ctx and domains[] */ DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; + unsigned int utlb_refcount[IPMMU_UTLB_MAX]; const struct ipmmu_features *features; }; @@ -467,13 +468,12 @@ static int ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, } } - /* - * TODO: Reference-count the micro-TLB as several bus masters can be - * connected to the same micro-TLB. - */ - ipmmu_imuasid_write(mmu, utlb, 0); - ipmmu_imuctr_write(mmu, utlb, imuctr | - IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_MMUEN); + if ( mmu->utlb_refcount[utlb]++ == 0 ) + { + ipmmu_imuasid_write(mmu, utlb, 0); + ipmmu_imuctr_write(mmu, utlb, imuctr | + IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_MMUEN); + } return 0; } @@ -484,7 +484,10 @@ static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, { struct ipmmu_vmsa_device *mmu = domain->mmu; - ipmmu_imuctr_write(mmu, utlb, 0); + ASSERT(mmu->utlb_refcount[utlb] > 0); + + if ( --mmu->utlb_refcount[utlb] == 0 ) + ipmmu_imuctr_write(mmu, utlb, 0); } /* Domain/Context Management */ From patchwork Mon Dec 20 21:15:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 12688627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DEE7C4167D for ; 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Move this code to common arch_iommu_hwdom_init() in order to get rid of code duplication. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Volodymyr Babchuk Reviewed-by: Yoshihiro Shimoda --- Changes V1 -> V2: - add R-b --- xen/drivers/passthrough/arm/iommu.c | 7 +++++++ xen/drivers/passthrough/arm/ipmmu-vmsa.c | 8 -------- xen/drivers/passthrough/arm/smmu-v3.c | 10 ---------- xen/drivers/passthrough/arm/smmu.c | 10 ---------- 4 files changed, 7 insertions(+), 28 deletions(-) diff --git a/xen/drivers/passthrough/arm/iommu.c b/xen/drivers/passthrough/arm/iommu.c index ee653a9..fc45318 100644 --- a/xen/drivers/passthrough/arm/iommu.c +++ b/xen/drivers/passthrough/arm/iommu.c @@ -134,6 +134,13 @@ void arch_iommu_domain_destroy(struct domain *d) void __hwdom_init arch_iommu_hwdom_init(struct domain *d) { + /* Set to false options not supported on ARM. */ + if ( iommu_hwdom_inclusive ) + printk(XENLOG_WARNING "map-inclusive dom0-iommu option is not supported on ARM\n"); + iommu_hwdom_inclusive = false; + if ( iommu_hwdom_reserved == 1 ) + printk(XENLOG_WARNING "map-reserved dom0-iommu option is not supported on ARM\n"); + iommu_hwdom_reserved = 0; } /* diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 1224ea4..64d8ddc 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1325,14 +1325,6 @@ static int ipmmu_iommu_domain_init(struct domain *d) static void __hwdom_init ipmmu_iommu_hwdom_init(struct domain *d) { - /* Set to false options not supported on ARM. */ - if ( iommu_hwdom_inclusive ) - printk(XENLOG_WARNING "ipmmu: map-inclusive dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_inclusive = false; - if ( iommu_hwdom_reserved == 1 ) - printk(XENLOG_WARNING "ipmmu: map-reserved dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_reserved = 0; - arch_iommu_hwdom_init(d); } diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index d115df7..ca8b5c7 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3404,16 +3404,6 @@ static int arm_smmu_iommu_xen_domain_init(struct domain *d) static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d) { - /* Set to false options not supported on ARM. */ - if (iommu_hwdom_inclusive) - printk(XENLOG_WARNING - "map-inclusive dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_inclusive = false; - if (iommu_hwdom_reserved == 1) - printk(XENLOG_WARNING - "map-reserved dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_reserved = 0; - arch_iommu_hwdom_init(d); } diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index c9dfc4c..ec18df7 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2851,16 +2851,6 @@ static int arm_smmu_iommu_domain_init(struct domain *d) static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d) { - /* Set to false options not supported on ARM. */ - if ( iommu_hwdom_inclusive ) - printk(XENLOG_WARNING - "map-inclusive dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_inclusive = false; - if ( iommu_hwdom_reserved == 1 ) - printk(XENLOG_WARNING - "map-reserved dom0-iommu option is not supported on ARM\n"); - iommu_hwdom_reserved = 0; - arch_iommu_hwdom_init(d); }