From patchwork Tue Dec 21 08:16:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12689249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E983C433EF for ; Tue, 21 Dec 2021 08:17:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234292AbhLUIRK (ORCPT ); Tue, 21 Dec 2021 03:17:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231856AbhLUIRJ (ORCPT ); Tue, 21 Dec 2021 03:17:09 -0500 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D70AC061574 for ; Tue, 21 Dec 2021 00:17:09 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id r138so11672214pgr.13 for ; Tue, 21 Dec 2021 00:17:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aRLeyWGQmaBIGWQYdaMGRPHT7zgXBAkrj+tRLFqqHo=; b=Exv7CVPLc3Ol0D/FD20r5qL3WzVs1zpkuZ3t7XE5xevhCCp3kjv3VPwaG7ApU2/crz z9q58+4cX7QsaKPAAFB/UlPRJdQgt8zlMGVUwwcsKUdAwx0tSlAI+DMg4O0G/EBCU7Fz Ra+iEWxZQDX50pVmIAt1j/ylRBKL4FBIi7TPral7jrarQnwntWI8x7FL8NBVKAzqB/d2 ujYI1HCaa4oM05llgIfHgmXBIy8coMXi0GxMsz+I3vks/svM9T1DTsFSc+X0Pmu0Kxnu DC/I7sOqeCaylay38XxQOxliZyUEOMsdJhm3FT2yyCO7+SBNq9A8ubyUJ2CMyBsxxE16 ImOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9aRLeyWGQmaBIGWQYdaMGRPHT7zgXBAkrj+tRLFqqHo=; b=e+Z+2W/bRXD/1nQ+sG40QPTz71efH+LjVfKwp5L/3UEc4BVnDi5/yxzVf+86aJNExE 1Ky2ZG/wEhYaQhCt2dJYP74GSjr1w0rw/pw8Fa+VqiO8LzFGB0/Suxg8gDtpBShItitr 1KQ+BKTtblYoMgzACG7tBHwB48G6eCr7LfFLu8StUrJif3a6e0/tULMe0zGYz6d6t7nk hayD2hf3d23p11WRE2rzit6HkryYzs+QlylEE4zYJCaD/eRfsa3Wkd6cOFITfMwvnhx1 iBMrNjKjP2RJLZtufzhXGux7hCLYyHV32JhrN8HFGQdjXGmqA2RBqi+VbwHfr0wh6k87 Nmsg== X-Gm-Message-State: AOAM533GtSnMIkuZ7sLl3wJTbtCOcVcz2/xWOXfUVjjagjFzJ7CxEDu9 Izo3UMcLzCsRlcaHfRtx0sM= X-Google-Smtp-Source: ABdhPJzDHgVhxjgqgMa0Unc8HDx7qLqsx3OSfbQ9DC5SFtHewIV6c6qHVeM/FWXwuoMhQ2ANKdQZhA== X-Received: by 2002:a05:6a00:8cf:b0:4ba:4647:51bc with SMTP id s15-20020a056a0008cf00b004ba464751bcmr2037673pfu.18.1640074629149; Tue, 21 Dec 2021 00:17:09 -0800 (PST) Received: from localhost.localdomain ([37.120.154.44]) by smtp.gmail.com with ESMTPSA id b6sm21196890pfm.170.2021.12.21.00.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Dec 2021 00:17:08 -0800 (PST) From: William Breathitt Gray To: gregkh@linuxfoundation.org Cc: jic23@kernel.org, linux-iio@vger.kernel.org, Yanteng Si , Yanteng Si , William Breathitt Gray Subject: [PATCH 1/3] counter: Add the necessary colons and indents to the comments of counter_compi Date: Tue, 21 Dec 2021 17:16:46 +0900 Message-Id: <26011e814d6eca02c7ebdbb92f171a49928a7e89.1640072891.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Yanteng Si Since commit aaec1a0f76ec ("counter: Internalize sysfs interface code") introduce a warning as: linux-next/Documentation/driver-api/generic-counter:234: ./include/linux/counter.h:43: WARNING: Unexpected indentation. linux-next/Documentation/driver-api/generic-counter:234: ./include/linux/counter.h:45: WARNING: Block quote ends without a blank line; unexpected unindent. Add the necessary colons and indents. Signed-off-by: Yanteng Si Fixes: aaec1a0f76ec ("counter: Internalize sysfs interface code") Signed-off-by: William Breathitt Gray --- include/linux/counter.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/include/linux/counter.h b/include/linux/counter.h index b7d0a00a61cf..dfbde2808998 100644 --- a/include/linux/counter.h +++ b/include/linux/counter.h @@ -38,64 +38,64 @@ enum counter_comp_type { * @type: Counter component data type * @name: device-specific component name * @priv: component-relevant data - * @action_read Synapse action mode read callback. The read value of the + * @action_read: Synapse action mode read callback. The read value of the * respective Synapse action mode should be passed back via * the action parameter. - * @device_u8_read Device u8 component read callback. The read value of the + * @device_u8_read: Device u8 component read callback. The read value of the * respective Device u8 component should be passed back via * the val parameter. - * @count_u8_read Count u8 component read callback. The read value of the + * @count_u8_read: Count u8 component read callback. The read value of the * respective Count u8 component should be passed back via * the val parameter. - * @signal_u8_read Signal u8 component read callback. The read value of the + * @signal_u8_read: Signal u8 component read callback. The read value of the * respective Signal u8 component should be passed back via * the val parameter. - * @device_u32_read Device u32 component read callback. The read value of + * @device_u32_read: Device u32 component read callback. The read value of * the respective Device u32 component should be passed * back via the val parameter. - * @count_u32_read Count u32 component read callback. The read value of the + * @count_u32_read: Count u32 component read callback. The read value of the * respective Count u32 component should be passed back via * the val parameter. - * @signal_u32_read Signal u32 component read callback. The read value of + * @signal_u32_read: Signal u32 component read callback. The read value of * the respective Signal u32 component should be passed * back via the val parameter. - * @device_u64_read Device u64 component read callback. The read value of + * @device_u64_read: Device u64 component read callback. The read value of * the respective Device u64 component should be passed * back via the val parameter. - * @count_u64_read Count u64 component read callback. The read value of the + * @count_u64_read: Count u64 component read callback. The read value of the * respective Count u64 component should be passed back via * the val parameter. - * @signal_u64_read Signal u64 component read callback. The read value of + * @signal_u64_read: Signal u64 component read callback. The read value of * the respective Signal u64 component should be passed * back via the val parameter. - * @action_write Synapse action mode write callback. The write value of + * @action_write: Synapse action mode write callback. The write value of * the respective Synapse action mode is passed via the * action parameter. - * @device_u8_write Device u8 component write callback. The write value of + * @device_u8_write: Device u8 component write callback. The write value of * the respective Device u8 component is passed via the val * parameter. - * @count_u8_write Count u8 component write callback. The write value of + * @count_u8_write: Count u8 component write callback. The write value of * the respective Count u8 component is passed via the val * parameter. - * @signal_u8_write Signal u8 component write callback. The write value of + * @signal_u8_write: Signal u8 component write callback. The write value of * the respective Signal u8 component is passed via the val * parameter. - * @device_u32_write Device u32 component write callback. The write value of + * @device_u32_write: Device u32 component write callback. The write value of * the respective Device u32 component is passed via the * val parameter. - * @count_u32_write Count u32 component write callback. The write value of + * @count_u32_write: Count u32 component write callback. The write value of * the respective Count u32 component is passed via the val * parameter. - * @signal_u32_write Signal u32 component write callback. The write value of + * @signal_u32_write: Signal u32 component write callback. The write value of * the respective Signal u32 component is passed via the * val parameter. - * @device_u64_write Device u64 component write callback. The write value of + * @device_u64_write: Device u64 component write callback. The write value of * the respective Device u64 component is passed via the * val parameter. - * @count_u64_write Count u64 component write callback. The write value of + * @count_u64_write: Count u64 component write callback. The write value of * the respective Count u64 component is passed via the val * parameter. - * @signal_u64_write Signal u64 component write callback. The write value of + * @signal_u64_write: Signal u64 component write callback. The write value of * the respective Signal u64 component is passed via the * val parameter. */ From patchwork Tue Dec 21 08:16:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12689251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD1BC433EF for ; Tue, 21 Dec 2021 08:17:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231856AbhLUIRN (ORCPT ); Tue, 21 Dec 2021 03:17:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234316AbhLUIRM (ORCPT ); Tue, 21 Dec 2021 03:17:12 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F057C061574 for ; Tue, 21 Dec 2021 00:17:12 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id r138so11672286pgr.13 for ; Tue, 21 Dec 2021 00:17:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jRify4V8vT0KGWGetZDy9/dHEzN+APIJ4WSTI6YZM+0=; b=im/gBXb2g/Yf2sf5orPe4XRaFd5fh+dzCCuycTNnaDhns4fKjXAI++HZBgPvbFfv2o M+orgjQ7nZ33KgDnnJ+kqhyqvcTXsXGWxBYVgumTYaEa6LMF5ldCpCsJW+xmi9VaNEFg pmjwqaAnLYNqKZ35Iwn5Dgf0fCEZVUJ4lveqpWUj/zleA9/G2opolPcM/jlElTIz2Lch IwtKU281/C1oaE6LoZXKmqLMZLYckkGjTGl56SedCwWLkujXvtYKne97WauYEvAFn6+S 1kIvM5RZ/TMCsezsKkj7vg1WoRboXFBDXHlTEOCiEhK4Gixzm29dZ/knSVJrOJHXJxiR R0Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jRify4V8vT0KGWGetZDy9/dHEzN+APIJ4WSTI6YZM+0=; b=ZbkFR7PtpKTudqUB83e0Gex+j3rmvmV3Jsd/07w4+aAF5FEWttEtridSeXP3W3gpRq lzFTHmROdS/yA0qyVIA0esRqJai6pARz4AZK6deVdCDDhV3h4no45T2YxlA8axCd7L6H r1gQAvdb5qjmI9bQlVLoe0ygvgpRdSDX53+F1g8uMLn8qH/ATuawmLGxOdtaE7lyi7QD 3cJilxbPypyIK7+CR2RNQlKKi3jKRRn3BfwKPznViT0qbOj4VCMM+U1+uf4sMWZ4I0x0 gxwIvaCoj7oUpEDOgOm/QoJif2Ioq/SJC6Q/XyeBNiicsL+He+iMV5nTEdkSd+W7hAz7 a4cQ== X-Gm-Message-State: AOAM5305uOUY0HDCK4/JzPYhGcj20GKapknTYS8+rhUdwqeKQW4NE/U3 Rv1Zitbg0x56R4ZdFiZ8ENk= X-Google-Smtp-Source: ABdhPJyiCkttDpoz7tsCU3UkqUg0cmyy1BRl/U6l+JGWL3vK2u/EOh3BkjuqBvbGIq6TO5ZFXTZFIg== X-Received: by 2002:a05:6a00:892:b0:4ba:12d5:1d4 with SMTP id q18-20020a056a00089200b004ba12d501d4mr2113787pfj.46.1640074632005; Tue, 21 Dec 2021 00:17:12 -0800 (PST) Received: from localhost.localdomain ([37.120.154.44]) by smtp.gmail.com with ESMTPSA id b6sm21196890pfm.170.2021.12.21.00.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Dec 2021 00:17:11 -0800 (PST) From: William Breathitt Gray To: gregkh@linuxfoundation.org Cc: jic23@kernel.org, linux-iio@vger.kernel.org, =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , David Lechner , William Breathitt Gray Subject: [PATCH 2/3] counter: ti-eqep: Use container_of instead of struct counter_device::priv Date: Tue, 21 Dec 2021 17:16:47 +0900 Message-Id: <4bde7cbd9e43a5909208102094444219d3154466.1640072891.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Uwe Kleine-König Using counter->priv is a memory read and so more expensive than container_of which is only an addition. (In this case even a noop because the offset is 0.) So container_of is expected to be a tad faster, it's type-safe, and produces smaller code (ARCH=arm allmodconfig): $ source/scripts/bloat-o-meter drivers/counter/ti-eqep.o-pre drivers/counter/ti-eqep.o add/remove: 0/0 grow/shrink: 0/9 up/down: 0/-108 (-108) Function old new delta ti_eqep_position_enable_write 132 120 -12 ti_eqep_position_enable_read 260 248 -12 ti_eqep_position_ceiling_write 132 120 -12 ti_eqep_position_ceiling_read 236 224 -12 ti_eqep_function_write 220 208 -12 ti_eqep_function_read 372 360 -12 ti_eqep_count_write 312 300 -12 ti_eqep_count_read 236 224 -12 ti_eqep_action_read 664 652 -12 Total: Before=4598, After=4490, chg -2.35% Signed-off-by: Uwe Kleine-König Acked-by: David Lechner Signed-off-by: William Breathitt Gray --- drivers/counter/ti-eqep.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/counter/ti-eqep.c b/drivers/counter/ti-eqep.c index 09817c953f9a..9e0e46bca4c2 100644 --- a/drivers/counter/ti-eqep.c +++ b/drivers/counter/ti-eqep.c @@ -87,10 +87,15 @@ struct ti_eqep_cnt { struct regmap *regmap16; }; +static struct ti_eqep_cnt *ti_eqep_count_from_counter(struct counter_device *counter) +{ + return container_of(counter, struct ti_eqep_cnt, counter); +} + static int ti_eqep_count_read(struct counter_device *counter, struct counter_count *count, u64 *val) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); u32 cnt; regmap_read(priv->regmap32, QPOSCNT, &cnt); @@ -102,7 +107,7 @@ static int ti_eqep_count_read(struct counter_device *counter, static int ti_eqep_count_write(struct counter_device *counter, struct counter_count *count, u64 val) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); u32 max; regmap_read(priv->regmap32, QPOSMAX, &max); @@ -116,7 +121,7 @@ static int ti_eqep_function_read(struct counter_device *counter, struct counter_count *count, enum counter_function *function) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); u32 qdecctl; regmap_read(priv->regmap16, QDECCTL, &qdecctl); @@ -143,7 +148,7 @@ static int ti_eqep_function_write(struct counter_device *counter, struct counter_count *count, enum counter_function function) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); enum ti_eqep_count_func qsrc; switch (function) { @@ -173,7 +178,7 @@ static int ti_eqep_action_read(struct counter_device *counter, struct counter_synapse *synapse, enum counter_synapse_action *action) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); enum counter_function function; u32 qdecctl; int err; @@ -245,7 +250,7 @@ static int ti_eqep_position_ceiling_read(struct counter_device *counter, struct counter_count *count, u64 *ceiling) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); u32 qposmax; regmap_read(priv->regmap32, QPOSMAX, &qposmax); @@ -259,7 +264,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter, struct counter_count *count, u64 ceiling) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); if (ceiling != (u32)ceiling) return -ERANGE; @@ -272,7 +277,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter, static int ti_eqep_position_enable_read(struct counter_device *counter, struct counter_count *count, u8 *enable) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); u32 qepctl; regmap_read(priv->regmap16, QEPCTL, &qepctl); @@ -285,7 +290,7 @@ static int ti_eqep_position_enable_read(struct counter_device *counter, static int ti_eqep_position_enable_write(struct counter_device *counter, struct counter_count *count, u8 enable) { - struct ti_eqep_cnt *priv = counter->priv; + struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter); regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0); From patchwork Tue Dec 21 08:16:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12689253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E574DC433EF for ; Tue, 21 Dec 2021 08:17:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235408AbhLUIRP (ORCPT ); Tue, 21 Dec 2021 03:17:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234316AbhLUIRP (ORCPT ); Tue, 21 Dec 2021 03:17:15 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF887C061574 for ; Tue, 21 Dec 2021 00:17:14 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id n15-20020a17090a394f00b001b0f6d6468eso1818813pjf.3 for ; Tue, 21 Dec 2021 00:17:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JjmeBVzpmVNuoVKPIAqqBFZFlEBd33RCxrYbf7EI4Z8=; b=SO/Zqg2JKypBzmuEAGJgMlaQUULw7eDDwZvAuqNlqmM6dn3QyTjNNsiCQcDTDi6KI0 RmWAtJ3LFtxU5rV1usPpL/i3S/d+L/kcvsLZ0kqDhOZMO07PzZNnb+odYyJOwQuP1EEl oKxNXRUd5vJ5r52nase4axHtiNzcHRub6WlrtPZ/JWw2053uB541nBCZ/2kFf6DfNjX1 VxOEtzYYo2RqDopVXgOdcoEdf3KMXOn6d+SLZVHbtzU0nvocOorCiY8Vf7dPJIO9s2lM 1DZaH6jTNfHuBH2u3dzd/lLIhI98hmVq3Qn9Zw3pZaaHtvyvT6qp7gfHuNyt3BAERqsj Ugsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjmeBVzpmVNuoVKPIAqqBFZFlEBd33RCxrYbf7EI4Z8=; b=4yAidzXzzrYjH/gkjfLjEGcR1qT6yZZpEzfAOadGBxSQkx4E+lKjEDINk15UWqmRTi TRKiWb6r8VpHZ1/mJGAM+iioRlbSMf4WgNFfJGoHIkFtiuEoj0FzAWl+29Rn2rjxylgk 8Fvn8skjQ+2pZnmPVakqv1fG0fTWYMXoKOPWKSzsbf7PhBraKojzAXKpwh6ipGhVCvDK 9jOJ88UNEZTdWFWdleYfNhXC0vFsWN6GDx6Eu14wAJQkKc7dYRPjpKqTVhzQsWNXBaeh iJ3duKIdqHvn0RLOYifT1xZ7kj3zCW71aALMl6dFPhXn0kyk6+WruxbdfLwMueO9QmOc NLKA== X-Gm-Message-State: AOAM533CKr0S7RU430N3EOW0Sg8lZJk4YDXIQ1fQH+rR5RIg1xrJrVJl mnfPqCew8UuAcv1Tv7zG/kQ= X-Google-Smtp-Source: ABdhPJw1w1NnrtAULaB47cl61CQ10ImdldglwV2wnzSFQe6nvytmPXdm3jS5NY4bRoK+1ov5qyjppw== X-Received: by 2002:a17:90b:198d:: with SMTP id mv13mr2860408pjb.182.1640074634454; Tue, 21 Dec 2021 00:17:14 -0800 (PST) Received: from localhost.localdomain ([37.120.154.44]) by smtp.gmail.com with ESMTPSA id b6sm21196890pfm.170.2021.12.21.00.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Dec 2021 00:17:14 -0800 (PST) From: William Breathitt Gray To: gregkh@linuxfoundation.org Cc: jic23@kernel.org, linux-iio@vger.kernel.org, William Breathitt Gray , Syed Nayyar Waris Subject: [PATCH 3/3] counter: 104-quad-8: Fix persistent enabled events bug Date: Tue, 21 Dec 2021 17:16:48 +0900 Message-Id: <5fd5731cec1c251acee30eefb7c19160d03c9d39.1640072891.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org A bug exists if the user executes a COUNTER_ADD_WATCH_IOCTL ioctl call, and then executes a COUNTER_DISABLE_EVENTS_IOCTL ioctl call. Disabling the events should disable the 104-QUAD-8 interrupts, but because of this bug the interrupts are not disabling. The reason this bug is occurring is because quad8_events_configure() is called when COUNTER_DISABLE_EVENTS_IOCTL is handled, but the next_irq_trigger[] array has not been cleared before it is checked in the loop. This patch fixes the bug by removing the next_irq_trigger array and instead utilizing a different algorithm of walking the events_list list for the current requested events. When a COUNTER_DISABLE_EVENTS_IOCTL is handled, events_list will be empty and thus all device channels end up with interrupts disabled. Fixes: 7aa2ba0df651 ("counter: 104-quad-8: Add IRQ support for the ACCES 104-QUAD-8") Cc: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 82 +++++++++++++++++------------------- 1 file changed, 39 insertions(+), 43 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index 1cbd60aaed69..a97027db0446 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,6 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers"); * @ab_enable: array of A and B inputs enable configurations * @preset_enable: array of set_to_preset_on_index attribute configurations * @irq_trigger: array of current IRQ trigger function configurations - * @next_irq_trigger: array of next IRQ trigger function configurations * @synchronous_mode: array of index function synchronous mode configurations * @index_polarity: array of index function polarity configurations * @cable_fault_enable: differential encoder cable status enable configurations @@ -61,7 +61,6 @@ struct quad8 { unsigned int ab_enable[QUAD8_NUM_COUNTERS]; unsigned int preset_enable[QUAD8_NUM_COUNTERS]; unsigned int irq_trigger[QUAD8_NUM_COUNTERS]; - unsigned int next_irq_trigger[QUAD8_NUM_COUNTERS]; unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; @@ -390,7 +389,6 @@ static int quad8_action_read(struct counter_device *counter, } enum { - QUAD8_EVENT_NONE = -1, QUAD8_EVENT_CARRY = 0, QUAD8_EVENT_COMPARE = 1, QUAD8_EVENT_CARRY_BORROW = 2, @@ -402,34 +400,49 @@ static int quad8_events_configure(struct counter_device *counter) struct quad8 *const priv = counter->priv; unsigned long irq_enabled = 0; unsigned long irqflags; - size_t channel; + struct counter_event_node *event_node; + unsigned int next_irq_trigger; unsigned long ior_cfg; unsigned long base_offset; spin_lock_irqsave(&priv->lock, irqflags); - /* Enable interrupts for the requested channels, disable for the rest */ - for (channel = 0; channel < QUAD8_NUM_COUNTERS; channel++) { - if (priv->next_irq_trigger[channel] == QUAD8_EVENT_NONE) - continue; + list_for_each_entry(event_node, &counter->events_list, l) { + switch (event_node->event) { + case COUNTER_EVENT_OVERFLOW: + next_irq_trigger = QUAD8_EVENT_CARRY; + break; + case COUNTER_EVENT_THRESHOLD: + next_irq_trigger = QUAD8_EVENT_COMPARE; + break; + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: + next_irq_trigger = QUAD8_EVENT_CARRY_BORROW; + break; + case COUNTER_EVENT_INDEX: + next_irq_trigger = QUAD8_EVENT_INDEX; + break; + default: + /* should never reach this path */ + spin_unlock_irqrestore(&priv->lock, irqflags); + return -EINVAL; + } - if (priv->irq_trigger[channel] != priv->next_irq_trigger[channel]) { - /* Save new IRQ function configuration */ - priv->irq_trigger[channel] = priv->next_irq_trigger[channel]; + /* Skip configuration if it is the same as previously set */ + if (priv->irq_trigger[event_node->channel] == next_irq_trigger) + continue; - /* Load configuration to I/O Control Register */ - ior_cfg = priv->ab_enable[channel] | - priv->preset_enable[channel] << 1 | - priv->irq_trigger[channel] << 3; - base_offset = priv->base + 2 * channel + 1; - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); - } + /* Save new IRQ function configuration */ + priv->irq_trigger[event_node->channel] = next_irq_trigger; - /* Reset next IRQ trigger function configuration */ - priv->next_irq_trigger[channel] = QUAD8_EVENT_NONE; + /* Load configuration to I/O Control Register */ + ior_cfg = priv->ab_enable[event_node->channel] | + priv->preset_enable[event_node->channel] << 1 | + priv->irq_trigger[event_node->channel] << 3; + base_offset = priv->base + 2 * event_node->channel + 1; + outb(QUAD8_CTR_IOR | ior_cfg, base_offset); /* Enable IRQ line */ - irq_enabled |= BIT(channel); + irq_enabled |= BIT(event_node->channel); } outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); @@ -442,35 +455,20 @@ static int quad8_events_configure(struct counter_device *counter) static int quad8_watch_validate(struct counter_device *counter, const struct counter_watch *watch) { - struct quad8 *const priv = counter->priv; + struct counter_event_node *event_node; if (watch->channel > QUAD8_NUM_COUNTERS - 1) return -EINVAL; switch (watch->event) { case COUNTER_EVENT_OVERFLOW: - if (priv->next_irq_trigger[watch->channel] == QUAD8_EVENT_NONE) - priv->next_irq_trigger[watch->channel] = QUAD8_EVENT_CARRY; - else if (priv->next_irq_trigger[watch->channel] != QUAD8_EVENT_CARRY) - return -EINVAL; - return 0; case COUNTER_EVENT_THRESHOLD: - if (priv->next_irq_trigger[watch->channel] == QUAD8_EVENT_NONE) - priv->next_irq_trigger[watch->channel] = QUAD8_EVENT_COMPARE; - else if (priv->next_irq_trigger[watch->channel] != QUAD8_EVENT_COMPARE) - return -EINVAL; - return 0; case COUNTER_EVENT_OVERFLOW_UNDERFLOW: - if (priv->next_irq_trigger[watch->channel] == QUAD8_EVENT_NONE) - priv->next_irq_trigger[watch->channel] = QUAD8_EVENT_CARRY_BORROW; - else if (priv->next_irq_trigger[watch->channel] != QUAD8_EVENT_CARRY_BORROW) - return -EINVAL; - return 0; case COUNTER_EVENT_INDEX: - if (priv->next_irq_trigger[watch->channel] == QUAD8_EVENT_NONE) - priv->next_irq_trigger[watch->channel] = QUAD8_EVENT_INDEX; - else if (priv->next_irq_trigger[watch->channel] != QUAD8_EVENT_INDEX) - return -EINVAL; + list_for_each_entry(event_node, &counter->next_events_list, l) + if (watch->channel == event_node->channel && + watch->event != event_node->event) + return -EINVAL; return 0; default: return -EINVAL; @@ -1183,8 +1181,6 @@ static int quad8_probe(struct device *dev, unsigned int id) outb(QUAD8_CTR_IOR, base_offset + 1); /* Disable index function; negative index polarity */ outb(QUAD8_CTR_IDR, base_offset + 1); - /* Initialize next IRQ trigger function configuration */ - priv->next_irq_trigger[i] = QUAD8_EVENT_NONE; } /* Disable Differential Encoder Cable Status for all channels */ outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);