From patchwork Tue Dec 21 09:04:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 12689291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1FDDC433F5 for ; Tue, 21 Dec 2021 09:06:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236063AbhLUJGC (ORCPT ); Tue, 21 Dec 2021 04:06:02 -0500 Received: from mail-mw2nam12on2075.outbound.protection.outlook.com ([40.107.244.75]:19937 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236054AbhLUJF6 (ORCPT ); Tue, 21 Dec 2021 04:05:58 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DscEfVfHTSjfOqQIA3kZmztjgQb2X1jCwZTaX3cyGgK0p+8850vGSQ3PJItdZqaWLbkBgxteXkhQIKZuCkGbdUXbEzrCUrZPo6563DyWdq4f98Wtx35SGbU6NgUHSME+VsYWNQGTurKBaW9wQ/nhderk8VyoizrYekQ8c94F2r12KtXIr3BnnQKW9d03dWOvnzETzcXrcBhrF9NK2KTDDyv2F3RzpHVhWIZ+Z91xPF9itWtHAcmwrgyfWU8Kq4Vy66D8VaWTrooTzfpC+89BwU0wgRN0JNxt9T6ZZbPOyHf9nWozNs2POdLd0nH5vWdeyy1recxG2U7C12JFdX5Csw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=idCRmkspddIsTrTnN4sXVvRn11UCUN/PbBSkZZGaU2E=; b=D1DB6EnDf2N5FMKOMddZnYpOIJEveKbPdxhkFGOPUz2ZPHTfqVcu1Ut6vdYfzEgGVUe8zCqcTJ67wTPG4axm0NQxgWK4FoB4jjjm6zT6NzAPOFlxVa4VQ/4Sud4e8IAHmmy8uoHUdgVn1QprKaz2U18A1vIOTSPwUceyyAzCnR2sB1YxUEK3VtSio77/c2i4yXMKz4fLugWIAA3+6/3lRD60Ij47W0dnBqUShHvQDIImzk1d+eFlW1pmxbUMDd9oTCPo2xzS2HSnL76LnCDgnjE2C+vPvUeYTL6Af8I3/5+yK3scxLLAgObVaPjyC718BIMCOlOm+hXqMp2wKXDLYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=idCRmkspddIsTrTnN4sXVvRn11UCUN/PbBSkZZGaU2E=; b=GEHhEIQWpcHerJlo44rG22Q7eVItz1UHwpoAQgtHfdHuutKR7OOq2ki9ZfhLxZkVwbC42GQZDaG8xuvxCYjHkQpiLnmORbaiFSsjftZCUpustijKP4kGUawmLQ1aGUDXSBvbCMMo+oyXcOR/Ed40TesAKCLWKiUJwj3PtgjcGluMtwX9ZVpCZI5ddQtl+CXmN0i+xIUTypJhEIpe5lzOUs1B4PSCobfnPFeKHtwQ16/kJ84CfHT3Be85uACihUNaMJpfakWrNX+ekelyUEl0kQ+iUfnLj+8bznTnE45u/WYqUJBPMRlRIu+ht5nbgGEDNsDdROv1sZpo8ckLKRv7zg== Received: from DM5PR22CA0022.namprd22.prod.outlook.com (2603:10b6:3:101::32) by BY5PR12MB3811.namprd12.prod.outlook.com (2603:10b6:a03:1a1::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.14; Tue, 21 Dec 2021 09:05:56 +0000 Received: from DM6NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:3:101:cafe::1f) by DM5PR22CA0022.outlook.office365.com (2603:10b6:3:101::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.14 via Frontend Transport; Tue, 21 Dec 2021 09:05:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4801.14 via Frontend Transport; Tue, 21 Dec 2021 09:05:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 21 Dec 2021 09:05:55 +0000 Received: from foundations-user-AS-2114GT-DNR-C1-NC24B.nvidia.com (172.20.187.5) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Tue, 21 Dec 2021 01:05:54 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v2 1/3] KVM: x86: only allow exits disable before vCPUs created Date: Tue, 21 Dec 2021 01:04:47 -0800 Message-ID: <20211221090449.15337-2-kechenl@nvidia.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211221090449.15337-1-kechenl@nvidia.com> References: <20211221090449.15337-1-kechenl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bc8e974b-8d3f-47a6-9821-08d9c461190f X-MS-TrafficTypeDiagnostic: BY5PR12MB3811:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AyadwvcX7/8o7nbqCjbiUebcHeBsf9Mtd/2Ek33IWqMk/ruYbAfKCwE1QaPjaWTW5fbBWzYa8BHrRz+iFd9Rn6DZUenvn7Vi9nzQDoxstEPXd2ODZ2iyz415svfEbiGaVZg62UI/LiyyPnZI3DNjWTNTthFA8TWf7wZ8ZeiIukkDMyY0+RLAUow0KGoeQPa+32UMK3xzJRMvTNvX5pH3BM6wrej7EB9G24eGFhkfdgSsqP3hx6+Dx5ZR//Z4VctD/fmJhcNCnEH3ERaSta3h7V00QK7D6GqX51va5RY/K0WcyqoSQUb4YcnT1lXltcje+lph5FSf6S87efoVlpRSeKzrrgEzfTbVS3Rzy02tr9ihEK5eKLSlMKaQ3xyEJIdExRxtquhcc13d/SIfqMbBWISljxZV2cDS/6E+rk94iV9DCV7rd48Kzy5wu9S5UonN+kQLTeSEKzCs3kC4ESNh9J43n6jJNgcNgS9Q2XUKrmAsaZRL/jmdkBdrGfgCYyu1jU9Kbna5EElfDiN/jv7Pzjmcy+BAe1FXYSwsN+nmU55dkOnMR+GKM77qo4fuNMU85h9o05eCSlbUIMTekGHlSvVolUViIQ0otaXtndXHKpGtgzs7d6/wKZv+hEc9V8peQ3xHszEakqEqlO0795HyIeHKQqtQrBGjfvULqXtx5L0YVBKjNSd6YMtLN9jiJO1UXUCiWVSlGhtplpk2y+IKyS14+tn6iu9+o4ypX+bVrcM4NIA9Oge5OeWHar5NB8XUeo1avSKOVeeGlwjGEO1fM4I4XL9HHamiK6Jlh3+bHcVo6NaCM1IbthSYYTEgnM+BW7JXMxw9DkGBqSAuZpTo7A== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(36840700001)(40470700002)(46966006)(34020700004)(5660300002)(16526019)(36860700001)(426003)(8936002)(2906002)(186003)(40460700001)(336012)(36756003)(86362001)(1076003)(47076005)(4326008)(508600001)(26005)(70586007)(70206006)(54906003)(83380400001)(81166007)(8676002)(110136005)(2616005)(82310400004)(6666004)(316002)(356005)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2021 09:05:55.9802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc8e974b-8d3f-47a6-9821-08d9c461190f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3811 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since VMX and SVM both would never update the control bits if exits are disable after vCPUs are created, only allow setting exits disable flag before vCPU creation. Signed-off-by: Sean Christopherson Signed-off-by: Kechen Lu Reviewed-by: Sean Christopherson --- Documentation/virt/kvm/api.rst | 1 + arch/x86/kvm/x86.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index aeeb071c7688..d1c50b95bbc1 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6581,6 +6581,7 @@ branch to guests' 0x200 interrupt vector. :Architectures: x86 :Parameters: args[0] defines which exits are disabled :Returns: 0 on success, -EINVAL when args[0] contains invalid exits + or if any vCPU has already been created Valid bits in args[0] are:: diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0cf1082455df..37529c0c279d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5764,6 +5764,10 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) break; + mutex_lock(&kvm->lock); + if (kvm->created_vcpus) + goto disable_exits_unlock; + if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && kvm_can_mwait_in_guest()) kvm->arch.mwait_in_guest = true; @@ -5774,6 +5778,8 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) kvm->arch.cstate_in_guest = true; r = 0; +disable_exits_unlock: + mutex_unlock(&kvm->lock); break; case KVM_CAP_MSR_PLATFORM_INFO: kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; From patchwork Tue Dec 21 09:04:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 12689293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3FD8C433FE for ; Tue, 21 Dec 2021 09:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236068AbhLUJGF (ORCPT ); Tue, 21 Dec 2021 04:06:05 -0500 Received: from mail-dm6nam12on2082.outbound.protection.outlook.com ([40.107.243.82]:35732 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236047AbhLUJGD (ORCPT ); Tue, 21 Dec 2021 04:06:03 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gtdcJuFkKsVfCyb1DpIcswpmpbUM/UfNXnC0RjNJpw2MzVRa4m8orosOePWtizd+o0JrmZV11xSS4T2iHFVtvd0ms8DCfWzPxZphzHx8t6qFk6M1lYyakTCshg2uFkULnajxf63JCSokEhyjK3xCdh/Ul2Ey6bqnTqbdheSp7B3gj9ZCShoj5bIS+SNV4+ZwHbL0BHwS1GvjDcCWWNeDe3jgtvNg5uEpp4dJdDItqUS7CMCHrYiHxGfvouBtt5tsYueqKGMKGC512YOydNG7oaVasoaktjjpOf8JNkUcOtU6owJTgRElVKNZgVL8r2Ow6CarKn6NQjVNUikzm+yzyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NFlWtN0m9u3nySYIuFXarvk4b/75D6BLp51ZKBntxUc=; b=j/dGIeow+WZxN/YJMBQUVDszMVMRWsW8bigHcPzIDTnfhYxZklT8gU5tVu3AkC8sDocsQvVUUQyq3R9/JqNqJbVzK4qJusQINve5tSjTOqeX0oD+72TnJnMzG+KsBsMhABBTOfnXGjshjSpIJxrRkGP62N0veEXq2WJwlPdtk+kwBZ3aY0VjrdT1QX6MFISjF6kqDOi7EJmxG0/DZ+RNDeI9xYgYGWZ8Y7/t5lUKjfDcfEvRaemvgIxFF8Dae28eThKVIY0NN2rL0nPnYgmsmruizHCLubQw46znewOzALCuNMkknnWq5sJoL0TpYk66BFdFidQGhZvNGAvd4TjgRA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NFlWtN0m9u3nySYIuFXarvk4b/75D6BLp51ZKBntxUc=; b=W0MtiGrRKfxYcxxjeRM5C2BGQhVJJYbJWLPlmC1w72UCpqEprcSWnMyXTY1srYMua7ggupbtOmdRKKk2G9m6FlFjjKRAccfeOBqxdMA48M3QRvnS21lhODPD7dQ0/35Mj+2vMkdlN7Y72BO83yRnxGsXPwHSJ3oel4PtnNX4qHPt448OBYgTvOVuIPJ6rW3k+rV9sgCjZrP9FfKAqLb851ZjL7xXwA6nDcxy1jGjj78gSLeTBFbHhF+wF8DZoA1j50AOkzsK15h5zBXOroRGfRQMSf57nQI+ttrTcZtSP+EjLKewU/7X3nfesqV8DWccgKaP2+p7w+MZzSXuExZ59w== Received: from BN6PR11CA0068.namprd11.prod.outlook.com (2603:10b6:404:f7::30) by MN2PR12MB3790.namprd12.prod.outlook.com (2603:10b6:208:164::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Tue, 21 Dec 2021 09:06:01 +0000 Received: from BN8NAM11FT006.eop-nam11.prod.protection.outlook.com (2603:10b6:404:f7:cafe::38) by BN6PR11CA0068.outlook.office365.com (2603:10b6:404:f7::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4823.14 via Frontend Transport; Tue, 21 Dec 2021 09:06:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT006.mail.protection.outlook.com (10.13.177.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4801.14 via Frontend Transport; Tue, 21 Dec 2021 09:06:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 21 Dec 2021 09:06:00 +0000 Received: from foundations-user-AS-2114GT-DNR-C1-NC24B.nvidia.com (172.20.187.5) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Tue, 21 Dec 2021 01:05:59 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v2 2/3] KVM: x86: move ()_in_guest checking to vCPU scope Date: Tue, 21 Dec 2021 01:04:48 -0800 Message-ID: <20211221090449.15337-3-kechenl@nvidia.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211221090449.15337-1-kechenl@nvidia.com> References: <20211221090449.15337-1-kechenl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0cb56a21-efef-45a5-b519-08d9c4611c29 X-MS-TrafficTypeDiagnostic: MN2PR12MB3790:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:233; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BJ8lMehSXXanSyiSqhnJQfBmh2vsz0nj+Y22A3dhPUbQVFbWyitZj34NjWMxpDhM2Iia1ZdfElVgZ2pLeqxwW2HEI9gTFIwlAkZbp4ZYm1kCfTOJyOwBEHlAwuP5eDVnDZXUgmUvJ1/U80OTWayT+3p/mZEmrfASNlnz40raVC+N/+Zgg8WM1oK6HJeLg85dM7dX3SifsI12uKIAM1v6XqToSynclU94vlHwDEFXxqLEiTWuK2+/NI1f4rDP7qkUpqQfw55FYrhiW3VWkK2gsEvdfDy2GyNGIdJnB+liY9u0pjcA0jFMXXQ9yv9s4LPdj5AkkPdVN6L//Q0mZ2fUv/Kr4oO7JjscP5ZL9hlHONLXqEdDzvBOf3L9Po4QjhJ/XYNs4qqqkLQUE3gMkQiKm4gnR3Yd2AaQiTHYLvmsiaHTQYMa/ayVcFc3827ZUeXI0IDjMpQuvQ9RPO8+zRjpjfoQ7QoE+rzmizwGhNnMAumwdh+Q7C1uWTtEkLc8eKWW5lw+fuxaTZ9008DRHPEXKNcXKsi18GVic5AwiHmeynteM9AnU+bj8bE3Lcht8TD/WcyjSYRtRTH6PtXMfcBaXdFgLePme2Ik299O8dKmk8psUnCh/fMFb17JOzein2kYWUrOwn75QxWqFYjxctDJ8uufryBgnmgr/sZZ1xZphGQ7AzefWqf27vb0VqWGx8Bt0lnNW1zTkZE0ea7r15Jd2wqM5eYUnznjF/BbYBGJKByMX5mL1Zf68PXUGo9k8Sd2M8duza+ZuILp/ZR8YB6Xq/lS5L3049N6fwBf21cRAICFJ/053GqCImSFij/nwf2crHviSUwURRkb2pZfIix87A== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(40470700002)(46966006)(36840700001)(2906002)(336012)(7696005)(26005)(2616005)(70206006)(16526019)(6666004)(5660300002)(4326008)(70586007)(508600001)(8676002)(426003)(81166007)(54906003)(8936002)(110136005)(36860700001)(47076005)(34020700004)(1076003)(316002)(356005)(86362001)(83380400001)(36756003)(82310400004)(186003)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2021 09:06:01.0659 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cb56a21-efef-45a5-b519-08d9c4611c29 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3790 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For futher extensions on finer-grained control on per-vCPU exits disable control, and because VM-scoped restricted to set before vCPUs creation, runtime disabled exits flag check could be purely vCPU scope. Suggested-by: Sean Christopherson Signed-off-by: Kechen Lu Reviewed-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 5 +++++ arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/lapic.c | 2 +- arch/x86/kvm/svm/svm.c | 10 +++++----- arch/x86/kvm/vmx/vmx.c | 16 ++++++++-------- arch/x86/kvm/x86.c | 6 +++++- arch/x86/kvm/x86.h | 16 ++++++++-------- 7 files changed, 33 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 2164b9f4c7b0..edc5fca4d8c8 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -908,6 +908,11 @@ struct kvm_vcpu_arch { #if IS_ENABLED(CONFIG_HYPERV) hpa_t hv_root_tdp; #endif + + bool mwait_in_guest; + bool hlt_in_guest; + bool pause_in_guest; + bool cstate_in_guest; }; struct kvm_lpage_info { diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 07e9215e911d..6291e15710ba 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -177,7 +177,7 @@ void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) best->ebx = xstate_required_size(vcpu->arch.xcr0, true); best = kvm_find_kvm_cpuid_features(vcpu); - if (kvm_hlt_in_guest(vcpu->kvm) && best && + if (kvm_hlt_in_guest(vcpu) && best && (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index f206fc35deff..effb994e6642 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -119,7 +119,7 @@ static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu) bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu) { return kvm_x86_ops.set_hv_timer - && !(kvm_mwait_in_guest(vcpu->kvm) || + && !(kvm_mwait_in_guest(vcpu) || kvm_can_post_timer_interrupt(vcpu)); } EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d0f68d11ec70..70e393c6dfb5 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1271,12 +1271,12 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm_set_intercept(svm, INTERCEPT_RDPRU); svm_set_intercept(svm, INTERCEPT_RSM); - if (!kvm_mwait_in_guest(vcpu->kvm)) { + if (!kvm_mwait_in_guest(vcpu)) { svm_set_intercept(svm, INTERCEPT_MONITOR); svm_set_intercept(svm, INTERCEPT_MWAIT); } - if (!kvm_hlt_in_guest(vcpu->kvm)) + if (!kvm_hlt_in_guest(vcpu)) svm_set_intercept(svm, INTERCEPT_HLT); control->iopm_base_pa = __sme_set(iopm_base); @@ -1320,7 +1320,7 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm->nested.vmcb12_gpa = INVALID_GPA; svm->nested.last_vmcb12_gpa = INVALID_GPA; - if (!kvm_pause_in_guest(vcpu->kvm)) { + if (!kvm_pause_in_guest(vcpu)) { control->pause_filter_count = pause_filter_count; if (pause_filter_thresh) control->pause_filter_thresh = pause_filter_thresh; @@ -3095,7 +3095,7 @@ static int pause_interception(struct kvm_vcpu *vcpu) */ in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0; - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) grow_ple_window(vcpu); kvm_vcpu_on_spin(vcpu, in_kernel); @@ -4308,7 +4308,7 @@ static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) shrink_ple_window(vcpu); } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 5aadad3e7367..b5133619dea1 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1585,7 +1585,7 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu) * then the instruction is already executing and RIP has already been * advanced. */ - if (kvm_hlt_in_guest(vcpu->kvm) && + if (kvm_hlt_in_guest(vcpu) && vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); } @@ -4120,10 +4120,10 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx) exec_control |= CPU_BASED_CR3_STORE_EXITING | CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_INVLPG_EXITING; - if (kvm_mwait_in_guest(vmx->vcpu.kvm)) + if (kvm_mwait_in_guest(&vmx->vcpu)) exec_control &= ~(CPU_BASED_MWAIT_EXITING | CPU_BASED_MONITOR_EXITING); - if (kvm_hlt_in_guest(vmx->vcpu.kvm)) + if (kvm_hlt_in_guest(&vmx->vcpu)) exec_control &= ~CPU_BASED_HLT_EXITING; return exec_control; } @@ -4202,7 +4202,7 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) } if (!enable_unrestricted_guest) exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; - if (kvm_pause_in_guest(vmx->vcpu.kvm)) + if (kvm_pause_in_guest(vcpu)) exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; if (!kvm_vcpu_apicv_active(vcpu)) exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | @@ -4305,7 +4305,7 @@ static void init_vmcs(struct vcpu_vmx *vmx) vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); } - if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { + if (!kvm_pause_in_guest(&vmx->vcpu)) { vmcs_write32(PLE_GAP, ple_gap); vmx->ple_window = ple_window; vmx->ple_window_dirty = true; @@ -5412,7 +5412,7 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu) */ static int handle_pause(struct kvm_vcpu *vcpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) grow_ple_window(vcpu); /* @@ -6859,7 +6859,7 @@ static int vmx_create_vcpu(struct kvm_vcpu *vcpu) vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); - if (kvm_cstate_in_guest(vcpu->kvm)) { + if (kvm_cstate_in_guest(vcpu)) { vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); @@ -7401,7 +7401,7 @@ static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) shrink_ple_window(vcpu); } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 37529c0c279d..d5d0d99b584e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10941,6 +10941,10 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) #if IS_ENABLED(CONFIG_HYPERV) vcpu->arch.hv_root_tdp = INVALID_PAGE; #endif + vcpu->arch.mwait_in_guest = vcpu->kvm->arch.mwait_in_guest; + vcpu->arch.hlt_in_guest = vcpu->kvm->arch.hlt_in_guest; + vcpu->arch.pause_in_guest = vcpu->kvm->arch.pause_in_guest; + vcpu->arch.cstate_in_guest = vcpu->kvm->arch.cstate_in_guest; r = static_call(kvm_x86_vcpu_create)(vcpu); if (r) @@ -12086,7 +12090,7 @@ bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) vcpu->arch.exception.pending)) return false; - if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) + if (kvm_hlt_in_guest(vcpu) && !kvm_can_deliver_async_pf(vcpu)) return false; /* diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 4abcd8d9836d..0da4b09535a5 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -372,24 +372,24 @@ static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) __rem; \ }) -static inline bool kvm_mwait_in_guest(struct kvm *kvm) +static inline bool kvm_mwait_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.mwait_in_guest; + return vcpu->arch.mwait_in_guest; } -static inline bool kvm_hlt_in_guest(struct kvm *kvm) +static inline bool kvm_hlt_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.hlt_in_guest; + return vcpu->arch.hlt_in_guest; } -static inline bool kvm_pause_in_guest(struct kvm *kvm) +static inline bool kvm_pause_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.pause_in_guest; + return vcpu->arch.pause_in_guest; } -static inline bool kvm_cstate_in_guest(struct kvm *kvm) +static inline bool kvm_cstate_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.cstate_in_guest; + return vcpu->arch.cstate_in_guest; } DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu); From patchwork Tue Dec 21 09:04:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 12689295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F0BBC433F5 for ; Tue, 21 Dec 2021 09:06:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236094AbhLUJGN (ORCPT ); Tue, 21 Dec 2021 04:06:13 -0500 Received: from mail-sn1anam02on2088.outbound.protection.outlook.com ([40.107.96.88]:63537 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234458AbhLUJGJ (ORCPT ); Tue, 21 Dec 2021 04:06:09 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JvnMeRL5rI61GKFIEGLHEY51byWVHlngVrR7mlQ8Bq72vLniyXuSwGkGHnhqze4YCisgLqSCyPsJKr97KWPN8Ceer8DC62m2ccKmByKQPmdSy8gVdS0qSPiXx0bl+q+rg97mhTavLLSF441q0ZsG0c79PU2dcMqAvD57EU96WRp8MXebFDBRyIEtFi20nQgsrvjcsVUobNWZgcmrMoUAWZkFOALh5BEo2z/GRwEk4yRcEBWCdWYcWjlgqqtFt3ze4DoFpIxWTEeJmQ6/RohkFqXkz5D6wFYAqYBm/+o/mCob8bi3bz/r5mzpYBW5kBnO/r977//2FseTAjJANpSrWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=423C2vMgljaXwW8RC2gskLtkzw5Xg8H4m0gx676AlqE=; b=lRTcmSvy9E7boZ2v6D7cfDyi9GyVd9ZebWnL5aCA7sle01tHGDIb007ycWepMMlNb6zUmrHdg0Hevg5Z8h4EfGesN4v2IjZwQue3YgngEpK0VF3rTtsaqvgRttWlmFRCCkYRzl5ejiHa+PATEXK679ezYge41s2PJJA30oFULIWApKGkS9i8yvQB+cP4EjJwEj52Y/OTpX4NEjTkcEJgXUHaBeaTVG6jD0DNV+eEn6ET2rwjUWvGNI6tX3QDWlqivSsU0kKHQgfbR2ZahaPsh1PEYzU1dfvrv7Swwf+PJCHwFo3fXkGH7zfckGD52KAkMZEBk5YkfXG1h2cZ7kkyYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=423C2vMgljaXwW8RC2gskLtkzw5Xg8H4m0gx676AlqE=; b=U6rD9ExTrv/56yyoR9skX7uH7K9fYSTv3v98sP0Ovf+Hz0t4UsRYxZ6WtyruCQjadHXdxZts8Bit96Du06j4Yj/8qbqkg6MHyxgQuaRb0vIVP756+o6aIWgk/JDVDu4+t/bMk6+JiFVlnM+VZ52irqWaEtPvLkkC4TOiHyL36xgdhmDwWjnbMswADCZZsB4g36GqIlOMtnnKaxQIVBTxJ+ZA6qLXVpQwufbASb7xKo5cYOa9qWGiSMK6PCEiAGyO3sEPBtUZKzlj/HoyFJL//iT3McjYShsgwjtbC11bIkBtL74tbLG+Z9T26TqotIbEcIADMrq5KtT9ce0/lQ1t8A== Received: from BN6PR11CA0062.namprd11.prod.outlook.com (2603:10b6:404:f7::24) by PH0PR12MB5402.namprd12.prod.outlook.com (2603:10b6:510:ef::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.16; Tue, 21 Dec 2021 09:06:07 +0000 Received: from BN8NAM11FT006.eop-nam11.prod.protection.outlook.com (2603:10b6:404:f7:cafe::32) by BN6PR11CA0062.outlook.office365.com (2603:10b6:404:f7::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17 via Frontend Transport; Tue, 21 Dec 2021 09:06:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT006.mail.protection.outlook.com (10.13.177.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4801.14 via Frontend Transport; Tue, 21 Dec 2021 09:06:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 21 Dec 2021 09:06:02 +0000 Received: from foundations-user-AS-2114GT-DNR-C1-NC24B.nvidia.com (172.20.187.5) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Tue, 21 Dec 2021 01:06:01 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v2 3/3] KVM: x86: add vCPU ioctl for HLT exits disable capability Date: Tue, 21 Dec 2021 01:04:49 -0800 Message-ID: <20211221090449.15337-4-kechenl@nvidia.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211221090449.15337-1-kechenl@nvidia.com> References: <20211221090449.15337-1-kechenl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd4743b7-f806-4d5c-1588-08d9c4611fc9 X-MS-TrafficTypeDiagnostic: PH0PR12MB5402:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oa3cNNBVZqxhbN3LbLj87BQhmmspGiNnEaeYgNEGYLVRgrv6RONjoPvMGCMUNTs/HXM2yBnXp8hOfaVhlv0Xd1C+rRFII82PJ1B/nlO4RQZX8cWB/wTQPKHvcaIjC3w38fnr/0YDGrzEZMxC4gA+CAIi6fqPZkYzuKQEfexA2Co7wn/NNn24CngU0keS3sg02qMG0/hN3tgKGHxxC8m9Li9CXQXs+gzPKwIUBDAWrJ5ycYGRJ6a+SEj5jVCuByk4/QAzVPU9Z8Ynyc4hw7d1RXOpn7370IibM5yi17jgEzkhn+SlUT8ZIn9S2NLQ8CMQI+C7Tznd9KK2OrQSLzvWckBQXTO27rsjkgk2rmt/ztW0ghimyQp0YGaT/WkTbkGvQg9y7/zwFQ1eSI0+2NEBCGMdfrVfdGFEHRGQVl/XJs6xS3kTh6oVXLUpRBdwU8MGwf3WNeaCTGsYhZwq1/FAD/lErBjcHPKhMi6O3z6jHc0C8ZeFHOSEJFHD76/cepPLHMd8USLW97CRh5yWUO88L52dRiUwnaSeWXGm8M8FqpcKffsPq/wTRV4qzcllZsBxYzsgs+VOXbK2JW8iNTFVeRb4XZPgJ9M5b3HxP/tRPXOeDZXudgL7EnsknKcaUnA4Fn6vlVXMe7iFcT+fDyCVRNbhjcSFrP5BMhu1r24ctiajFd2kNtJRjAIaYWfLk/Hp0Zmdn5SeWTbimsHz5fdAcM9fIiwNCCYsFCbBCLD/uKH62+8N+oj/f76vLmRfk4ih3F3bestzmDcfHhQiJYyEFcuo/6Z02TqBLi/++TOS7pY5coRgMXye5N2U7QOAl57VAJ9a9oH2ZTWWPRWHwJxilA== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(46966006)(40470700002)(36840700001)(2616005)(1076003)(70586007)(4326008)(70206006)(426003)(36860700001)(86362001)(356005)(508600001)(47076005)(5660300002)(82310400004)(81166007)(40460700001)(8676002)(36756003)(8936002)(54906003)(316002)(26005)(16526019)(7696005)(186003)(2906002)(6666004)(83380400001)(110136005)(34020700004)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2021 09:06:07.1904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd4743b7-f806-4d5c-1588-08d9c4611fc9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5402 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce support of vCPU-scoped ioctl with KVM_CAP_X86_DISABLE_EXITS cap for disabling exits to enable finer-grained VM exits disabling on per vCPU scales instead of whole guest. This patch enabled the vCPU-scoped exits control on HLT VM-exits. In use cases like Windows guest running heavy CPU-bound workloads, disabling HLT VM-exits could mitigate host sched ctx switch overhead. Simply HLT disabling on all vCPUs could bring performance benefits, but if no pCPUs reserved for host threads, could happened to the forced preemption as host does not know the time to do the schedule for other host threads want to run. With this patch, we could only disable part of vCPUs HLT exits for one guest, this still keeps performance benefits, and also shows resiliency to host stressing workload running at the same time. In the host stressing workload experiment with Windows guest heavy CPU-bound workloads, it shows good resiliency and having the ~3% performance improvement. Suggested-by: Sean Christopherson Signed-off-by: Kechen Lu --- Documentation/virt/kvm/api.rst | 5 +++-- arch/x86/include/asm/kvm-x86-ops.h | 1 + arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/svm/svm.c | 10 ++++++++++ arch/x86/kvm/vmx/vmx.c | 10 ++++++++++ arch/x86/kvm/x86.c | 12 ++++++++++++ 6 files changed, 38 insertions(+), 2 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index d1c50b95bbc1..b340e36a34f3 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6581,7 +6581,7 @@ branch to guests' 0x200 interrupt vector. :Architectures: x86 :Parameters: args[0] defines which exits are disabled :Returns: 0 on success, -EINVAL when args[0] contains invalid exits - or if any vCPU has already been created + or if any vCPU has already been created for vm ioctl Valid bits in args[0] are:: @@ -6595,7 +6595,8 @@ longer intercept some instructions for improved latency in some workloads, and is suggested when vCPUs are associated to dedicated physical CPUs. More bits can be added in the future; userspace can just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable -all such vmexits. +all such vmexits. vCPUs scoped capability support is also added for +HLT exits. Do not enable KVM_FEATURE_PV_UNHALT if you disable HLT exits. diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-x86-ops.h index cefe1d81e2e8..3e54400535f2 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -121,6 +121,7 @@ KVM_X86_OP_NULL(enable_direct_tlbflush) KVM_X86_OP_NULL(migrate_timers) KVM_X86_OP(msr_filter_changed) KVM_X86_OP_NULL(complete_emulated_msr) +KVM_X86_OP(update_disabled_exits) #undef KVM_X86_OP #undef KVM_X86_OP_NULL diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index edc5fca4d8c8..20a1f34c772c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1498,6 +1498,8 @@ struct kvm_x86_ops { int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); + + void (*update_disabled_exits)(struct kvm_vcpu *vcpu); }; struct kvm_x86_nested_ops { diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 70e393c6dfb5..6cad069a540a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4556,6 +4556,14 @@ static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) sev_vcpu_deliver_sipi_vector(vcpu, vector); } +static void svm_update_disabled_exits(struct kvm_vcpu *vcpu) +{ + if (kvm_hlt_in_guest(vcpu)) + svm_clr_intercept(to_svm(vcpu), INTERCEPT_HLT); + else + svm_set_intercept(to_svm(vcpu), INTERCEPT_HLT); +} + static void svm_vm_destroy(struct kvm *kvm) { avic_vm_destroy(kvm); @@ -4705,6 +4713,8 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .complete_emulated_msr = svm_complete_emulated_msr, .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector, + + .update_disabled_exits = svm_update_disabled_exits, }; static struct kvm_x86_init_ops svm_init_ops __initdata = { diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b5133619dea1..149eb621b124 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7536,6 +7536,14 @@ static bool vmx_check_apicv_inhibit_reasons(ulong bit) return supported & BIT(bit); } +static void vmx_update_disabled_exits(struct kvm_vcpu *vcpu) +{ + if (kvm_hlt_in_guest(vcpu)) + exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_HLT_EXITING); + else + exec_controls_setbit(to_vmx(vcpu), CPU_BASED_HLT_EXITING); +} + static struct kvm_x86_ops vmx_x86_ops __initdata = { .name = "kvm_intel", @@ -7672,6 +7680,8 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { .complete_emulated_msr = kvm_complete_insn_gp, .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector, + + .update_disabled_exits = vmx_update_disabled_exits, }; static __init void vmx_setup_user_return_msrs(void) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d5d0d99b584e..d7b4a3e360bb 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5072,6 +5072,18 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, kvm_update_pv_runtime(vcpu); return 0; + + case KVM_CAP_X86_DISABLE_EXITS: + if (cap->args[0] && (cap->args[0] & + ~KVM_X86_DISABLE_VALID_EXITS)) + return -EINVAL; + + vcpu->arch.hlt_in_guest = (cap->args[0] & + KVM_X86_DISABLE_EXITS_HLT) ? true : false; + + static_call(kvm_x86_update_disabled_exits)(vcpu); + return 0; + default: return -EINVAL; }